KR20080026364A - Plasma display, and driving device and method thereof - Google Patents

Abstract

A plasma display apparatus, and an apparatus and a method for driving thereof are provided to reduce power consumption by applying alternately Vs and zero voltages to X electrodes during sustain period. One end of a first transistor(S2) is connected to plural first electrodes. One end of a second transistor(S1) is connected to a second end of the first transistor and a second end thereof is connected to a first source voltage for supplying a first voltage. One end of a third transistor(S3) is connected to the first electrodes. One end of a fourth transistor(S4) is connected to a second end of the third transistor and a second end thereof is connected to a second source voltage. One ends of first and second inductors(L2,L1) are connected between a contact point between first and second transistors, and third and fourth transistors, respectively. A fifth transistor(S6), which is connected to a third source voltage, forms a path, which increases and decreases the voltage of the first electrodes, through the first inductor. A sixth transistor(S5), connected to a fourth source voltage, forms a path which increases and decreases the voltage of the first electrodes, through the second inductor.

Description

Plasma display device, its driving device and driving method {PLASMA DISPLAY, AND DRIVING DEVICE AND METHOD THEREOF}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 is a diagram illustrating a sustain discharge pulse according to an exemplary embodiment of the present invention.

3 is a schematic view of a sustain discharge circuit according to an exemplary embodiment of the present invention.

4 is a diagram illustrating signal timing of a sustain discharge circuit according to an exemplary embodiment of the present invention.

5A to 5F are diagrams illustrating the operation of the sustain discharge circuit of FIG. 3 according to the signal timing of FIG. 4, respectively.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, a drive device thereof, and a drive method thereof, and more particularly, to an energy recovery circuit of a plasma display device.

The plasma display device is a device that displays characters or images using plasma generated by gas discharge. In the plasma display panel, dozens to millions or more of discharge cells are arranged in a matrix form according to their size. In general, in a plasma display device, one frame is divided into a plurality of subfields to be driven, and a gray level is displayed by a combination of weights of subfields in which a display operation occurs among the plurality of subfields. Cells to be turned on and cells not to be turned on during the address period of each subfield are selected, and sustain discharge is performed on the cells to be turned on to actually display an image during the sustain period.

In order to perform this operation, a high level voltage and a low level voltage are alternately applied to an electrode which performs sustain discharge during the sustain period. At this time, since the two electrodes where the sustain discharge is generated act as capacitive components, reactive power is required to apply a high level voltage or a low level voltage to the electrodes. Therefore, in the sustain discharge circuit of the plasma display device, an energy recovery circuit for recovering and reusing reactive power is used. Conventional energy recovery circuits include those proposed by L.F.Weber (US Pat. Nos. 4,866,349 and 5,081,400). At this time, if a high level voltage (for example, Vs voltage) and a low level voltage (for example, 0 V voltage) are alternately applied to the electrode where sustain discharge is generated, (1/2) Cp (Vs) 2 * 2 High power loss occurs. In addition, the transistor for applying the high level voltage and the low level voltage in the sustain period should have at least a voltage corresponding to the difference between the high level voltage and the low level voltage. Thus, there is a problem in that the cost of the sustain discharge driving circuit is increased due to the transistor having a high breakdown voltage.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a driving circuit of a plasma display device capable of reducing reactive power consumption and using a transistor with low breakdown voltage, and a driving device and a driving method thereof.

According to a feature of the present invention for achieving the above object, a plasma display device is provided. The plasma display device includes a plurality of first electrodes; A first transistor having a first end connected to the plurality of first electrodes; A second transistor having a first end connected to a second end of the first transistor and having a second end connected to a first power supply for supplying a first voltage; A third transistor having a first end connected to the plurality of first electrodes; A fourth transistor having a first end connected to a second end of the third transistor and having a second end connected to a second power supply for supplying a second voltage lower than the first voltage; A first inductor having a first end connected to the contacts of the first and second transistors; A second inductor having a first end connected to the contacts of the third and fourth transistors; A third power supply for supplying a third voltage between the first voltage and an intermediate voltage between the first voltage and the second voltage, and increasing and decreasing the voltage of the first electrode through the first inductor. Fifth transistors each forming a path; And a fourth power supply for supplying a fourth voltage between the first voltage and the second voltage and the second voltage, and increasing and decreasing the voltage of the first electrode through the second inductor. And sixth transistors each forming a path to be made.

According to another feature of the invention there is provided a method of driving a plasma display device comprising a first electrode and a second electrode. The driving method includes the steps of: a) increasing the voltage of the first electrode through a first path comprising a first power supply for supplying a first voltage and a first inductor coupled between the first electrode; b) further increasing the voltage of the first electrode through a second path including a second power supply that supplies a second voltage higher than the first voltage and a second inductor coupled between the first electrode; c) applying a third voltage higher than the second voltage to the first electrode; d) reducing the voltage of the first electrode through a third path including the second inductor; e) further reducing the voltage of the first electrode through a fourth path including the first inductor; And f) applying a fourth voltage lower than the first voltage to the first electrode, wherein the first and fourth paths are second in first stage between the first power source and the first inductor. And a first transistor in which a body diode is formed in a unidirectional direction, wherein the second and third paths have a body diode formed in a direction from a first end to a second end between the second power supply and the second inductor. Further comprising a second transistor, one of the first and fourth paths formed through a body diode of the first transistor, and one of the second and third paths formed through a body diode of the second transistor It includes being.

According to still another feature of the present invention, an apparatus for driving a plasma display device including a first electrode and a second electrode is provided. The drive device includes a first node for supplying a first voltage; A second node supplying a second voltage lower than the first voltage; A first path connected between the first node and the first electrode to form a first path that increases the voltage of the plurality of first electrodes when turned on, and decreases the voltage of the first electrode when turned off; A first transistor forming two paths; A third path connected between the second node and the first electrode to form a third path that increases the voltage of the plurality of first electrodes when turned off, and decreases the voltage of the first electrode when turned on; A second transistor forming four paths; A third transistor formed together with the first transistor to form the first path when turned off and to form the second path when turned on; A fourth transistor formed together with the second transistor to form the third path at turn-on and to form the fourth path at turn-off; A fifth transistor configured to apply a third voltage higher than the first voltage to the first electrode through the first transistor when turned on; And a sixth transistor configured to apply a fourth voltage lower than the second voltage to the first electrode through the second transistor when turned on.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the expression that voltage is maintained throughout the specification indicates that even if the potential difference between two specific points changes over time, the change is within an acceptable range of the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Include cases by. In addition, since the threshold voltage of a semiconductor device (transistor, diode, etc.) is very low compared to the discharge voltage, the threshold voltage is regarded as 0V and approximated.

A plasma display device, a driving device, and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a schematic conceptual view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 2 is a diagram illustrating a sustain discharge pulse according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a sustain electrode driver 400, and a scan electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes (hereinafter referred to as “A electrodes”) A1 to Am extending in the column direction, and a plurality of sustain electrodes extending in pairs to each other in the row direction (hereinafter, “X”). Electrodes ”(X1 to Xn) and scan electrodes (hereinafter referred to as“ Y electrodes ”) (Y1 to Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and the Y electrodes Y1 to Yn and the X electrodes X1 to Xn are orthogonal to the A electrodes A1 to Am. Is arranged to. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms the discharge cell 110.

The controller 200 receives a video signal from the outside and outputs a driving control signal, and divides and drives one frame into a plurality of subfields having respective luminance weights. Each subfield includes an address period and a sustain period. The A electrode, the X electrode, and the Y electrode driver 300, 400, and 500 are each of the A electrodes A1 to Am, the X electrodes X1 to Xn, and the Y electrodes Y1 to the driving control signals from the controller 200. Yn) is applied a driving voltage.

Specifically, during the address period of each subfield, the A electrode, the X electrode, and the Y electrode driver 300, 400, or 500 select a discharge cell to be turned on and a discharge cell not to be turned on from the plurality of discharge cells 110. . During the sustain period of each subfield, as shown in FIG. 2, the X electrode driver 400 maintains and discharges alternately having a high level voltage Vs and a low level voltage 0V at the plurality of X electrodes X1 to Xn. The pulse is applied a number of times corresponding to the weight of the subfield. The Y electrode driver 500 applies a sustain discharge pulse to the plurality of Y electrodes Y1 to Yn in a phase opposite to that of the sustain discharge pulse applied to the X electrodes X1 to Xn.

Next, the sustain discharge circuit for supplying the sustain discharge pulse of FIG. 2 will be described in detail with reference to FIGS. 3, 4 and 5A to 5F.

3 is a schematic diagram of a sustain discharge circuit 410 according to an exemplary embodiment of the present invention. In FIG. 3, for convenience of description, only one X electrode X and one Y electrode Y are illustrated, and a capacitive component formed by the X electrode X and the Y electrode Y is illustrated in the panel capacitor Cp. ). 3, only the sustain discharge circuit 410 connected to the plurality of X electrodes X1 to Xn is illustrated for convenience of description, and the sustain discharge circuit 410 may be formed in the sustain electrode driver 400 of FIG. 1. . In addition, the scan electrode driver 500 connected to the plurality of Y electrodes Y1-Yn may have the same structure as that of the sustain discharge circuit 410 of FIG. 3, and may have a structure different from that of the sustain discharge circuit 410 of FIG. 3. It may be.

The sustain discharge circuit 410 may be commonly connected to the plurality of X electrodes X1 to Xn, or may be connected to only some of the plurality of X electrodes X1 to Xn.

As shown in FIG. 3, the sustain discharge circuit 410 includes transistors S1 to S6, inductors L1 and L2, diodes D1 and D2, and capacitors C1 to C4. In FIG. 3, the transistors S1 to S6 are illustrated as n-channel field effect transistors, in particular, n-channel metal oxide semiconductor (NMOS) transistors, and the body diodes may be formed in the transistors S1 to S6 from a source to a drain direction. have. Instead of the NMOS transistors, other transistors having similar functions may be used as these transistors S1 to S6. In addition, although the transistors S1 to S6 are illustrated as one transistor in FIG. 3, the transistors S1 to S6 may be formed of a plurality of transistors connected in parallel, respectively.

3, the source of the transistor S2 and the drain of the transistor S3 are connected to the X electrode, respectively. The drain of the transistor S2 is connected to the source of the transistor S1, and the drain of the transistor S1 is connected to the power supply Vs supplying the high level voltage of the sustain discharge pulse, that is, the Vs voltage. The source of the transistor S3 is connected to the drain of the transistor S4, and the source of the transistor S4 is connected to the ground terminal 0V supplying the low level voltage of the sustain discharge pulse, that is, the 0V voltage. .

The first end of the inductor L2 is connected to the contact point of the source of the transistor S1 and the drain of the transistor S2, and the second end of the inductor L2 is connected to the drain of the transistor S6. The source of transistor S6 is connected to node A. The first end of the inductor L1 is connected to the contact of the source of the transistor S3 and the drain of the transistor S4, and the second end of the inductor L1 is connected to the source of the transistor S5. The drain of the transistor S5 is connected to the node B.

The capacitors C1 to C4 are connected in series between the power supply Vs and the ground terminal. That is, the first end of the capacitor C1 is connected to the power source Vs, and the second end of the capacitor C1 is connected to the node A. The first end of the capacitor C2 is connected to the node A, the second end of the capacitor C2 is connected to the first end of the capacitor C3, and the second end of the capacitor C3 is the node. Is connected to (B). The first end of the capacitor C4 is connected to the node B, and the second end of the capacitor C4 is connected to the ground terminal. At this time, if the capacitors C1, C2, C3, and C4 have the same capacitance, the capacitors C1, C2, C3, and C4 are charged with the voltage Vs / 4. Thus, node A operates with power supplied by the 3Vs / 4 voltage, and node B operates with power supplied by the Vs / 4 voltage.

The cathode of the diode D2 is connected to the power supply Vs, and the anode of the diode D2 is connected to the second terminal of the inductor L2 and the contact of the source of the transistor S6. The cathode of the diode D1 is connected to the contact of the second end of the inductor L1 and the source of the transistor S5. The diode D2 prevents the voltage D between the transistor S6 and the inductor L2 from rapidly increasing while the current flows from the transistor S6 toward the inductor L2, thereby preventing the diode D1 from exceeding the allowable voltage. The second voltage prevents the voltage between the transistor S5 and the inductor L1 from rapidly decreasing as the current flows from the inductor L1 to the transistor S5, thereby preventing the voltage from exceeding the allowable voltage.

Next, the operation of the sustain discharge circuit 410 of FIG. 3 will be described in detail with reference to FIGS. 4 and 5A to 5H.

4 is a signal timing diagram of the sustain discharge circuit 410 according to an exemplary embodiment of the present invention, and FIGS. 5A to 5H are views illustrating an operation of the sustain discharge circuit 410 of FIG. 3 according to the signal timing of FIG. 4, respectively. to be.

First, referring to FIGS. 4 and 5A, in the mode 1 M1, the transistor S5 is turned on, and as shown in FIG. 5A, the capacitor C4, the transistor S5, the inductor L1, and the transistor S3 are turned on. Resonance occurs in the path of the X electrode of the body diode and the panel capacitor Cp (○ 1). The energy charged in the capacitor C4 by this resonance is injected into the X electrode through the inductor L1, so that the voltage Vx of the X electrode increases from 0V to Vs / 2.

In mode 2 (M2), transistor S5 is turned off and transistor S2 is turned on. As shown in FIG. 5B, the ground terminal, capacitors C4, C3, C2, and body diodes and inductors of transistor S6 ( Resonance occurs in the path of the X electrode of L2), transistor S2 and panel capacitor Cp (○ 2). The energy charged in the capacitors C2 to C4 by this resonance is injected into the X electrode through the inductor L2 so that the voltage Vx of the X electrode increases from the voltage Vs / 2 to the voltage Vs.

In mode 3 M3, transistor S1 is turned on while transistor S2 is turned on, and as shown in FIG. 5C, the power supply Vs, the transistors S1 and S2, and the X electrode of the panel capacitor Cp are turned on. The voltage Vs is applied to the X electrode X through the path (○ 3).

In mode 4 M4, the transistors S1 and S2 are turned off and the transistor S6 is turned on, as shown in FIG. 5D, the X electrode of the panel capacitor Cp, the body diode of the transistor S2, and the inductor L2. ), Resonance occurs in the paths of the transistor S6 and the capacitors C2, C3, and C4 (○ 4). As a result of the resonance, energy stored in the panel capacitor Cp is recovered to the capacitors C2 to C4 through the inductor L2, so that the voltage of the X electrode decreases from the voltage Vs to the voltage Vs / 2.

In mode 5 M5, transistor S6 is turned off and transistor S3 is turned on, as shown in FIG. 5E, the X electrode of the panel capacitor Cp, the transistor S3, the inductor L1, and the transistor S5. Resonance occurs in the path of the body diode and the capacitor C4 of (). As a result of the resonance, energy stored in the panel capacitor Cp is recovered to the capacitor C4 through the inductor L2, so that the voltage of the X electrode decreases from the voltage of Vs / 2 to the voltage of 0V.

In mode 6 (M6), transistor S4 is turned on while transistor S3 is turned on, and as shown in FIG. 5F, 0V voltage is applied to the X electrode through the paths of panel capacitor Cp and transistors S3 and S4. Is applied (○ 6).

As described above, in the exemplary embodiment of the present invention, the mode 1 to mode 6 (M1 to M6) may be repeated as many times as the weight of the corresponding subfield during the sustain period, so that the Vs voltage and the 0V voltage may be alternately applied to the X electrode. .

In the embodiment of the present invention, the voltage Vx of the X electrode is increased from 0V to Vs / 2, and then the voltage Vy of the Y electrode is increased from Vs / 2 to Vs and the voltage Vy of the Y electrode is Vs / 2 at Vs. Since the voltage is lowered to the voltage of Vs / 2 to 0V, power loss of (1/2) Cp (Vs / 2) 2 * 4 occurs. That is, in the embodiment of the present invention, the power loss when the voltages of the Y electrode and the X electrode are directly increased from 0 V voltage to Vs voltage and immediately dropped from Vs voltage to 0 V voltage (1/2) Cp (Vs) 2 * 2 Compared with this, the power loss can be reduced.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, a transistor having a low breakdown voltage can be used and the reactive power consumption can be reduced.

Claims (14)

A plurality of first electrodes; A first transistor having a first end connected to the plurality of first electrodes; A second transistor having a first end connected to a second end of the first transistor and having a second end connected to a first power supply for supplying a first voltage; A third transistor having a first end connected to the plurality of first electrodes; A fourth transistor having a first end connected to a second end of the third transistor and having a second end connected to a second power supply for supplying a second voltage lower than the first voltage; A first inductor having a first end connected to the contacts of the first and second transistors; A second inductor having a first end connected to the contacts of the third and fourth transistors; A third power supply for supplying a third voltage between the first voltage and the second voltage and the first voltage to increase and decrease the voltage of the first electrode through the first inductor; Fifth transistors each forming a path; And A fourth power supply configured to supply a fourth voltage between the intermediate voltage of the first voltage and the second voltage and the second voltage to increase and decrease a voltage of the first electrode through the second inductor; Sixth transistors each forming a path Plasma display device comprising a. The method of claim 1, The fifth and sixth transistors each include a body diode, The fifth transistor forms a path that increases the voltage through the body diode when turned off, and forms a path that decreases the voltage when turned on, And the sixth transistor forms a path that increases the voltage when turned on, and forms a path that decreases the voltage through the body diode when turned off. The method of claim 1, And the first and third transistors each include a body diode. The method according to any one of claims 1 to 3, A first diode having an anode connected to a contact point of the fifth transistor and a first inductor and having a cathode connected to the first power source; And A second diode having a cathode connected to a contact point of the sixth transistor and a second inductor, and an anode connected to the second power source Plasma display device further comprising. The method according to any one of claims 1 to 3, A first capacitor having a first end connected to the first power source; A second capacitor having a first end connected to a second end of the first capacitor; A third capacitor having a first end connected to a second end of the second capacitor; And A fourth capacitor having a first end connected to a second end of the third capacitor and a second end connected to the second power source More, And the first capacitor or the second to fourth capacitors operate with the third power source, and the fourth capacitor or the first to third capacitors operate with the fourth power source. In the method for driving a plasma display device comprising a first electrode and a second electrode, a) increasing the voltage of the first electrode through a first path comprising a first power supply for supplying a first voltage and a first inductor coupled between the first electrode; b) further increasing the voltage of the first electrode through a second path including a second power supply that supplies a second voltage higher than the first voltage and a second inductor coupled between the first electrode; c) applying a third voltage higher than the second voltage to the first electrode; d) reducing the voltage of the first electrode through a third path including the second inductor; e) further reducing the voltage of the first electrode through a fourth path including the first inductor; And f) applying a fourth voltage lower than the first voltage to the first electrode Including; The first and fourth paths are And a first transistor in which a body diode is formed in a direction from a first end to a second end between the first power supply and the first inductor. The second and third paths are And a second transistor having a body diode formed in a direction from a first end to a second end between the second power supply and the second inductor. One of the first and fourth paths is formed through the body diode of the first transistor, One of the second and third paths is formed through a body diode of the second transistor. The method of claim 6, The first and fourth paths are And a third transistor having a body diode formed in a direction opposite to that of the body diode formed in the first transistor between the first inductor and the first electrode. The second and third paths are And a fourth transistor in which a body diode is formed in a direction opposite to the body diode formed in the second transistor between the second inductor and the first electrode. The method of claim 6, Applying the third voltage to the first electrode through a third power supply supplying the third voltage and the second transistor, And driving the fourth voltage to the first electrode through a fourth power supply for supplying the fourth voltage and the first transistor. The method of claim 8, Applying the third voltage to the first electrode, Applying the fourth voltage to the second electrode; Applying the fourth voltage to the first electrode, Applying the third voltage to the second electrode Method of driving a plasma display device comprising a. In an apparatus for driving a plasma display device comprising a first electrode and a second electrode, A first node for supplying a first voltage; A second node supplying a second voltage lower than the first voltage; A first path connected between the first node and the first electrode to increase a voltage of the plurality of first electrodes when turned on, and to decrease a voltage of the first electrode when turned off; A first transistor forming a second path; A third path connected between the second node and the first electrode to form a third path that increases the voltage of the plurality of first electrodes when turned off, and decreases the voltage of the first electrode when turned on; A second transistor forming four paths; A third transistor formed together with the first transistor to form the first path when turned off and to form the second path when turned on; A fourth transistor formed together with the second transistor to form the third path at turn-on and to form the fourth path at turn-off; A fifth transistor configured to apply a third voltage higher than the first voltage to the first electrode through the first transistor when turned on; And A sixth transistor configured to apply a fourth voltage lower than the second voltage to the first electrode through the second transistor at turn-on; Driving device comprising a. The method of claim 10, The first and second paths, A first inductor having a first end coupled to the third transistor and a second end coupled to the first transistor More, The third and fourth paths, A second inductor having a first end connected to a second end of the fourth transistor and a second end connected to the second transistor Driving device further comprising. The method of claim 10, The first, second, fifth and sixth transistors each include a body diode, and a path is formed through the body diode at turn off. The method of claim 11, And a first diode between the contact point of the third transistor and the first inductor and the first power source. And a second diode between the contact point of the fourth transistor and the second inductor and the second power supply. The method according to any one of claims 10 to 13, The fourth voltage is applied to the second electrode while the third voltage is applied to the first electrode, and the third voltage is applied to the second electrode while the fourth voltage is applied to the first electrode. Driven device.

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