KR100646965B1 - Method of manufacturing a flash memory device - Google Patents

Abstract

A method for fabricating a flash memory device is provided to easily bury a trench by avoiding damages to a first polysilicon layer during a device process of a small critical dimension and by lowering an aspect ratio. A tunnel oxide layer(12), a first polysilicon layer(13) and a hard mask layer are sequentially formed on a semiconductor substrate(11). After the hard mask layer, the first polysilicon layer and a predetermined region of the tunnel oxide layer are etched, the exposed semiconductor substrate is etched by a predetermined depth to form a trench. An oxide layer is formed on the resultant structure to bury the trench. The oxide layer and the hard mask layer are polished to expose the first polysilicon layer so that an isolation layer(16) is formed. After a predetermined thickness of the isolation layer is etched to adjust an EFH(effective field height), a dielectric layer(17) and a second polysilicon layer(18) are formed on the resultant structure. The hard mask layer is made of an oxide layer or a compound of an oxide layer and SiON.

Description

Method of Manufacturing a Flash Memory Device

1 to 4 are cross-sectional views sequentially illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 semiconductor substrate 12 tunnel oxide film

13: first polysilicon film 14: hard mask oxide film

15: surface oxide film 16: device isolation film

17 dielectric film 18 second polysilicon film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a NAND flash memory cell, and more particularly, to a method of manufacturing a flash memory device capable of lowering an aspect ratio to facilitate trench filling and preventing etching damage of a first polysilicon film. It is about

As the line width of semiconductors decreases, a device isolation layer and a self-aligning floating gate (STI) method and a self-aligning floating gate method are used in the manufacturing process of a NAND flash memory device having a thickness of 60 nm or less. To form a floating gate. In such a structure, the trench depth and the thickness of the polysilicon film are highly related to the electrical characteristics of the device. However, the narrower the line width, the larger the aspect ratio, which is the ratio of the trench width to the height. This is because the formation speed at the top is faster than the bottom when the material is formed between the device isolation regions, thereby creating a space at the bottom. Will drop.

In addition, the first polysilicon film is damaged when the nitride film is etched on the first polysilicon film. This is because the etching rate of the first polysilicon film doped with phosphorus in the phosphoric acid solution for removing the nitride film is high. In order to prevent such a problem, an oxide film having a buffering function is formed between the first polysilicon film and the nitride film, but there is still a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a flash memory device which can improve the reliability of the device by removing the damage of the first polysilicon film and reducing the aspect ratio during the device processing of the narrow line width, thereby improving the reliability of the device. .

A method of manufacturing a flash memory device according to an embodiment of the present invention may include sequentially forming a tunnel oxide film, a first polysilicon film, and a hard mask film on a semiconductor substrate, wherein the hard mask film, the first polysilicon film, and a tunnel oxide film are sequentially formed. Etching a predetermined region of the semiconductor substrate to form a trench by etching an exposed semiconductor substrate to a predetermined depth, forming an oxide film on the entire structure to fill the trench, and expose the oxide film and hard layer to expose the first polysilicon film. Forming an isolation layer by polishing the mask layer, etching the device isolation layer to a predetermined thickness, and adjusting the EFH to form a dielectric layer and a second polysilicon layer on the entire structure.

The first polysilicon film includes a method of manufacturing a flash memory device formed at 800 to 1200 Å.

The hard mask film includes a method of manufacturing a flash memory device using an oxide film or an oxide film and a SiON mixture.

And a method of manufacturing a flash memory device to polish the first polysilicon film by 50 to 200 microseconds during the polishing process of the oxide film and the hard mask film.

The EFH includes a method of manufacturing a flash memory device of 200 to 400 microseconds.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 4 are cross-sectional views sequentially illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1, a tunnel oxide film 12, a first polysilicon film 13, and a hard mask film 14 are sequentially formed on a semiconductor substrate 11. The hard mask layer 14, the first polysilicon layer 13, and the tunnel oxide layer 12 are etched by a photolithography and an etching process using an element isolation mask to expose a predetermined region of the semiconductor substrate 11, and expose the exposed semiconductor substrate. (11) is etched to a predetermined depth to form a trench. Then, the surface oxide film 15 is formed on the trench sidewalls.

At this time, the first polysilicon film 13 is formed by stacking an undoped polysilicon film and a dope polysilicon film, and has a thickness of 800 to 1200 kPa. In addition, the hard mask film 14 uses an oxide film or an oxide film and a SiON mixture.

Referring to FIG. 2, an oxide film 16A is formed on the entire structure including the trench.

Referring to FIG. 3, the oxide film 16A and the hard mask film 14 are polished by a CMP process so that the first polysilicon film 13 is exposed. At this time, the first polysilicon film 13 is excessively polished to be polished by 50 to 200 kPa. As a result, the device isolation film 16 is formed.

Referring to FIG. 4, the device isolation layer 16 is etched to a predetermined thickness in a wet solution including HF, and a second polysilicon layer 18 is formed after the dielectric layer 17 is formed over the entire structure. At this time, the EFH (Effective Field Height), which is the height B from the surface of the semiconductor substrate 11 to the surface of the device isolation film 16, is 200 to 400 kPa.

As described above, according to the present invention, in the NAND flash memory device isolation process having a narrow line width of 60 nm or less, the trench is formed by lowering the aspect ratio by using an oxide film of the same type as the device isolation film without using a nitride film on the first polysilicon film. It is easy to remove the damage caused by etching of the first polysilicon film to improve the reliability of the device.

Claims (5)

Sequentially forming a tunnel oxide film, a first polysilicon film, and a hard mask film on the semiconductor substrate; Etching a predetermined region of the hard mask layer, the first polysilicon layer, and the tunnel oxide layer, and then etching the exposed semiconductor substrate to a predetermined depth to form a trench; Forming an oxide film over the entire structure to fill the trench; Forming an isolation layer by polishing the oxide layer and the hard mask layer to expose the first polysilicon layer; And Forming a dielectric film and a second polysilicon film on the entire structure after controlling the EFH by etching the device isolation film to a predetermined thickness. The method of claim 1, wherein the first polysilicon film is formed at 800 to 1200 GHz. The method of claim 1, wherein the hard mask film uses an oxide film or an oxide film and a SiON mixture. 2. The method of claim 1, wherein the first polysilicon film is polished by 50 to 200 microseconds during the polishing process of the oxide film and the hard mask film. The method of manufacturing a flash memory device according to claim 1, wherein the EFH is 200 to 400 microseconds.

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