KR100623339B1 - Method for manufacturing nonvolatile memory device - Google Patents

Abstract

The present invention prevents a decrease in program efficiency due to a bird's beak phenomenon at both sides of a tunnel oxide layer, thereby increasing a cell operation margin of a memory device, thereby preventing a device from malfunctioning. The present invention relates to a method for fabricating a device, the method comprising: providing a semiconductor substrate on which a device isolation film is formed; Etching a top corner portion of the device isolation layer in contact with the semiconductor substrate to form a groove; Forming a tunnel oxide layer on the entire structure including the groove; Forming a floating gate on the tunnel oxide layer to fill the groove; It provides a method of manufacturing a nonvolatile memory device comprising sequentially forming a dielectric film and a control gate on the floating gate.

Nonvolatile Memory Devices, EEPROM, Buzz Beek

Description

Method of manufacturing nonvolatile memory device {METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE}             

1 is a cross-sectional view showing a cell formed by a method of manufacturing a nonvolatile memory device according to the prior art.

FIG. 2 is a transmission electron microscope (TEM) diagram illustrating a bird's beak phenomenon generated in the cell shown in FIG. 1. FIG.

3A to 3G are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention.

4 is a TEM diagram of a cell formed in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate

11, 114: device isolation film (or HDP oxide film)

12, 118 tunnel oxide film

13, 119: floating gate

14, 120: dielectric film

15, 121: control gate

111: pad oxide film

112: pad nitride film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device (NVM), and more particularly to a cell of a logic device, i.e., an electrically erasable programmable read-only memory (EEPROM) device implemented in a chip together with a high voltage transistor. It relates to a manufacturing method.

The semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device. Volatile memory devices lose their data when their power supplies are interrupted, such as DRAM (Dynamic Random Access Memory) devices and static RAM (SRAM) devices. Nonvolatile memory devices include memory devices that retain data of the memory device even when a power supply is cut off, such as EEPROM devices and flash devices.

In general, nonvolatile memory devices such as EEPROM devices and flash memory devices have a stacked gate structure that is advantageous for high integration. The stacked gate structure includes a tunnel oxide film, a floating gate, a dielectric film, and a control gate stacked on a semiconductor substrate.

Program operation in such a nonvolatile memory device is performed by F-N tunneling (Fowler-nordheim tunneling) method and hot electron injection (hot electron injection) method. The F-N tunneling method is a method in which a program operation is performed by applying a high electric field to a gate insulating film to inject electrons into a floating gate from a semiconductor substrate. The hot electron injection method is a method in which a hot electron generated in a channel region near a drain is injected into a floating gate to perform a program operation. Meanwhile, an erase operation of the nonvolatile memory device is performed by releasing electrons injected into the floating gate into the semiconductor substrate or the source through a program operation.

Hereinafter, a cell manufacturing method of a nonvolatile memory device according to the prior art will be described with reference to FIG. 1.

As illustrated in FIG. 1, a shallow trench isolation (STI) process is performed to form the device isolation layer 11 in a field region of the substrate 10. Then, a gate electrode composed of the tunnel oxide film 12, the floating gate 13, the dielectric film 14, and the control gate 15 is formed in an active region defined by the device isolation film 11. Here, the tunnel oxide film 12 shows a region where the gate oxide film for the high voltage transistor and the tunnel oxide film of the EEPROM cell overlap. That is, the gate oxide film for the high voltage transistor is composed of a thermal oxide film and a high temperature low pressure dielectric (HLD) film.

However, in the cell manufacturing method of the nonvolatile memory device according to the related art described above, a bird's beak phenomenon occurs in which both sides of the tunnel oxide film 12 swell, as shown in FIG. 16. As shown in FIG. 2, the buzz beak phenomenon is diffused from both sides to the center of the tunnel oxide film 12. As a result, the central portion of the tunnel oxide film 12 is grown thick. This phenomenon occurs because the floating gate 13 is etched and defined, and then the process of forming the dielectric film 14 having the structure of ONO (Oxide / Nitride / Oxide) proceeds to a subsequent process, especially a high temperature for forming an oxide layer, which is a lower layer. It is known that oxygen penetrates into the corner portion of the floating gate 13 during the thermal oxidation process.

As such, when a buzz beak phenomenon occurs at both sides of the tunnel oxide layer 12, the program efficiency is reduced by preventing the introduction of hot electrons injected from the channel region into the floating gate 13 during the program operation, thereby reducing the cell operating margin. Or cause a malfunction of the device.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and prevents the program efficiency from being reduced by the buzz beak phenomenon at both sides of the tunnel oxide film, thereby increasing the cell operating margin of the memory device. It is an object of the present invention to provide a method of manufacturing a nonvolatile memory device capable of preventing a malfunction of the device.

According to an aspect of the present invention, there is provided a semiconductor substrate having an isolation layer formed thereon, forming a groove by etching an upper edge portion of the isolation layer in contact with the semiconductor substrate; Forming a tunnel oxide film along a step of an upper surface of the entire structure including the groove to have a bent portion in the groove, and depositing a floating gate film on the tunnel oxide film so that the groove is filled; Sequentially etching the floating gate layer and the tunnel oxide layer to form a tunnel oxide layer and a floating gate, wherein a portion of the floating gate is formed so that the groove is buried, and a dielectric layer is formed on the floating gate. And forming a control gate over the dielectric layer. It provides a process for the production of surname memory element.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

3A to 3G are cross-sectional views illustrating a method of manufacturing a cell of a memory device to explain a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 3A to 3G are the same elements performing the same function.

As shown in FIG. 3A, the pad oxide layer 111 and the pad nitride layer 112 are sequentially deposited on the substrate 110. In this case, the pad oxide layer 111 may be formed of a substrate 110 by a stress applied during the deposition process of the pad nitride layer 112 or an etching solution (eg, H ₃ PO ₄ ) used during the removal process of the pad nitride layer 112. It functions as a buffer oxide film to prevent the upper surface of the film from being damaged.

Subsequently, as shown in FIG. 3B, after the photoresist is applied on the pad nitride film 112, an exposure and development process using a photo mask is sequentially performed to form a photoresist pattern (not shown). In this case, the photoresist pattern has a profile in which the field region is opened.

Subsequently, an etching process using the photoresist pattern is performed to form a trench 113 by etching the pad nitride layer 112, the pad oxide layer 111, and a portion of the substrate 110.

Subsequently, as shown in FIG. 3C, a high density plasma (HDP) oxide film 114 is deposited on the entire structure of the device 113 so as to fill the trench 113.

Subsequently, the chemical mechanical polishing (CMP) process is performed to planarize the HDP oxide film 114.

Subsequently, as illustrated in FIG. 3D, an etching process 115 using phosphoric acid (H ₃ PO ₄ ) is performed to remove the exposed pad nitride film 112 (see FIG. 3C) to expose the pad oxide film 111.

Subsequently, as illustrated in FIG. 3E, the pad oxide layer 111 is removed by performing a cleaning process 116 using a mask in which only the cell array region is opened, and at the same time, the upper edge portion of the HDP oxide layer 114 is removed. A recessed groove (or gap) 117 is formed. At this time, the etching solution used in the cleaning process 116 is quickly penetrated into the interface between the upper edge portion of the HDP oxide film 114 and the substrate 110 as compared with other portions to form the groove 117. Here, the cleaning process 116 is performed for at least 100 seconds using DHF (diluted HF, a mixture of HF and H ₂ O) solution to the upper edge portion of the HDP oxide film 114 to the upper surface of the substrate 110 Recess to a depth of 200 kPa to 400 kPa as a reference. That is, the groove 117 formed in the corner portion of the HDP oxide film 114 is formed to a depth of 200 kPa to 400 kPa.

Subsequently, as shown in FIG. 3F, a thermal oxidation process is performed on the entire structure to form the tunnel oxide film 118. In this case, the tunnel oxide film 118 is formed along a step inside the groove 117 formed in the upper corner portion of the HDP oxide film 114.

Subsequently, a floating gate polysilicon film 119 is deposited on the tunnel oxide film 118. In this case, the polysilicon layer 119 is deposited on the tunnel oxide layer 118, but is preferably deposited to fill the groove formed in the upper edge portion of the HDP oxide layer 114. This is to prevent the buzz beak from being diffused into the active region when oxygen penetrates into the tunnel oxide film 118 and causes the buzz beak in the subsequent formation of the ONO structure dielectric film 120 (see FIG. 3G). That is, as shown in FIG. 4, in the dielectric film 120 forming process, when the oxygen is penetrated, when the lateral oxidation occurs from both ends of the tunnel oxide film 118 to the center, the groove 117 is buried. The diffusion of the horizontal oxide is prevented through the polysilicon film 119 which is formed to be. Here, the polysilicon film 119 is deposited by using a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ gas (if undoped) or Si ₂ H ₆ and PH ₃ gas (doped).

Subsequently, as shown in FIG. 3G, a photoresist is coated on the polysilicon layer 119, and then a photoresist pattern (not shown) is formed by performing an exposure and development process using a photomask. At this time, the photoresist pattern is a pattern mask for a gate electrode.

Next, an etching process using a photoresist pattern is performed to etch the polysilicon film 119 and the tunnel oxide film 118. Thus, the floating gate 119 is defined.

Subsequently, the ONO structure dielectric film 120 is formed to cover the floating gate 119. At this time, the oxide film, which is the upper and lower layers of the dielectric film 120, is composed of DCS (Dichloro Silane; SiH ₂ Cl ₂ ) and N ₂ O gas having excellent internal pressure and excellent Time Depedent Dielectric Breakdown (TDDB) characteristics. It is deposited by hot temperature oxide at a temperature of 800 ℃ to 900 ℃. The nitride layer, which is an intermediate layer of the dielectric film 120, has a high step coverage of CVD (Chemical Vapor Deposition) and PECVD (Plasma Enhanced CVD) under a low pressure of 1 tor to ₃ torr and a temperature of about 650 ° C to 800 ° C using DCS and NH ₃ gas Or deposition by APCVD (Atmospheric Pressure CVD) method.

Subsequently, a control gate polysilicon film 121 is deposited on the dielectric film 120. In this case, the polysilicon film 121 may be formed in the same manner as the polysilicon film 119 for the floating gate.

Subsequently, an etching process is performed by a blanket or etch back method to etch the polysilicon layer 121 and the dielectric layer 120. Thus, the control gate 121 is defined.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by forming a groove in the corner portion of the HDP oxide film in contact with the substrate, by depositing a polysilicon film for floating gate so that the groove is buried by the penetration of oxygen during the subsequent dielectric film forming process It is possible to prevent horizontal oxidation (i.e., buzz beak phenomenon) that is diffused from both ends of the tunnel oxide film to the center portion.

Therefore, the thickening of the tunnel oxide film caused by the buzz beak phenomenon is prevented, thereby smoothly inducing the hot electron injection operation through the tunnel oxide film through the tunnel oxide film during the program operation, thereby increasing the program efficiency and increasing the cell operation margin of the memory device. In this way, malfunction of the device can be prevented.

Claims (7)

Providing a semiconductor substrate on which an isolation layer is formed; Etching a top corner portion of the device isolation layer in contact with the semiconductor substrate to form a groove; Forming a tunnel oxide film along a step of an upper surface of the entire structure including the groove to have a bend in the groove; Depositing a floating gate film on the tunnel oxide film so as to fill the groove; Sequentially etching the floating gate film and the tunnel oxide film to form a tunnel oxide film and a floating gate, wherein a portion of the floating gate is formed so that the grooves are buried; Forming a dielectric film on the floating gate; And Forming a control gate on the dielectric layer Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, The groove is formed by performing an etching process using a DHF solution. The method of claim 2, The etching process is performed for at least 100 seconds to 200 seconds. The method according to claim 1 or 2, The groove is a method of manufacturing a nonvolatile memory device to form a depth of 200 ~ 400Å. The method of claim 1, wherein forming the device isolation layer, Sequentially depositing a pad oxide film and a pad nitride film on the semiconductor substrate; Etching a portion of the pad nitride layer, the pad oxide layer, and the semiconductor substrate to form a trench; Depositing an oxide film for device isolation so that the trench is buried; And Removing the pad nitride layer to expose the pad oxide layer; Method of manufacturing a nonvolatile memory device comprising a. The method of claim 5, wherein And the pad oxide layer is removed during the groove forming process. The method of claim 1, And the dielectric film is formed in an ONO structure.

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