KR20060005177A - A gate electrode of nonvolatile memory device and a method for forming the same - Google Patents

Abstract

The present invention relates to a gate electrode of a nonvolatile memory device and a method of forming the same, and the present invention provides a thinner tunnel oxide layer at a portion where hot carrier injection is generated, through the region during a program operation. Make tunneling easy to occur. Therefore, in the present invention, the program operation speed can be increased quickly.

In addition, the present invention increases the junction area between the dielectric film, the floating gate and the control gate by forming a plurality of grooves on the floating gate. Therefore, in the present invention, the program / erase operation speed can be increased by maximizing the coupling ratio between the control gate and the floating gate.

Nonvolatile Memory Devices, Flash Memory Devices, Coupling Ratio, Hot Carriers

Description

A gate electrode of a nonvolatile memory device and a method of forming the same {A GATE ELECTRODE OF NONVOLATILE MEMORY DEVICE AND A METHOD FOR FORMING THE SAME}

1 to 15 are cross-sectional views illustrating a gate electrode and a method of forming the nonvolatile memory device according to an exemplary embodiment of the present invention.

16 and 17 are diagrams for describing respective coupling ratios of cells of a general flash memory device.

         <Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 11 first film

12, 15, 18: 1st polysilicon film 13: 2nd film

14: first polysilicon film 14a: groove

16 dielectric film 17 second polysilicon film

19 gate electrode 113 tunnel oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate electrode of a nonvolatile memory device and a method of forming the same, and more particularly to a gate electrode of a nonvolatile memory device and a method of forming the same that can improve the program operation speed of the device.

In general, program and erase operations of a stack type flash memory device, which is a nonvolatile memory device, are performed as follows. First, a program operation is performed by generating a hot carrier through the side of the drain region, and injecting the hot carrier thus generated into the floating gate through the tunnel oxide film. In addition, the erase operation is performed by using FN tunneling generated by a high electric field between a source region and a floating gate, or a bulk and the floating gate, to remove electrons injected into the floating gate. By releasing.

As such, during the program and erase operations of the flash memory device, a high voltage must be applied to the gate. In this case, the driving of the low voltage is severely limited. This is because the bias voltage cannot be directly applied to the floating gate directly, only through the control gate. That is, the voltage drop is caused by an inter poly oxide (IPO) (hereinafter, referred to as a 'dielectric film') formed between the control gate and the floating gate. This voltage drop depends on the thickness and the junction area of the dielectric film.

On the other hand, the ratio of capacitance is called a coupling ratio. When the coupling ratio is "1", it means that the bias voltage applied to the control gate is applied to the floating gate as it is without a voltage drop. This means that the bias voltage applied to the control gate to drive the memory cell must be higher by that amount.

For reference, the coupling ratio of each terminal will be described with reference to FIGS. 16 and 17. 16 is a cross-sectional view illustrating a gate electrode of a flash memory device, and FIG. 17 is an equivalent circuit diagram of FIG. 16. Equation 1 includes a gate coupling ratio (α _G ), a drain coupling ratio (α _D ), a source coupling ratio (α _S ), and a body coupling ratio (Body) coupling ratio, α _B ) is shown.

As shown in Equations 1, 16, and 17, the coupling ratio in the memory cell is greatly influenced by the thickness of the dielectric film and the junction area between the dielectric film and the gate. In order to increase the coupling ratio of the dielectric film, the junction area between the gate and the dielectric film should be increased or the thickness of the dielectric film should be made thin. However, reducing the cell dimension to reduce the size of the memory chip naturally reduces the junction area between the gate and the dielectric film, and reducing the thickness of the data chip results in data retention characteristics. This deterioration problem occurs.

Accordingly, the present invention has been made to solve the above problems, and a gate electrode of a nonvolatile memory device and a method for forming the same, which can increase the coupling ratio by increasing the junction area between the gate and the dielectric film without changing the cell size. The purpose is to provide.

Another object of the present invention is to provide a gate electrode of a nonvolatile memory device capable of improving the program operation speed of a cell by controlling the thickness of a tunnel oxide film and a method of forming the same.

According to an aspect of the present invention for realizing the above object, a tunnel oxide film formed on a semiconductor substrate, a thin portion is formed, a floating gate formed on the tunnel oxide film, a plurality of grooves formed on the top, A dielectric film formed along a step of an upper surface of the floating gate including a plurality of grooves, a control gate formed on the dielectric film, and a source / drain region formed on the semiconductor substrate exposed to both sides of the control gate. A gate electrode of a nonvolatile memory device is provided.                     

In addition, according to another aspect of the present invention for achieving the above object, forming a tunnel oxide film having a different thickness on the semiconductor substrate, forming a first polysilicon film for the floating gate in the tunnel oxide film and Etching a portion of the first polysilicon film to form a plurality of grooves thereon; forming a dielectric film along a step of an upper surface of the entire structure including the first polysilicon film; and forming a dielectric film on the dielectric film. Forming a second polysilicon film for a control gate, patterning the second polysilicon film for the control gate, the dielectric film, the first polysilicon film for the floating gate, and the tunnel oxide film to define a gate electrode; Forming a source region and a drain region on the semiconductor substrate exposed by both sidewalls of the gate electrode; A method of forming a gate electrode of a nonvolatile memory device including a system is provided.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 to 15 are cross-sectional views illustrating a gate electrode and a method of forming the nonvolatile memory device according to an exemplary embodiment of the present invention. The same reference numerals among the reference numbers described below are the same elements performing the same function.                     

Referring to FIG. 1, a semiconductor substrate 10 cleaned by a pretreatment cleaning process is provided. The pretreatment cleaning process is performed with DHF (Diluted HF) followed by SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O), or with BOE (Buffer Oxide Etchant) followed by SC-1 It can be carried out as.

Then, an ion implantation process for forming a well and an ion implantation process for adjusting a threshold voltage are performed. Before performing the ion implantation processes, a sacrificial oxide (not shown) is deposited on the semiconductor substrate 10, and an ion implantation process is performed using the sacrificial oxide film as a screen oxide. As a result, a well region (not shown) is formed in the semiconductor substrate 10. Here, the well region may be formed in a triple structure.

Then, a tunnel oxide film 11 (hereinafter referred to as 'first film') is formed on the semiconductor substrate 10. Here, the first film 11 may be formed in a temperature range of 750 ° C to 800 ° C by a wet oxidation process.

Then, an annealing process using N ₂ gas is performed for 20 minutes to 30 minutes in the temperature range of 900 ° C. to 910 ° C. with respect to the first film 11 to minimize the defect density with the interface of the semiconductor substrate 10. You may.

Referring to FIG. 2, a photoresist is applied over the entire structure on which the first film 11 is formed, followed by an exposure and development process using a photo mask to form a photoresist pattern 12. In this case, the photoresist pattern 12 is formed so that a portion of the first film 11 is exposed, where a portion where the first film 11 is exposed is a portion where hot carrier injection occurs.

Referring to FIG. 3, an etching process using the photoresist pattern 12 as an etching mask is performed to pattern and remove the exposed first film 11. In this case, the etching process is preferably performed by a wet etching method so as not to damage the upper surface of the semiconductor substrate 10.

Referring to FIG. 4, a tunnel oxide film 13 (hereinafter referred to as a “second film”) that is thinner than the thickness of the first film 11 on the exposed semiconductor substrate 10 using the photoresist pattern 12 as a mask. Form). In this case, the second layer 13 may be formed by a wet oxidation process similarly to the first layer 11. As such, by reducing the thickness of the tunnel oxide layer at the site where the hot carrier injection occurs, the tunneling of the electrons occurs more easily during the program operation of the device, so that the electron trap, that is, the hot carrier injection, occurs more quickly, thereby increasing the program operation speed. do.

Referring to FIG. 5, the post resist pattern 12 is removed by performing a strip process.

Referring to FIG. 6, a polysilicon film 14 for floating gate (hereinafter, referred to as a 'first polysilicon film') is deposited on the first and second films 11 and 13. In this case, the first polysilicon film 14 may be deposited as an undoped amorphous silicon film having low oxidation resistance or a low concentration doped amorphous silicon film having a low doping concentration. Here, the undoped amorphous silicon film may be deposited at a thickness of 1000 kPa to 3000 kPa at a low pressure of 0.1torr to 0.3torr in the temperature range of 480 ° C to 550 ° C using SiH ₄ gas by LPCVD (Low Pressure Chemical Vapor Deposition) method. Can be. The doped amorphous silicon film may be deposited to a thickness of 1000 kPa to 3000 kPa at a low pressure of 0.1torr to 0.3torr in a temperature range of 480 ° C to 550 ° C using Si ₂ H ₆ and PH ₃ gas by LPCVD.

Referring to FIG. 7, after the photoresist is coated on the entire structure on which the first polysilicon layer 14 is formed, the photoresist pattern 15 is formed by performing exposure and development processes using a photomask.

Referring to FIG. 8, an etching process using the photoresist pattern 15 is performed to form a plurality of grooves 14a on the first polysilicon film 14 to have an uneven shape. Here, the reason for forming the groove 14a may be a dielectric film (see '16' of FIG. 10), a floating gate, a dielectric film 16, and a control formed on the first polysilicon film 14 through a subsequent process. This is to increase the capacitance between the gates (see 'FG' in FIGS. 16 and 17).

Referring to FIG. 9, a strip process is performed to remove the photoresist pattern 15.

Referring to FIG. 10, the dielectric film 16 is deposited along a step of the top surface of the first polysilicon film 14 having the grooves 14a formed therein. In this case, the dielectric film 16 may be formed of an oxide film / nitride film / oxide film (SiO ₂ / Si ₃ N ₄ / SiO ₂ ). In addition, the oxide film may be deposited as a high temperature oxide film using DCS (Dichloro Silane; SiH ₂ Cl ₂ ) and N ₂ O gas having excellent internal pressure and TDDB (Time Depedent Dielectric Breakdown) characteristics. In this case, the deposition condition is a process condition having good step coverage under the low pressure of 0.1torr to 3torr and the temperature of about 810 ° C to 850 ° C by loading the semiconductor substrate 10 in a temperature atmosphere of 600 ° C to 700 ° C. The deposition may be performed using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atmospheric pressure CVD (APCVD). On the other hand, the nitride film can be deposited by a CVD, PECVD or APCVD method with excellent step coverage under a low pressure of 1torr to 3torr and a temperature of about 650 ℃ to 800 ℃ using DCS and NH ₃ gas.

Referring to FIG. 11, a control gate polysilicon film 17 (hereinafter referred to as a second polysilicon film) is formed on the entire structure including the dielectric film 16. In this case, the second polysilicon film 17 may be formed under the same deposition conditions as the first polysilicon film 14. However, although not shown, in the case where the tungsten silicide film is formed thereon in order to lower the resistance of the second polysilicon film 17, the tungsten silicide film is replaced with the dielectric film 16 during the tungsten silicide film forming process to form the dielectric film 16. Doped and undoped films to prevent the diffusion of hydrofluoric acid, which can increase the thickness of the oxide layer, the top layer, and to prevent the formation of a WPx layer formed through the combination of tungsten (W) and phosphorus (P). It can be formed into a double structure of (doped and undoped). In this case, an amorphous silicon film is formed using a CVD, PECVD, or APCVD method at a temperature of about 510 ° C to 550 ° C and a pressure of 1.0torr to 3.0torr. When the second polysilicon film 17 is formed in a two-layer structure as described above, a dopant film is formed using SiH ₄ or SiH ₆ and PH ₃ gas, and then the PH ₃ gas is blocked and continuously It is preferable to form an undoped film.

Referring to FIG. 12, after the photoresist is coated on the entire structure of the second polysilicon layer 17, the photoresist pattern 18 is formed by performing exposure and development processes using a photomask.

Referring to FIG. 13, an etching process using the photoresist pattern 18 as an etching mask is performed to form the second polysilicon layer 17, the dielectric layer 16, the first polysilicon layer 14, and the first and first layers. The two films 11 and 13 are etched to define the gate electrode 19. Hereinafter, the first and second films 11 and 13 patterned by an etching process for defining the gate electrode 19 are referred to as tunnel oxide films (see 113 in FIG. 15).

Referring to FIG. 14, a strip process is performed to remove the photoresist pattern 18.

Subsequently, although not shown, a source / drain ion implantation process may be performed to form a source / drain region (not shown) in the semiconductor substrate 10 exposed to the sidewall of the gate electrode 19.

For example, the process for forming the source / drain region may further include forming a spacer (not shown) for lightly doped drain (LDD) high temperature low pressure dielectric (LDD) on both sidewalls of the gate electrode 19. The source / drain regions may be formed in a double structure. In this case, the source / drain ion implantation process performs a low concentration ion implantation process to form a low concentration junction region, and then forms spacers on both side walls of the gate electrode 19, and then uses the spacers as a mask to form a high concentration junction region. It can be carried out by forming a process.

15 is a cross-sectional view of a gate electrode of a nonvolatile memory device formed through the process of FIGS. 1 to 14. As shown in FIG. 15, the tunnel oxide film 113 is not uniformly formed to have the same thickness. The thickness of the portion where the hot carrier injection is generated (that is, the drain region side) is made thinner so that tunneling easily occurs through the portion during the program operation. This can speed up the program operation speed. In addition, by forming a plurality of grooves 14a on the floating gate 14, the bonding area between the dielectric film 16, the floating gate 14, and the control gate 17 is increased to reduce the coupling ratio at this portion. It is possible to increase.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the thickness of the tunnel oxide film is made thinner at the site where the hot carrier injection is generated, so that tunneling is easily generated through the site during the program operation, thereby increasing the program operation speed. You can take it quickly.

In addition, according to the present invention, a plurality of grooves are formed on the floating gate to increase the junction area between the dielectric film, the floating gate, and the control gate, thereby maximizing the coupling ratio between the control gate and the floating gate, thereby increasing the program / erase operation speed. Can be increased.

Claims (4)

A tunnel oxide film formed on the semiconductor substrate and having a thin portion; A floating gate formed on the tunnel oxide film and having a plurality of grooves formed thereon; A dielectric film formed along a step of an upper surface of the floating gate including the plurality of grooves; A control gate formed on the dielectric layer; And And a source / drain region formed in the semiconductor substrate exposed to both sides of the control gate. The method of claim 1, The thin portion of the tunnel oxide layer is a gate electrode of a non-volatile memory device that is a hot carrier injection occurs during the program operation. (a) forming tunnel oxide films having different thicknesses on the semiconductor substrate; (b) forming a first polysilicon film for a floating gate on the tunnel oxide film; (c) etching a portion of the first polysilicon film to form a plurality of grooves on the top; (d) forming a dielectric film along a step of an upper surface of the entire structure including the first polysilicon film; (e) forming a second polysilicon film for a control gate on the dielectric film; (f) patterning the second polysilicon film for the control gate, the dielectric film, the first polysilicon film for the floating gate, and the tunnel oxide film to define a gate electrode; And (g) forming a source region and a drain region in the semiconductor substrate exposed by both sidewalls of the gate electrode. The method of claim 3, wherein step (a) comprises: (a-1) forming a first film on the semiconductor substrate; (a-2) etching and removing a portion of the first film; And (A-3) A method of forming a gate electrode of a nonvolatile memory device comprising forming a second film thinner than the first film on a portion where the first film is removed.

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