KR100582442B1 - LDD structure transistor and its manufacturing method - Google Patents

Abstract

The present invention relates to a lightly doping drain (LDD) structure transistor and a method of manufacturing the same. More specifically, a gate poly is formed in a silicon substrate rather than a surface of a silicon substrate to form a gate poly. The present invention relates to a method of manufacturing a MOS transistor that suppresses the occurrence of a threshold voltage drop and a leakage current by keeping the channel length short even if the size is reduced.

In the LDD structure transistor of the present invention and a method of manufacturing the same, in the transistor manufacturing method, a hole 20 is formed in a region in which a gate electrode 22 is to be formed by a trench process, and a field 21 for separating an active region is formed. The first step includes forming a gate oxide film in the hole 20, forming a gate electrode 22 thereon, and performing a third step of implanting ions for source / drain formation of each device. Has technical features.

Accordingly, the LDD structure transistor of the present invention and a method of manufacturing the same can be expanded by using a silicon trench to extend the channel length of a gate poly and a transistor formed on a silicon surface using a gate in a semiconductor device process that is becoming increasingly finer. By preventing the voltage drop and suppressing the leakage current according to the reduction in the length, there is an effect that the device margin for forming a gate electrode of a smaller length can be obtained.

LDD, Transistor

Description

LED structure transistor and its manufacturing method             

1 illustrates a conventional LDD structure transistor and a method of manufacturing the same.

2 illustrates an LDD structure transistor of the present invention and a method of manufacturing the same.

(Explanation of symbols for the main parts of the drawing)

10, 21: field 11, 22: gate poly (electrode)

       20: hall

The present invention relates to a lightly doping drain (LDD) structure transistor and a method of manufacturing the same. More specifically, a gate poly is formed in a silicon substrate rather than a surface of a silicon substrate to form a gate poly. The present invention relates to a method of manufacturing a MOS transistor that suppresses the occurrence of a threshold voltage drop and a leakage current by keeping the channel length short even if the size is reduced.

Since the LDD may have a low concentration of impurity distribution between the drain and the channel, the LDD may minimize the hot carrier effect or the punch through effect, and may secure the reliability of the semiconductor device. However, the device is characterized by a complicated process and difficult to obtain a sufficiently high voltage.

A method of manufacturing a conventional MOS transistor is described below with reference to FIG. 1.

FIG. 1A shows a first process of manufacturing a prior art MOS transistor, which forms a field 10 that separates the active region using a trench process. In other words, the formation of finely recessed grooves in the silicon wafer is called a trench, which is a field in which a beam is irradiated onto a substrate by a deflection scanner in an electron beam drawing apparatus by separating an active region from an inactive region using this process. 10) form. Here, the active region is divided into a high voltage device region and a low voltage device region. A high voltage NMOS transistor is formed in the high voltage device region, and a low voltage NMOS transistor and a low voltage PMOS transistor are formed in the low voltage device region.

FIG. 1B shows a second process of manufacturing a MOS transistor of the prior art, in which a gate oxide film and a gate electrode 11 are formed. As the gate size becomes smaller, ion implantation is performed to control the impurity concentration in the source / drain region in order to obtain a desired threshold voltage. In the ion implantation process, the impurity concentration used is greater than 4.0E12 to 4.0E13 dose and the energy is smaller than 50 to 150 KeV to form an N + type impurity layer in the high voltage device region, and an N + type impurity in the low voltage device region. Form a layer.

FIG. 1C shows a third process of manufacturing a conventional MOS transistor, which is a process of implanting ions into an NMOS and a PMOS, and performing source / drain ion implantation. The ion implantation process includes a process of implanting threshold voltage control ions, a process of implanting channel stop formation ions, and a process of implanting well formation ions. A photoresist pattern for masking NMOS or PMOS is sequentially formed to inject ions, and the ion implantation blocking layer is used to inject ions into the NMOS and PMOS, respectively, to control the threshold voltage ion doping region, and to prevent punch through ion doping. A region, an ion doped region for channel stop formation, and an ion doped region for well formation are formed.

However, the conventional method of manufacturing a semiconductor device as described above requires a channel having a smaller and smaller size as technology advances, and as the channel becomes shorter, a threshold voltage is lowered and a lot of leakage current is generated. In addition, as shown in the Republic of Korea Patent No. 0352930 and Republic of Korea Patent No. 0361534, the ion implantation process is added to compensate for the lowered threshold voltage, there is a problem in that the process is added to suppress the leakage current.

Accordingly, the present invention is to solve the problems of the prior art as described above, even if the gate poly (Gate Poly) is formed in the silicon substrate rather than the surface of the silicon substrate (Substrate), even if the size of the gate poly is small It is an object of the present invention to suppress the occurrence of threshold voltage drop and leakage current by keeping the length short.

The above object of the present invention is a first process of forming a field 21 for separating a hole 20 and an active region, which are regions in which a gate electrode 22 is to be formed, on a semiconductor substrate in a region where a gate is to be formed. ; A second process of forming a gate oxide film in the hole 20 and forming a gate electrode 22 thereon; A third step of forming a spacer 23 on sidewalls of the gate electrode 22; And a fourth step of performing ion implantation for forming a source / drain of each device using the spacers 23 as a mask.

Details of the above object and technical configuration of the present invention and the resulting effects thereof will be more clearly understood by the following detailed description with reference to FIG. 2, which shows a preferred embodiment of the present invention.

FIG. 2A shows a first process of manufacturing the MOS transistor of the present invention, in which the hole 20 is formed using a trench in the region where the gate electrode 22 is to be formed. At this time, the length of the channel may be adjusted using a trench in the lower portion of the gate electrode. Then, a plurality of trenches are connected to form a capacitor composed of a gate poly-oxide-silicon bulk. Then, by using a trench process, the active region is separated from the inactive region to form a field 21 in which the beam can be irradiated onto the substrate by a deflection scanner in the electron beam writing apparatus. Here, the active region is divided into a high voltage device region and a low voltage device region. A high voltage NMOS transistor is formed in the high voltage device region, and a low voltage NMOS transistor and a low voltage PMOS transistor are formed in the low voltage device region.

Fig. 2B shows a second process of manufacturing the MOS transistor of the present invention, in which the gate oxide film is formed in the hole 20 and the gate poly 22 is formed thereon. As mentioned above, a difference occurs in the length of the portion to be a channel according to the depth of the hole 20. For example, the deeper the hole 20, the longer the channel, while the shallower the channel, the shorter the channel. Therefore, the ion implantation process of adjusting the threshold voltage by impurity implantation can be omitted, thereby simplifying the process and suppressing the occurrence of the threshold voltage drop and leakage current. In addition, problems such as management problems in the ion implantation process, problems caused by diffusion of ion particles, and outgassing may be solved.

  FIG. 2C is a third step of manufacturing the MOS transistor of the present invention, in which ions are implanted into the NMOS and the PMOS, where source / drain ion implantation is performed using a spacer as a mask. At this time, the ion implantation energy for forming the source / drain region is preferably 10keV to 100keV.

Accordingly, the LDD structure transistor of the present invention and a method of manufacturing the same can be used to reduce the gate length in a semiconductor device process that is becoming more and more miniaturized by allowing the channel lengths of the transistors formed on the gate poly and the silicon surface to be extended using silicon trenches. The voltage drop prevention and the leakage current suppression according to the present invention have an effect of having a device margin for forming a gate electrode having a smaller length.

Claims (6)

In the LDD structure transistor manufacturing method, A first step of simultaneously forming a hole 21, which is a region where the gate electrode 22 is to be formed, and a field 21, which separates the active region, from the trench etching process on the semiconductor substrate; A second process of forming a gate oxide film in the hole 20 and forming a gate electrode 22 thereon; A third step of forming a spacer 23 on sidewalls of the gate electrode 22; And A fourth process of implanting ions for source / drain formation of each device using the spacers 23 as a mask LDD structure transistor manufacturing method comprising a The method of claim 1, In the first process, a length of a channel may be adjusted by using a trench in a lower portion of the gate electrode 22. The method of claim 1, In the first process, a plurality of trenches are connected to form a capacitor including a gate poly-oxide-silicon bulk. The method of claim 1, The second process is a method of manufacturing an LDD structure transistor, characterized in that the gate poly (22) to form a channel in the silicon sub using a trench process in silicon. The method of claim 1, In the second process, the threshold voltage is controlled by the structure of the hole 20 formed by the trench process. delete

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