KR100575335B1 - Contact hole formation method of semiconductor memory device - Google Patents

Contact hole formation method of semiconductor memory device Download PDF

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KR100575335B1
KR100575335B1 KR1019980045183A KR19980045183A KR100575335B1 KR 100575335 B1 KR100575335 B1 KR 100575335B1 KR 1019980045183 A KR1019980045183 A KR 1019980045183A KR 19980045183 A KR19980045183 A KR 19980045183A KR 100575335 B1 KR100575335 B1 KR 100575335B1
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contact hole
forming
etching process
semiconductor memory
memory device
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KR20000027280A (en
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홍성훈
김민규
박승희
김태규
김상수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 메모리 소자의 콘택 홀 형성 방법에 관한 것임.The present invention relates to a method of forming a contact hole in a semiconductor memory device.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

종래의 메탈 콘택은 1단계의 식각 레시피를 통하여 형성되는데, 셀 지역에 비해 주변 영역의 낮은 단차를 갖는 부분에서 기판이 손실되어 누설 전류가 발생하므로써 소자의 수율이 저하되는 문제점이 있음.Conventional metal contacts are formed through a one-step etch recipe, whereby the substrate is lost in a portion having a lower step height in the peripheral region than in the cell region, resulting in a decrease in yield of devices due to leakage current.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

종래의 1단계 식각 레시피로 콘택을 형성한 후, 장비를 변경하여 새로운 레시피로 2단계 식각을 실시하여 콘택을 형성하므로써, 기판 손실로 인한 누설 전류를 감소시킬 수 있고 소자의 수율을 향상시킬 수 있음.By forming a contact with a conventional one-step etch recipe and then changing the equipment to form a contact by performing a two-step etch with a new recipe, leakage current due to substrate loss can be reduced and device yield can be improved. .

Description

반도체 메모리 소자의 콘택 홀 형성 방법Contact hole formation method of semiconductor memory device

본 발명은 반도체 메모리 소자의 콘택 홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a contact hole in a semiconductor memory device.

일반적으로 플래쉬 메모리 셀은 다음과 같은 공정으로 형성된다. 즉, 셀 영역과 주변 영역에 게이트를 형성한 후, 게이트 양측벽에 스페이서를 형성한다. 이후, N+ 이온 주입 공정을 통해 NMOS 트랜지스터 영역에 N+접합 영역을 형성하고 P+ 이온 주입 공정을 통해 PMOS 트랜지스터 영역에 P+ 접합 영역을 형성한다. 다음에, 폴리간 산화막을 형성하고, BPSG막을 형성한 후 평탄화한다. 이후, 콘택 홀 형성용 마스크를 이용한 식각 공정으로 콘택을 형성한다.Generally, flash memory cells are formed by the following process. That is, after the gate is formed in the cell region and the peripheral region, spacers are formed on both side walls of the gate. Since, N + by an ion implantation process to form a N + junction region in the NMOS transistor region and to form a P + junction region in the PMOS transistor region over the P + ion implantation step. Next, an interpoly oxide film is formed, and a BPSG film is formed and then planarized. Thereafter, the contact is formed by an etching process using a contact hole forming mask.

이 콘택 홀 형성 공정은 단일 장비에서 진행되며, 400mT의 압력, 1300W의 전력에서 40CHF3, 70CF4, 600Ar을 이용하여 33초 동안 진행된다.The contact hole formation process is performed in a single device and is performed for 33 seconds using 40CHF 3 , 70CF 4 and 600Ar at a pressure of 400mT and a power of 1300W.

이러한 콘택 홀 형성 공정시 셀 영역에 비해 주변 영역의 BPSG막의 단차가 낮아지게 되며, 이 부분의 기판이 손실되어 누설 전류 발생의 원인이 된다. 이 누설 전류는 스탠바이 전류를 증가시키며, 이에 의해 소자의 특성 및 수율이 저하하는 문제점이 있다.In the contact hole forming process, the step difference of the BPSG film in the peripheral area is lower than that in the cell area, and the substrate of this part is lost, which causes leakage current. This leakage current increases the standby current, thereby degrading the characteristics and yield of the device.

따라서, 본 발명은 종래의 1단계 식각 레시피로 콘택을 형성한 후, 장비를 변경하여 새로운 레시피로 2단계 식각을 실시하여 콘택을 형성하므로써, 기판 손실로 인한 누설 전류를 감소시킬 수 있고 소자의 수율을 향상시킬 수 있는 반도체 메모리 소자의 콘택 홀 형성 방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, after forming a contact with a conventional one-step etch recipe, by changing the equipment to form a contact by performing a two-step etch with a new recipe, the leakage current due to substrate loss can be reduced and the yield of the device can be reduced. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor memory device capable of improving the efficiency.

상술한 목적을 달성하기 위한 본 발명의 제 1 실시예에 따른 반도체 메모리 소자의 콘택 홀 형성 방법은 반도체 메모리 소자의 금속 배선 형성 등을 위한 콘택 홀을 형성 방법에 있어서, 제 1 식각 장비를 이용하여 1단계 식각 공정을 실시하는 단계와, 제 2 식각 장비를 이용하여 2단계 식각 공정을 실시하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A method of forming a contact hole in a semiconductor memory device according to a first embodiment of the present invention for achieving the above object is a method of forming a contact hole for forming a metal wiring of a semiconductor memory device, by using a first etching equipment And performing a two-step etching process using the second etching equipment.

또한, 상술한 목적을 달성하기 위한 본 발명의 제 2 실시예에 따른 반도체 메모리 소자의 콘택 홀 형성 방법은 반도체 메모리 소자의 금속 배선 형성 등을 위한 콘택 홀을 형성 방법에 있어서, 제 1 식각 장비를 이용하여 1단계 식각 공정을 실시하는 단계와, 제 2 식각 장비를 이용하여 각기 레시피가 다른 3과정의 2단계 식각 공정을 실시하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In addition, the contact hole forming method of the semiconductor memory device according to the second embodiment of the present invention for achieving the above object in the method for forming a contact hole for forming the metal wiring of the semiconductor memory device, the first etching equipment Performing a one-step etching process using the second step, and performing a two-step etching step of three different processes using different recipes.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1은 종래의 콘택 홀 형성 방법에 따른 식각 프로파일을 설명하기 위한 도면이다.1 is a view for explaining an etching profile according to a conventional contact hole forming method.

도시된 바와 같이, 종래의 1단계 식각 공정만으로 콘택을 형성하게 되면, 식각 프로파일이 불량한 것을 알 수 있다.As shown, when the contact is formed only by the conventional one-step etching process, it can be seen that the etching profile is poor.

본 발명의 제 1 실시예에서는 종래의 문제점을 해결하기 위해, 종래의 제 1 식각 장비를 이용한 1단계 식각 공정 후 제 2 식각 장비를 이용하여 새로운 레시피로 2단계 식각 공정을 실시한다.In the first embodiment of the present invention, in order to solve the conventional problems, after performing the first step etching process using the conventional first etching equipment, a second step etching process using a new recipe using a second etching equipment.

즉, 1단계 식각 공정을 400mT의 압력, 1300W의 전력에서 40CHF3, 70CF4, 600Ar을 이용하여 33초 동안 진행한다. 다음에 장비를 변경하여, 250 내지 400mT의 압력, 1300W의 전력에서 40 내지 60 CHF3, 30 내지 70CF4, 400 내지 600Ar을 이용하여 33 내지 66초 동안 2단계 식각 공정을 실시한다.That is, the one-step etching process is performed for 33 seconds using 40CHF 3 , 70CF 4 , 600Ar at 400mT pressure and 1300W power. Next, the equipment is changed to perform a two-step etching process for 33 to 66 seconds using 40 to 60 CHF 3 , 30 to 70CF 4 , 400 to 600 Ar at a pressure of 250 to 400 mT and a power of 1300 W.

또는, 본 발명의 제 2 실시예로 제 1 식각 장비를 이용한 1단계 식각 공정 후, 제 2 장비를 이용하여 레시피를 각각 달리한 3과정의 2단계 식각 공정을 실시한다.Alternatively, after the one-step etching process using the first etching equipment according to the second embodiment of the present invention, a three-step two-step etching process using different recipes is performed using the second equipment.

즉, 1단계 식각 공정을 400mT의 압력, 1300W의 전력에서 40CHF3, 70CF4, 600Ar을 이용하여 33초 동안 진행한다. 다음에 장비를 변경하여, 1450Wb의 압력, 2500 내지 3000의 고주파 전력에서 40C2F6을 이용하여 33초 동안 2단계 식각 공정의 제 1 과정을 진행한 후, 1450Wb의 압력, 2500 내지 3000의 고주파 전력에서 95O2를 이용하여 3초 동안 2단계 식각 공정의 제 2 과정을 진행한 다음, 300Wb의 압력, 2500 내지 3000의 고주파 전력에서 95O2를 이용하여 45초 동안 2단계 식각 공정의 제 3 과정을 진행한다.That is, the one-step etching process is performed for 33 seconds using 40CHF 3 , 70CF 4 , 600Ar at 400mT pressure and 1300W power. Next, after changing the equipment, proceed to the first step of the two-step etching process for 33 seconds using 40C 2 F 6 at a pressure of 1450Wb, high frequency power of 2500 to 3000, and then the pressure of 1450Wb, high frequency of 2500 to 3000 After the second process of the two-step etching process for 3 seconds using 95O 2 in power, the third process of the two-step etching process for 45 seconds using 95O 2 at a pressure of 300Wb, high frequency power of 2500 to 3000 Proceed.

도 2는 본 발명의 콘택 홀 형성 방법에 따른 식각 프로파일을 설명하기 위한 도면으로, 이상에서 설명한 것과 같은 방법으로 콘택을 형성한 경우 식각 프로파일이 개선되었음을 알 수 있다.2 is a view for explaining an etching profile according to the contact hole forming method of the present invention, it can be seen that the etching profile is improved when the contact is formed in the same manner as described above.

상술한 바와 같이, 본 발명에 따르면 1단계의 식각 공정 후 장비를 변경하여 2단계 식각 공정을 후속으로 진행하므로써, 셀 주변 영역의 단차로 인한 기판 손실을 방지할 수 있어 누설 전류의 발생을 감소시킬 수 있다. 이에 따라 소자의 특성 및 수율이 향상되는 탁월한 효과가 있다.As described above, according to the present invention, by changing the equipment after the one-step etching process and subsequently performing the two-step etching process, it is possible to prevent the substrate loss due to the step difference in the area around the cell, thereby reducing the occurrence of leakage current. Can be. Accordingly, there is an excellent effect of improving the characteristics and yield of the device.

도 1은 종래의 콘택 홀 형성 방법에 따른 식각 프로파일을 설명하기 위한 도면.1 is a view for explaining an etching profile according to a conventional contact hole forming method.

도 2는 본 발명의 콘택 홀 형성 방법에 따른 식각 프로파일을 설명하기 위한 도면.2 is a view for explaining an etching profile according to the method for forming a contact hole of the present invention.

Claims (6)

반도체 메모리 소자의 금속 배선 형성 등을 위한 콘택 홀을 형성 방법에 있어서,In the method for forming a contact hole for forming the metal wiring of the semiconductor memory device, etc. 제 1 식각 장비에서 CHF3, CF4 및 Ar 가스를 혼합한 혼합 가스를 이용하여 1단계 식각 공정을 실시하는 단계와,Performing a one-step etching process using a mixed gas of CHF 3 , CF 4, and Ar gas in the first etching equipment; 제 2 식각 장비에서 상기 1 단계 식각 공정에서 사용된 동일한 상기 혼합 가 스를 이용하여 2단계 식각 공정을 실시하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 메모리 소자의 콘택 홀 형성 방법.And performing a two-step etching process using the same mixed gas used in the one-step etching process in the second etching equipment. 제 1 항에 있어서,The method of claim 1, 상기 1단계 식각 공정은 400mT의 압력, 1300W의 전력에서 40CHF3, 70CF4, 600Ar을 이용하여 33초 동안 진행하는 것을 특징으로 하는 반도체 메모리 소자의 콘택 홀 형성 방법.The one-step etching process is performed for 33 seconds using 40CHF 3 , 70CF 4 , 600Ar at a pressure of 400mT, power of 1300W. 제 1 항에 있어서,The method of claim 1, 상기 2단계 식각 공정은 250 내지 400mT의 압력, 1300W의 전력에서 40 내지 60 CHF3, 30 내지 70CF4, 400 내지 600Ar을 이용하여 33 내지 66초 동안 진행하는 것을 특징으로 하는 반도체 메모리 소자의 콘택 홀 형성 방법.The two-step etching process is performed for 33 to 66 seconds using 40 to 60 CHF 3 , 30 to 70CF 4 , 400 to 600Ar at a pressure of 250 to 400mT and a power of 1300W. Forming method. 반도체 메모리 소자의 금속 배선 형성 등을 위한 콘택 홀을 형성 방법에 있어서,In the method for forming a contact hole for forming the metal wiring of the semiconductor memory device, etc. 제 1 식각 장비를 이용하여 1단계 식각 공정을 실시하는 단계와,Performing a one-step etching process using the first etching equipment, 제 2 식각 장비를 이용하여 각기 레시피가 다른 3과정의 2단계 식각 공정을 실시하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 메모리 소자의 콘택 홀 형성 방법.A method of forming a contact hole in a semiconductor memory device, comprising the step of performing a two-step etching process of three processes having different recipes using second etching equipment. 제 4 항에 있어서,The method of claim 4, wherein 상기 1단계 식각 공정은 400mT의 압력, 1300W의 전력에서 40CHF3, 70CF4, 600Ar을 이용하여 33초 동안 진행하는 것을 특징으로 하는 반도체 메모리 소자의 콘택 홀 형성 방법.The one-step etching process is performed for 33 seconds using 40CHF 3 , 70CF 4 , 600Ar at a pressure of 400mT, power of 1300W. 제 4 항에 있어서,The method of claim 4, wherein 상기 레시피가 다른 3과정의 2단계 식각 공정은 1450Wb의 압력, 2500 내지 3000의 고주파 전력에서 40C2F6을 이용하여 33초 동안 진행하는 제 1 과정과,The three-step two-step etching process of the recipe is different, the first process proceeds for 33 seconds using 40C 2 F 6 at a pressure of 1450Wb, high frequency power of 2500 to 3000, 1450Wb의 압력, 2500 내지 3000의 고주파 전력에서 95O2를 이용하여 3초 동안 진행하는 제 2 과정과,A second process for 3 seconds using 95O 2 at a pressure of 1450 Wb and a high frequency power of 2500 to 3000; 300Wb의 압력, 2500 내지 3000의 고주파 전력에서 95O2를 이용하여 45초 동안 진행하는 제 3 과정을 포함하여 이루어지는 것을 특징으로 하는 반도체 메모리 소자의 콘택 홀 형성 방법.And a third step of performing 45 seconds using 95O 2 at a pressure of 300 Wb and a high frequency power of 2500 to 3000.
KR1019980045183A 1998-10-27 1998-10-27 Contact hole formation method of semiconductor memory device KR100575335B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0360121A (en) * 1989-07-28 1991-03-15 Sony Corp Dry etching
JPH03291929A (en) * 1990-04-09 1991-12-24 Nippon Telegr & Teleph Corp <Ntt> Dry etching method
JPH0491432A (en) * 1990-08-02 1992-03-24 Sony Corp Magnetron rie apparatus
JPH04273435A (en) * 1991-02-28 1992-09-29 Sony Corp Dry etching method
JPH05234932A (en) * 1992-02-26 1993-09-10 Nec Corp Manufacture of semiconductor device and semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0360121A (en) * 1989-07-28 1991-03-15 Sony Corp Dry etching
JPH03291929A (en) * 1990-04-09 1991-12-24 Nippon Telegr & Teleph Corp <Ntt> Dry etching method
JPH0491432A (en) * 1990-08-02 1992-03-24 Sony Corp Magnetron rie apparatus
JPH04273435A (en) * 1991-02-28 1992-09-29 Sony Corp Dry etching method
JPH05234932A (en) * 1992-02-26 1993-09-10 Nec Corp Manufacture of semiconductor device and semiconductor device

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