KR100571330B1 - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR100571330B1
KR100571330B1 KR1020017004519A KR20017004519A KR100571330B1 KR 100571330 B1 KR100571330 B1 KR 100571330B1 KR 1020017004519 A KR1020017004519 A KR 1020017004519A KR 20017004519 A KR20017004519 A KR 20017004519A KR 100571330 B1 KR100571330 B1 KR 100571330B1
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KR
South Korea
Prior art keywords
signal
clock
input
timing
clock signal
Prior art date
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Expired - Fee Related
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KR1020017004519A
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English (en)
Korean (ko)
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KR20010080083A (ko
Inventor
이케다히토시
후지오카신야
사토야수하루
마츠자키야스로우
Original Assignee
후지쯔 가부시끼가이샤
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Publication date
Application filed by 후지쯔 가부시끼가이샤 filed Critical 후지쯔 가부시끼가이샤
Publication of KR20010080083A publication Critical patent/KR20010080083A/ko
Application granted granted Critical
Publication of KR100571330B1 publication Critical patent/KR100571330B1/ko
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
KR1020017004519A 1998-10-13 1999-09-20 반도체 장치 Expired - Fee Related KR100571330B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP98-290811 1998-10-13
JP29081198A JP4034886B2 (ja) 1998-10-13 1998-10-13 半導体装置
PCT/JP1999/005114 WO2000022626A1 (fr) 1998-10-13 1999-09-20 Dispositif a semi-conducteur

Publications (2)

Publication Number Publication Date
KR20010080083A KR20010080083A (ko) 2001-08-22
KR100571330B1 true KR100571330B1 (ko) 2006-04-17

Family

ID=17760799

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020017004519A Expired - Fee Related KR100571330B1 (ko) 1998-10-13 1999-09-20 반도체 장치

Country Status (4)

Country Link
US (1) US6498522B2 (enExample)
JP (1) JP4034886B2 (enExample)
KR (1) KR100571330B1 (enExample)
WO (1) WO2000022626A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100424118B1 (ko) * 2001-05-03 2004-03-24 주식회사 하이닉스반도체 클럭 신호의 주파수 정보를 이용하여 셀 동작을 제어하는동기식 반도체 메모리 장치
EP1446910B1 (en) * 2001-10-22 2010-08-11 Rambus Inc. Phase adjustment apparatus and method for a memory device signaling system
JP2005049970A (ja) * 2003-07-30 2005-02-24 Renesas Technology Corp 半導体集積回路
KR20050032365A (ko) 2003-10-01 2005-04-07 삼성전자주식회사 플래시메모리카드
JP2006053981A (ja) * 2004-08-11 2006-02-23 Fujitsu Ltd 記憶装置、記憶装置リード方法
DE102006012654B4 (de) * 2006-03-20 2008-02-07 Infineon Technologies Ag Taktfrequenzvariation eines getakteten Stromverbrauchers
JP2008048214A (ja) * 2006-08-17 2008-02-28 Toshiba Corp 半導体装置
JP5563183B2 (ja) * 2007-02-15 2014-07-30 ピーエスフォー ルクスコ エスエイアールエル 半導体メモリ集積回路
JP2009016017A (ja) * 2007-07-09 2009-01-22 Samsung Electronics Co Ltd 半導体集積回路
US8817072B2 (en) 2010-03-12 2014-08-26 Sony Corporation Disparity data transport and signaling
CN114217193B (zh) * 2020-09-04 2025-01-21 中国科学院微电子研究所 与非门树结构
CN116844620B (zh) * 2022-03-23 2024-05-03 长鑫存储技术有限公司 一种信号采样电路以及半导体存储器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748553A (en) * 1995-09-26 1998-05-05 Nec Corporation Semiconductor memory device having extended margin in latching input signal

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0737389A (ja) * 1993-07-20 1995-02-07 Mitsubishi Electric Corp 半導体装置
KR0158762B1 (ko) * 1994-02-17 1998-12-01 세키자와 다다시 반도체 장치
JP2616567B2 (ja) * 1994-09-28 1997-06-04 日本電気株式会社 半導体記憶装置
JP3778993B2 (ja) * 1995-05-16 2006-05-24 ヒューレット・パッカード・カンパニー 最小論理マルチプレクサ・システム
JP2874619B2 (ja) * 1995-11-29 1999-03-24 日本電気株式会社 半導体記憶装置
JP3986578B2 (ja) * 1996-01-17 2007-10-03 三菱電機株式会社 同期型半導体記憶装置
JP2924797B2 (ja) * 1996-06-14 1999-07-26 日本電気株式会社 半導体装置
JP3612634B2 (ja) * 1996-07-09 2005-01-19 富士通株式会社 高速クロック信号に対応した入力バッファ回路、集積回路装置、半導体記憶装置、及び集積回路システム
JP4090088B2 (ja) 1996-09-17 2008-05-28 富士通株式会社 半導体装置システム及び半導体装置
US6002282A (en) * 1996-12-16 1999-12-14 Xilinx, Inc. Feedback apparatus for adjusting clock delay
JPH10228772A (ja) * 1997-02-18 1998-08-25 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH11120768A (ja) * 1997-10-09 1999-04-30 Toshiba Corp 半導体集積回路
US5970020A (en) * 1998-09-16 1999-10-19 G-Link Technology Controlling the set up of a memory address

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748553A (en) * 1995-09-26 1998-05-05 Nec Corporation Semiconductor memory device having extended margin in latching input signal

Also Published As

Publication number Publication date
KR20010080083A (ko) 2001-08-22
JP4034886B2 (ja) 2008-01-16
JP2000123570A (ja) 2000-04-28
WO2000022626A1 (fr) 2000-04-20
US20010021141A1 (en) 2001-09-13
US6498522B2 (en) 2002-12-24

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