KR100555452B1 - Manufacturing method of semiconductor device which can reduce contact resistance - Google Patents
Manufacturing method of semiconductor device which can reduce contact resistance Download PDFInfo
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- KR100555452B1 KR100555452B1 KR1019980043696A KR19980043696A KR100555452B1 KR 100555452 B1 KR100555452 B1 KR 100555452B1 KR 1019980043696 A KR1019980043696 A KR 1019980043696A KR 19980043696 A KR19980043696 A KR 19980043696A KR 100555452 B1 KR100555452 B1 KR 100555452B1
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- plug
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- conductive film
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- contact hole
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 19
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 17
- 229910052721 tungsten Inorganic materials 0.000 claims description 17
- 239000010937 tungsten Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- LSCACAQJPBCKDI-UHFFFAOYSA-N B1B=[C-]C=C1.[Ti+4].B1B=[C-]C=C1.B1B=[C-]C=C1.B1B=[C-]C=C1 Chemical compound B1B=[C-]C=C1.[Ti+4].B1B=[C-]C=C1.B1B=[C-]C=C1.B1B=[C-]C=C1 LSCACAQJPBCKDI-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
콘택 저항을 감소시킬 수 있는 반도체 장치의 제조방법이 개시된다. 반도체 기판 상에 하부 도전영역을 형성한다. 하부 도전영역이 형성된 기판 위에 절연막을 형성하고, 절연막을 패터닝하여 하부 도전영역을 노출시키는 콘택홀을 형성한다. 노출된 도전영역 및 콘택홀의 전표면에 금속장벽막을 형성하고, 금속장벽막 상에 콘택홀을 매립하는 플러그용 도전막를 형성한다. 절연막 상에 형성된 플러그용 도전막 및 금속장벽막을 제거하여 콘택홀 내에 플러그를 형성한다. 플러그와 접촉하는 도전막을 절연막 상에 형성한다. 도전막 형성시 설정된 진공상태를 그대로 유지하면서 도전막을 리플로우하여 플러그 내에 형성된 틈을 채운다.A method of manufacturing a semiconductor device capable of reducing contact resistance is disclosed. A lower conductive region is formed on the semiconductor substrate. An insulating film is formed on the substrate on which the lower conductive region is formed, and the insulating film is patterned to form a contact hole exposing the lower conductive region. A metal barrier film is formed on the exposed conductive region and the entire surface of the contact hole, and a plug conductive film for filling the contact hole is formed on the metal barrier film. The plug conductive film and the metal barrier film formed on the insulating film are removed to form a plug in the contact hole. A conductive film in contact with the plug is formed on the insulating film. The conductive film is reflowed to fill the gap formed in the plug while maintaining the vacuum state set when the conductive film is formed.
Description
본 발명은 반도체 장치의 제조방법에 관한 것으로 특히, 콘택홀을 통하여 상호연결되는 배선 구조를 갖는 반도체 장치의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a wiring structure interconnected through a contact hole.
반도체 집적회로의 배선구조는 하부 배선 위에 형성된 절연막 내에 콘택홀이 형성되고, 절연막 위에 형성된 상부 배선이 콘택홀을 통하여 하부 배선과 접촉한다.In the wiring structure of the semiconductor integrated circuit, a contact hole is formed in the insulating film formed on the lower wiring, and the upper wiring formed on the insulating film contacts the lower wiring through the contact hole.
도 1을 참조하면, 반도체 기판(2) 위에 제1 절연막(4)이 형성되어 있고, 제1 절연막(4) 위에는 하부 배선(6)이 형성되어 있다. 하부 배선(6) 위에는 콘택홀(10)을 내재한 제2 절연막(8)이 형성되어 있고, 콘택홀(10)을 매립하며 하부 배선(6)과 접촉하는 플러그(14)가 형성되어 있다. 제2 절연막(8) 위로 플러그(14)와 접촉하는 상부 배선(16)이 형성되어 있다. Referring to FIG. 1, a first insulating film 4 is formed on a semiconductor substrate 2, and a lower wiring 6 is formed on the first insulating film 4. A second insulating film 8 having a contact hole 10 is formed on the lower wiring 6, and a plug 14 filling the contact hole 10 and contacting the lower wiring 6 is formed. An upper wiring 16 is formed on the second insulating film 8 to contact the plug 14.
하부 배선(6) 및 상부 배선(16)은 주로 알루미늄 또는 알루미늄 합금으로 형성한다. 그리고 플러그(14)는 매우 작은 크기의 콘택홀(10) 내에 형성되어야 하기 때문에 텅스텐으로 매립한다. The lower wiring 6 and the upper wiring 16 are mainly formed of aluminum or an aluminum alloy. The plug 14 is embedded in tungsten because it is to be formed in the contact hole 10 of a very small size.
따라서 다른 종류의 금속 물질이 접촉하는 접촉영역들이 존재한다. 다시 말하면, 하부 배선(6)과 텅스텐 플러그(14) 사이의 첫 번째 접촉영역 및 텅스텐 플러그(14)와 상부 배선(16) 사이의 두 번째 접촉영역에서는 서로 다른 금속 물질들, 예컨대 알루미늄과 텅스텐이 접촉하게 된다. 서로 다른 종류의 금속 물질들이 접촉하는 영역은 같은 종류의 금속 물질들이 접촉하는 영역보다 전기적 특성이 나쁘다.Thus, there are contact areas in which different kinds of metal materials come into contact. In other words, in the first contact region between the lower wiring 6 and the tungsten plug 14 and in the second contact region between the tungsten plug 14 and the upper wiring 16, different metal materials such as aluminum and tungsten are deposited. Contact. Regions where metal materials of different kinds contact each other have worse electrical characteristics than regions where metal materials of the same type contact each other.
그 이유는 서로 다른 종류의 금속 물질 사이에 기본적인 저항 차이가 존재하여 접촉영역에서는 금속 물질 내의 캐리어(carrier)의 이동에 불연속(discontinuity)이 발생하기 때문이다. 예를 들어, 하부 배선(6)에서 상부 배선(16)으로 흐르는 전류를 인가하게되면, 상부 배선(16)을 통하여 흐르는 전자에 의하여 상부 배선(16) 원자가 이동하게 된다. 그러나, 이러한 상부 배선(16) 원자의 이동은 텅스텐 플러그(14)와 상부 배선(16) 사이의 접촉영역에서 저지된다. The reason for this is that there is a fundamental resistance difference between different kinds of metal materials, and discontinuity occurs in the movement of carriers in the metal material in the contact region. For example, when a current flowing from the lower wiring 6 to the upper wiring 16 is applied, atoms of the upper wiring 16 are moved by electrons flowing through the upper wiring 16. However, this movement of the upper wiring 16 atoms is prevented in the contact area between the tungsten plug 14 and the upper wiring 16.
더욱이, 텅스텐 플러그(14)를 형성하는 과정에서도 텅스텐 내에 틈(seam)(14a)이 불가피하게 형성되어 하부배선(6), 플러그(14) 및 상부배선(16)간의 콘택 저항을 증가시킨다.Further, even in the process of forming the tungsten plug 14, a gap 14a is inevitably formed in the tungsten to increase the contact resistance between the lower wiring 6, the plug 14 and the upper wiring 16.
본 발명이 이루고자 하는 기술적 과제는 콘택 저항을 감소시킬수 있는 반도체 장치의 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a semiconductor device capable of reducing contact resistance.
상기 기술적 과제를 해결하기 위해 본 발명의 일실시예에 따른 반도체 장치의 제조방법은 반도체 기판 상에 하부 도전영역을 형성하는 단계와, 하부 도전영역이 형성된 기판 위에 절연막을 형성하는 단계와, 절연막을 패터닝하여 하부 도전영역을 노출시키는 콘택홀을 형성하는 단계와, 노출된 도전영역 및 콘택홀의 전표면에 금속장벽막을 형성하는 단계와, 금속장벽막 상에 콘택홀을 매립하는 플러그용 도전막를 형성하는 단계와, 절연막 상에 형성된 플러그용 도전막 및 금속장벽막을 제거하여 콘택홀 내에 플러그를 형성하는 단계와, 플러그와 접촉하는 도전막을 절연막 상에 형성하는 단계와, 도전막을 형성하는 단계에서는 설정된 진공상태를 그대로 유지하면서 상기 도전막을 리플로우하는 단계를 구비한다.In order to solve the above technical problem, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a lower conductive region on a semiconductor substrate, forming an insulating film on the substrate on which the lower conductive region is formed, Forming a contact hole exposing the lower conductive region by patterning, forming a metal barrier film on the entire surface of the exposed conductive region and the contact hole, and forming a plug conductive film filling the contact hole on the metal barrier film; Forming a plug in the contact hole by removing the plug conductive film and the metal barrier film formed on the insulating film, forming the conductive film in contact with the plug on the insulating film, and forming the conductive film. Reflowing the conductive film while maintaining the same.
금속장벽막을 형성하는 단계는 콘택홀이 형성되어 있는 결과물 전면에 금속장벽 물질을 화학 기상 증착법으로 증착하여 콘택홀의 측면 및 밑면을 따라 정합하도록 형성한다. The forming of the metal barrier film is performed by depositing the metal barrier material on the entire surface of the resultant in which the contact hole is formed by chemical vapor deposition to match the side and bottom surfaces of the contact hole.
금속장벽 물질은 티타늄 나이트라이드(TiN), 티타늄 텅스텐(TiW), 텅스텐 나이트라이드(WN) 또는 티타늄 디보로라이드(TiB₂)이다.Metal barrier materials are titanium nitride (TiN), titanium tungsten (TiW), tungsten nitride (WN) or titanium diborolide (TiB2).
플러그용 도전막을 형성하는 단계는 화학적 기상 증착법으로 형성한다.The step of forming the plug conductive film is formed by chemical vapor deposition.
플러그용 도전막은 텅스텐(W) 또는 구리(Cu)로 형성된다.The plug conductive film is formed of tungsten (W) or copper (Cu).
도전막은 알루미늄 또는 알루미늄 합금으로 형성한다.The conductive film is formed of aluminum or aluminum alloy.
리플로우 단계는 도전막을 형성하는 물질을 플러그로 이동시켜 플러그 내에 형성된 틈을 채운다. The reflow step moves the material forming the conductive film to the plug to fill the gap formed in the plug.
리플로우 단계는 500℃ 내지 660℃의 온도로 60초 내지 120초 동안 리플로우한다. The reflow step reflows for 60 seconds to 120 seconds at a temperature of 500 ° C to 660 ° C.
이와같은 본 발명의 반도체 장치는 콘택홀의 텅스텐 플러그와 알루미늄 도전막사이의 콘택 저항을 감소시킬 수 있다. Such a semiconductor device of the present invention can reduce the contact resistance between the tungsten plug of the contact hole and the aluminum conductive film.
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 한정되어지는 것으로 해석되어져서는 안된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되어지는 것이다. 따라서, 도면에서의 막의 두께 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면 상에서 동일한 부호로 표시된 요소는 동일한 구성요소를 의미한다. 또한 어떤 막이 다른 막 또는 반도체 기판의 "상"에 있다 또는 접촉하고 있다라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the thickness of the film and the like in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same components. Also, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 2 내지 도 5는 본 발명의 일실시예의 공정순서에 따라 배선을 제조하는 방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method of manufacturing a wire according to a process sequence of an embodiment of the present invention.
도 2를 참조하면, 반도체 기판(102) 위에 예를 들면, 실리콘 산화막 또는 다른 적합한 절연물질로 제1 절연막(104)을 형성한다. 제1 절연막(104) 위에, 도전물질을 증착하고 패터닝하여 하부 도전막(106)을 형성한다. 하부 도전막(106)은 알루미늄 합금, 구리, 티타늄, 텅스텐 또는 다른 적합한 금속물질로 구성한다. 하부 도전막(106) 위에 제2 절연막(108)을 형성한다. 일반적으로 제2 절연막(108)은 실리콘 산화막, 예컨대 옥시나이트라이드 또는 보로 실리케이트 그래스(BSG:Boron Silicate Glass)등으로 형성한다.Referring to FIG. 2, a first insulating film 104 is formed over the semiconductor substrate 102 with, for example, a silicon oxide film or other suitable insulating material. A conductive material is deposited and patterned on the first insulating film 104 to form a lower conductive film 106. The lower conductive film 106 is made of aluminum alloy, copper, titanium, tungsten or other suitable metal material. The second insulating layer 108 is formed on the lower conductive layer 106. In general, the second insulating film 108 is formed of a silicon oxide film, for example, oxynitride or boron silicate glass (BSG).
이 후, 제2 절연막(108) 위로 콘택홀(110)을 형성하기 위하여 포토레지스트(미도시)를 도포하여 노광, 현상한 후 식각한다. 제2 절연막 내에, 하부 도전막(106)과의 접촉영역을 노출시키면서 이 후에 형성되는 상부 도전막(116)과 하부 도전막(106)을 연결시키는 콘택홀(110)을 형성한다.Thereafter, in order to form the contact hole 110 on the second insulating layer 108, a photoresist (not shown) is coated, exposed, developed, and then etched. A contact hole 110 is formed in the second insulating film to expose a contact region with the lower conductive film 106 and to connect the upper conductive film 116 and the lower conductive film 106 formed thereafter.
도 3를 참조하면, 결과물 전면에 금속장벽(barrier) 물질을 증착하여 금속장벽막(112a, 112b)을 형성한다. 금속장벽 물질은 티타늄 나이트라이드(TiN), 티타늄 텅스텐(TiW), 텅스텐 나이트라이드(WN) 또는 티타늄 디보로라이드(TiB₂) 들로 형성한다. 화학 기상 증착법으로 금속장벽 물질을 증착하여 콘택홀(110)의 측면 및 밑면을 따라 정합(conformal)하도록 금속장벽막(112)을 형성한다. 이 후, 결과물 전면에 플러그용 도전막(114)을 형성한다. 플러그용 도전막(114)은 텅스텐(W) 또는 구리(Cu)로 구성한다. 이렇게 형성된 플러그용 도전막(114) 내에는 틈(114h)이 불가피하게 존재한다.Referring to FIG. 3, metal barrier materials 112a and 112b are formed by depositing a metal barrier material on the entire surface of the resultant product. The metal barrier material is formed of titanium nitride (TiN), titanium tungsten (TiW), tungsten nitride (WN) or titanium diborolide (TiB2). The metal barrier material is deposited by chemical vapor deposition to form a metal barrier film 112 to conform along the side and bottom surfaces of the contact hole 110. Thereafter, a plug conductive film 114 is formed on the entire surface of the resultant product. The plug conductive film 114 is made of tungsten (W) or copper (Cu). The gap 114h inevitably exists in the plug conductive film 114 thus formed.
본 일실시예에서는 콘택홀(110)을 내재한 절연막(108) 아래에 하부 도전막(106)이 형성되어 있다. 이는 절연막(108) 아래에 도전영역의 일예로서 하부 도전막(106)을 예를 들어, 설명한 것이다. 따라서, 제2 절연막(108) 아래의 도전영역으로서 반도체 기판 상에 불순물이 확산되어 형성된 접합층(junction layer)도 가능하며, 콘택홀(110)을 통하여 접합층의 접촉영역과 이후에 형성되는 상부 도전막(도 5의 116참조)과의 상호연결도 가능하다. 이 경우 제1 절연막(104)의 형성이 생략됨은 물론이다. In the present exemplary embodiment, the lower conductive layer 106 is formed under the insulating layer 108 having the contact hole 110 therein. This is described by taking the lower conductive film 106 as an example of the conductive region under the insulating film 108. Accordingly, a junction layer formed by diffusion of impurities on the semiconductor substrate as a conductive region under the second insulating layer 108 may be formed, and the contact region of the junction layer may be formed through the contact hole 110 and thereafter. Interconnection with the conductive film (see 116 of FIG. 5) is also possible. In this case, the formation of the first insulating film 104 is of course omitted.
여기서, 금속장벽막(112a, 112b)은 다음과 같이 이유에 의하여 형성한다.Here, the metal barrier films 112a and 112b are formed for the following reasons.
만약 이 후에 형성되는 상부 도전막(도 5의 116참조)으로 알루미늄을 사용하면 알루미늄 원자가 하부 도전막(106) 또는 하부 접합층으로 확산되어 접합층 스파이크(junction spike)와 같은 비정상적인 반응을 일으킨다. 접합층 스파이크는 접합층 누설(junction leakage)을 일으키고 접합층을 파괴한다. 이러한 접합층 스파이크를 방지하기 위하여 접합층 위에 바로 접촉하는 금속장벽막(112a, 112b)을 형성한다.If aluminum is used as the upper conductive film formed later (see 116 of FIG. 5), aluminum atoms diffuse into the lower conductive film 106 or the lower bonding layer, causing an abnormal reaction such as a junction spike. Bond layer spikes cause junction leakage and break the bond layer. In order to prevent such a bonding layer spike, metal barrier films 112a and 112b directly contacting the bonding layer are formed.
계속하여 금속장벽막(112a, 112b) 위에 플러그용 도전막(114)을 형성한다.Subsequently, a plug conductive film 114 is formed on the metal barrier films 112a and 112b.
집적회로의 스케일이 작아짐에 따라 콘택홀(110)의 크기(a) 즉, 너비가 작아지고 콘택홀(110)의 깊이(b)도 깊어진다. 이렇게 에스펙트 비(aspect ratio: 깊이/너비)가 큰 콘택홀을 완전히 매립하기 위하여 침투력(penetration)이 좋은 도전물질을 사용한다. 텅스텐(W) 이나 구리(Cu) 와 같은 도전물질을 화학 기상 증착법으로 증착하여 콘택홀을 매립하면 플러그를 형성한다.As the scale of the integrated circuit becomes smaller, the size a of the contact hole 110, that is, the width thereof becomes smaller, and the depth b of the contact hole 110 becomes deeper. In order to completely fill the contact holes having a large aspect ratio (depth / width), a conductive material having good penetration is used. A conductive material such as tungsten (W) or copper (Cu) is deposited by chemical vapor deposition to fill a contact hole to form a plug.
도 4를 참조하면, 결과물 전면에 대하여 화학적 기계적 연마(Chemical mechanical Polishing:CMP)공정을 실시하여 제2 절연막(108) 위에 형성된 금속장벽막(도 2b의 112a) 및 플러그용 도전막(도 3의 114)을 제거하여 플러그(114p)를 완성한다. Referring to FIG. 4, a chemical mechanical polishing (CMP) process is performed on the entire surface of the resultant to form a metal barrier film (112a of FIG. 2B) and a plug conductive film (FIG. 114 is removed to complete the plug 114p.
도 5를 참조하면, 결과물 전면에 상부 도전막(116)을 형성한다. 상부 도전막(116)은 하부 도전막(106)과 동일한 물질을 사용하여 동일한 방법으로 형성한다.Referring to FIG. 5, the upper conductive layer 116 is formed on the entire surface of the resultant. The upper conductive layer 116 is formed in the same manner using the same material as the lower conductive layer 106.
상부 도전막(116)은 알루미늄으로 형성한다. 알루미늄을 화학 기상 증착법으로 증착한 후, 진공인 상태에서 연속하여 알루미늄 리플로우를 실시한다. 이러한 알루미늄 리플로우에 의해 액상인 알루미늄이 플러그(114p) 내의 틈(seam)(114a)을 채우게 된다. 이러한 플러그(114p) 내의 틈(114a)은 텡스텐 또는 구리를 도전물질로 사용하여 화학 기상 증착법으로 증착할 때 불가피하게 생기는 것으로 접촉저항을 증가시킨다. The upper conductive film 116 is made of aluminum. After aluminum is deposited by chemical vapor deposition, aluminum reflow is performed continuously in a vacuum. The aluminum reflow fills the gap 114a in the plug 114p by the aluminum reflow. The gap 114a in the plug 114p inevitably occurs when deposited by chemical vapor deposition using tungsten or copper as a conductive material, thereby increasing contact resistance.
일정온도에서 일정시간동안 알루미늄 리플로우를 실시하면 알루미늄이 플러그(114p) 내의 틈(114a)을 채우면서 텅스텐 내부로 스며든다. 그러므로, 텅스텐 플러그(114p)와 상부 알루미늄 도전막(116) 사이의 콘택 저항을 감소시킨다. 리플로우시 텅스텐과 알루미늄이 충분히 접촉하도록 하는 것이 바람직하다. 따라서 500℃ 내지 660℃ 온도에서 60초 내지 120초 동안 리플로우를 실시하는 것이 적합하다.If aluminum is reflowed for a certain time at a constant temperature, aluminum seeps into the tungsten while filling the gap 114a in the plug 114p. Therefore, the contact resistance between the tungsten plug 114p and the upper aluminum conductive film 116 is reduced. It is desirable to have sufficient contact between tungsten and aluminum during reflow. Therefore, it is suitable to perform the reflow for 60 seconds to 120 seconds at a temperature of 500 to 660 ℃.
이후의 공정은 통상의 반도체 제조공정에 따라 진행한다. The subsequent process proceeds according to a conventional semiconductor manufacturing process.
상술한 본 발명의 반도체 장치의 제조방법에 따르면, 일정온도에서 일정시간동안 상부 도전막 예컨대, 알루미늄 리플로우시켜 상부 도전막 내의 구성원소, 예컨대 알루미늄이 플러그, 예컨대 텅스텐 플러그 내의 틈을 채우면서 플러그 내부로 스며든다. 그러므로, 플러그와 상부 도전막 사이의 콘택 저항을 감소시킨다. According to the manufacturing method of the semiconductor device of the present invention described above, the inside of the plug is filled with a member such as aluminum in the upper conductive film by reflowing the upper conductive film such as aluminum for a predetermined time at a constant temperature. Soak into. Therefore, the contact resistance between the plug and the upper conductive film is reduced.
도 1은 종래의 배선 구조에 있어서 손상을 설명하는 단면도이다.1 is a cross-sectional view illustrating damage in a conventional wiring structure.
도 2 내지 도 5는 본 발명의 일실시예의 공정순서에 따라 배선을 제조하는 방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method of manufacturing a wire according to a process sequence of an embodiment of the present invention.
Claims (9)
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| KR960010056A (en) * | 1994-09-07 | 1996-04-20 | 공희택 | Prewetting method and apparatus for a filter having a Teflon filtration membrane installed in a high purity chemical transport path of a semiconductor manufacturing process |
| JPH10106975A (en) * | 1996-10-02 | 1998-04-24 | Hitachi Ltd | Film forming method of semiconductor device |
| KR980011861A (en) * | 1996-07-19 | 1998-04-30 | 김광호 | METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR |
| KR100303796B1 (en) * | 1994-01-03 | 2001-11-30 | 윤종용 | Method for forming metal interconnection of semiconductor device |
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| KR100303796B1 (en) * | 1994-01-03 | 2001-11-30 | 윤종용 | Method for forming metal interconnection of semiconductor device |
| KR960010056A (en) * | 1994-09-07 | 1996-04-20 | 공희택 | Prewetting method and apparatus for a filter having a Teflon filtration membrane installed in a high purity chemical transport path of a semiconductor manufacturing process |
| KR980011861A (en) * | 1996-07-19 | 1998-04-30 | 김광호 | METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR |
| JPH10106975A (en) * | 1996-10-02 | 1998-04-24 | Hitachi Ltd | Film forming method of semiconductor device |
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