KR100501647B1 - Method of forming an isolation layer in a semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a device isolation layer of a semiconductor device, and to form a silicon layer on the insulating material layer formed on the entire upper portion to fill the trench, and to oxidize the silicon layer of the active region excluding the device isolation region of the device isolation region After adjusting the etch selectivity, the chemical mechanical polishing process is performed by removing the oxide layer and the insulating material layer on the upper surface of the pad nitride layer by a planarization etching process using a wet etching method to reduce the height of the device isolation layer. By preventing the removal of the groove formed between the device isolation region and the active region to secure the margin of the chemical mechanical polishing process, it is possible to improve the reliability of the process and the electrical characteristics of the device.

Description

Method of forming an isolation layer in a semiconductor device

The present invention relates to a method of forming a device isolation layer of a semiconductor device, and more particularly, to a method of forming a device isolation layer of a semiconductor device capable of improving planarization characteristics in a process of filling a trench with an insulating material and removing an insulating material over an active region. .

As the integration of devices increases, in order to solve the problem of the LOCOS process in which a bird's beak is generated when the device isolation layer is formed and the active region is narrowed, the device isolation layer is formed by a shallow trench isolation (STI) process. A method of forming the device isolation layer using the STI process will be described in detail below.

1A to 1D are cross-sectional views of devices for describing a method of forming a device isolation layer of a semiconductor device according to the prior art.

Referring to FIG. 1A, an oxide film (not shown) and a nitride film (not shown) are sequentially formed on a semiconductor substrate 101, and then the nitride film and the oxide film are sequentially patterned by an etching process using an element isolation mask. The nitride film pattern 103 and the pad oxide film pattern 102 are formed. As a result, the device isolation region of the semiconductor substrate 101 is exposed.

Next, the trench 104 may be formed by etching the device isolation region of the semiconductor substrate 101 to a predetermined depth by a trench etching process. A layer of insulating material 105 is then formed over the entirety so that the trench 104 is completely buried.

Referring to FIG. 1B, a chemical mechanical polishing process should be performed to remove the insulating material layer on the pad nitride film pattern 103, which is an active region, and the device isolation region is formed by filling the trench 104 with the insulating material layer 105. And a step is generated in the active region. For this reason, when the chemical mechanical polishing process is performed by setting the thickness of the insulating material layer 105 remaining in the active region to the polishing target thickness, the height of the insulating material layer (insulating material layer formed in the trench) formed in the element isolation region is increased. As a result, the height of the isolation layer is lowered.

Therefore, in order to solve this problem, the insulating material layer 105 on the pad nitride film pattern 103 which is the active region is first removed by a predetermined thickness to alleviate the step with the device isolation region. This process is called a planarization etch process.

For this planarization process, an etch mask 106 is formed on the device isolation region (trench). In this case, the etching mask 106 may be formed as a photoresist pattern, and may be formed to have the same width as the trench 104 or a part of the edge overlapping the active region. On the other hand, at the boundary between the device isolation region and the active region, the surface of the insulating material layer 106 is inclined by the step generated by the trench 104. As a result, a trench 107 is formed between the inclined surface of the insulating material layer 106 and the etching mask 106.

Referring to FIG. 1C, in consideration of a margin of a chemical mechanical polishing process to be performed in a subsequent process, the insulating material layer 105 on the pad nitride layer pattern 103, which is an active region, is removed by a predetermined thickness in a planarization etching process. At this time, since the flat portion and the inclined portion of the insulating material layer 105 are etched uniformly, the groove 107 remains between the inclined surface of the insulating material layer 106 and the etching mask 106.

This can be confirmed in the cross-sectional photograph shown in FIG.

Referring to FIG. 1D, the etching mask (106 of FIG. 1C) is removed.

In the above, when the insulating material layer 105 is excessively etched during the planarization etching process, the groove 107 is uniformly etched while the shape of the grooves 107 is maintained. The semiconductor substrate 101 may be damaged.

In addition, in the planarization etching process, since the insulating material layer 105 must remain on the pad nitride layer pattern 103 by a predetermined thickness, the progress time of the planarization etching process must be accurately controlled. However, it is not easy to control the progress time of the planarization etching process by a change (for example, a change in thickness) of the insulating material layer 105 depending on the process conditions. As a result, it is difficult to accurately control the planarization etching process, and if the time adjustment is incorrect, damage to the semiconductor substrate 101 may occur, thereby reducing the reliability of the process and the electrical characteristics of the device.

On the other hand, in the method of forming an isolation layer of a semiconductor device according to the present invention, a silicon layer is formed on an insulating material layer formed over the entire surface to fill a trench, and the device isolation is oxidized by oxidizing the silicon layer in the active region except for the isolation region. After adjusting the etch selectivity of the region, a chemical mechanical polishing process is performed by removing the oxide layer and the insulating material layer on the upper surface of the pad nitride layer by a planarization etching process using a wet etching method, thereby reducing the height of the device isolation layer. By preventing the loss of the groove formed between the device isolation region and the active region can be removed to secure a margin of the chemical mechanical polishing process and improve the reliability of the process and the electrical characteristics of the device.

The method of forming a device isolation layer of a semiconductor device according to an embodiment of the present invention includes forming a pad oxide layer pattern and a pad nitride layer pattern having a device isolation region in a stacked structure on a semiconductor substrate, and forming a trench in the device isolation region of the semiconductor substrate. Forming an insulating material layer over the entire portion to fill the trench; forming a silicon layer on the device isolation region so that the etching selectivity of the device isolation region and the active region is different; Removing the insulating material layer on the upper surface of the pad nitride layer by a planarization etching process using the planarization etching process, and planarizing the entire upper part by a chemical mechanical polishing process.

In the above, the silicon layer may be formed by depositing amorphous silicon by a low pressure chemical vapor deposition method, the low pressure chemical vapor deposition process may be carried out at a temperature of 400 ℃ to 600 ℃. The silicon layer can be formed to a thickness of 200 kPa to 1000 kPa.

On the other hand, forming the silicon layer in the substrate isolation region, forming a silicon layer on the insulating material layer, forming an ion implantation mask in the device isolation region, and oxidizing the silicon layer of the active region to form an oxide film Forming and removing the ion implantation mask.

Here, the forming of the oxide film may be performed by an O ₂ ion implantation process of injecting oxygen into the silicon layer. O ₂ ion implantation step can be injected into the tilt angle of the 1E12atoms / cm ² to 1E16atoms / cm can be injected ² in O _2, within the vertical injection into or 30 the O ₂ with an ion implantation energy of 60KeV to 130KeV.

The planarization etching process may selectively remove only the insulating material layer of the active region by a wet etching method while maintaining a high selectivity by the ion implantation layer formed in the device isolation region.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

3A to 3H are cross-sectional views of devices for describing a method of forming a device isolation film of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, after an oxide film (not shown) and a nitride film (not shown) are sequentially formed on a semiconductor substrate 301, the nitride film and the oxide film are sequentially patterned by an etching process using an element isolation mask. The nitride film pattern 303 and the pad oxide film pattern 302 are formed. As a result, the device isolation region of the semiconductor substrate 301 is exposed. In this case, the pad oxide film pattern 302 may be formed to have a thickness of 100 kPa to 200 kPa. On the other hand, the pad nitride film pattern 303 is preferably formed to a thickness that can secure a process margin in consideration of the thickness to be removed during the subsequent polishing process, it can be formed to a thickness of 1000 ~ 1800Å.

Next, the trench 304 is formed by etching the device isolation region of the semiconductor substrate 301 to a predetermined depth by a trench etching process. The trench may be formed to a depth of 3000 kPa to 4000 kPa. Thereafter, an insulating material layer 305 is formed over the entirety so that the trench 304 is completely buried. Meanwhile, since the insulating material layer 305 on the pad nitride film pattern 303 is completely removed during the planarization etching process performed in a subsequent process, the insulating material layer 305 may be formed to a thickness lower than that of the conventional art and may be formed to a thickness of 4000 to 6000 Å.

Referring to FIG. 3B, a silicon layer 306 is formed on the insulating material layer 305. The silicon layer 306 may be formed by depositing amorphous silicon by a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition). Meanwhile, the low pressure chemical vapor deposition process for forming the silicon layer 306 may be performed at a temperature of 400 ° C. to 600 ° C., and the silicon layer 306 may be formed to a thickness of 200 μm to 1000 μm.

Here, the silicon layer 306 is formed to adjust the etching selectivity of the device isolation region. More specifically, it is as follows.

In order to remove the insulating material layer on the pad nitride layer pattern 303, which is an active region, a chemical mechanical polishing process should be performed. As the insulating material layer 305 is filled with the trench 304, there is a step between the device isolation region and the active region. Is generated. Therefore, when the chemical mechanical polishing process is performed by setting the thickness of the insulating material layer 305 remaining in the active region to the polishing target thickness, the height of the insulating material layer (insulating material layer formed in the trench) formed in the element isolation region is increased. As a result, the height of the isolation layer is lowered.

Therefore, in order to solve this problem, before performing the chemical mechanical polishing process, the insulating material layer formed in the active region except the device isolation region is first removed to alleviate the step with the device isolation region. This process is called a planarization etch process.

In this planarization etching process, in order to remove only the insulating material layer over the active region, a difference in etching selectivity between the device isolation region and the active region must be generated, and the silicon layer 306 is formed to generate such a difference in etching selectivity. do.

Referring to FIG. 3C, an ion implantation mask 307 is formed on the device isolation region (trench). In this case, the ion implantation mask 307 may be formed as a photoresist pattern, and may be formed to have the same width as the trench 304 or a part of the edge overlapping the active region. For example, it is preferable to form the ion implantation mask 307 so as to overlap the active region to 0.5 um or less.

Referring to FIG. 3D, the silicon layer on the pad nitride layer pattern 303 which is an active region is oxidized to form an oxide layer 308 having an etching selectivity substantially similar to that of the insulating material layer 305. As a result, the silicon layer 306 remains in the device isolation region and the silicon layer 308 is formed in the active region, thereby changing the etching selectivity of the device isolation region and the active region.

The silicon layer in the active region may be formed of an oxide film in various ways. Among them, the silicon layer may be formed of an oxide film by performing an O ₂ ion implantation process. In this case, O ₂ ion implantation process 60KeV to 1E12atoms the ion implantation energy of 130KeV / cm ² to 1E16atoms / cm ² of O may be performed in a manner of injecting _2, O ₂ to the inclination angle of the injection, or less than 30 degrees in the vertical Can be injected by

Referring to FIG. 3E, the ion implantation mask 307 of FIG. 3D is removed.

Referring to FIG. 3F, in consideration of a margin of a chemical mechanical polishing process to be performed in a subsequent process, a planar etching process completely removes an oxide layer and an insulating material layer on the pad nitride layer pattern 303 which are active regions. In this case, in the device isolation region, due to the difference in the etching selectivity of the silicon layer 306 formed on the surface of the insulating material layer 305, the insulating material layer 305 embedded in the trench 304 remains unetched. .

On the other hand, the planarization etching process is different from the conventional method in which the insulating material layer 305 is partially left by adjusting the process time, and the planarization etching process is performed by a wet etching method to completely remove the insulating material layer on the pad nitride layer pattern 303. Remove Therefore, the planar etching process may be performed without considering the process change generated in the process of forming the insulating material layer 305, so that the planarization etching process may be performed more easily and the reliability of the process may be improved.

For example, the planarization etching process may be described in more detail by applying a power of 800 W to 1500 W at a pressure of 500 mTorr to 300 mTorr, and using CHF ₃ / CF ₄ / Ar gas. At this time, the supply flow rate of CHF ₃ may be set to 20 sccm to 60 sccm, the supply flow rate of CF ₄ may be set to 30 sccm to 90 sccm, and the supply flow rate of Ar may be set to 1000 sccm to 1500 sccm.

Referring to FIG. 3G, a chemical mechanical polishing process is performed to form a silicon layer (306 of FIG. 3E) formed on the surface of the insulating material layer 305 and the insulating material layer 305 protruding higher than the pad nitride film pattern 303. Remove the to flatten the entire top surface.

Referring to FIG. 3H, the pad nitride film pattern 303 of FIG. 3D and the pad oxide film pattern 302 are removed. As a result, an isolation layer formed of the insulating material layer 305 is formed.

As described above, in order to fill the trench, the present invention forms a silicon layer on an insulating material layer formed on the entire upper portion, and oxidizes the silicon layer of the active region excluding the device isolation region to control the etching selectivity of the device isolation region. Then, by performing a chemical mechanical polishing process in a state in which the oxide film and the insulating material layer on the pad nitride film is removed by a planarization etching process using a wet etching method, the device isolation region and the device isolation layer are prevented from being lowered. By removing the grooves formed between the active regions, it is possible to secure a margin of the chemical mechanical polishing process and improve the reliability of the process and the electrical characteristics of the device.

1A to 1D are cross-sectional views of devices for describing a method of forming a device isolation layer of a semiconductor device according to the prior art.

FIG. 2 is a cross-sectional view illustrating a state in which grooves are formed in an insulating material layer for forming an isolation layer due to a step.

3A to 3H are cross-sectional views of devices for describing a method of forming a device isolation film of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 301: semiconductor substrate 102, 302: pad oxide film pattern

103, 303: pad nitride film pattern 104, 304: trench

105, 305: insulating material layer 106: etching mask

107: groove 306: silicon layer

307: ion implantation mask 308: oxide film

Claims (5)

Forming a pad film on the semiconductor substrate, patterning a predetermined depth of the pad film and the semiconductor substrate to form a trench as an isolation region in the semiconductor substrate, and defining an active region at the same time; Forming an insulating material layer over the entire trench to fill the trench; Forming a silicon layer over the insulating material layer; Forming an ion implantation mask in the device isolation region; Oxidizing the silicon layer in the active region to form an oxide film so that the silicon layer remains only in the device isolation region; Removing the ion implantation mask; Removing the insulating material layer on the pad layer by a planarization etching process using a difference between an etch selectivity of an oxide film formed on the active region and a silicon layer formed on the device isolation region; And A method of forming a device separator of a semiconductor device comprising the step of planarizing the entire upper portion by a chemical mechanical polishing process. The method of claim 1, Wherein the silicon layer is formed by depositing amorphous silicon by a low pressure chemical vapor deposition method. The method of claim 1, The forming of the oxide film is a method of forming a device isolation layer of a semiconductor device which is performed in the O ₂ ion implantation process of injecting oxygen into the silicon layer. The method of claim 3, wherein The O ₂ ion implantation process 60KeV to 1E12atoms / cm ² to the device isolation film forming method of the semiconductor device of injecting O ₂ of 1E16atoms / cm ² with an ion implantation energy of 130KeV. The method of claim 4, wherein The method of forming an isolation layer of a semiconductor device in which the O ₂ ion implantation process implants the O ₂ vertically or at an inclination angle within 30 degrees.