KR20080060318A - Method for forming isolation layer in semiconductor device - Google Patents

Abstract

A method for forming an isolation layer of a semiconductor device is provided to control uniformly the effective height of the isolation layer by increasing gradually temperature in thermal processes. A pad nitride layer(103) is formed on an upper surface of a substrate(100). A trench is formed by etching the pad nitride layer and the substrate. An isolation layer(105) is deposited on the pad nitride layer to bury the trench. The isolation is thermally processed by performing a first and second thermal process. The first and second thermal process are performed by increasing gradually the temperature. The first and second thermal process are performed finally at the temperature of 700 °C. The isolation layer is planarized.

Description

METHODS FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE}

1 to 5 are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

100 substrate 101 gate insulating film

102 conductive film 103, 103A pad nitride film

104: trench 105, 105A, 105B: device isolation film

106: heat treatment 107: dry etching process

108: wet etching process CELL: cell area

PERI: Peripheral Circuit Area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device to which a shallow trench isolation (STI) technology is applied.

With the development of the manufacturing process technology of the semiconductor memory device, the line width of the semiconductor memory device has gradually decreased. As a result, the width of the field region between the active regions is reduced. As a result, the aspect ratio of the trenches formed in the field region is increased to fill the device isolation film in the trench. It became difficult.

In particular, when the HDP oxide film formed by the conventional HDP (High Density Plasma) Chemical Vapor Deposition (CVD) method is used as the device isolation layer, it is difficult to fill in the trench having a high aspect ratio. For example, in the STI process having an aspect ratio of 3.5 or less, there is no great difficulty. However, when the aspect ratio is 4 or more, there is a limit to using an HDP oxide film as an element isolation film. That is, as the conventional STI process is performed using only the HDP oxide layer, a void occurs in the device isolation layer.

Therefore, in order to prevent such voiding and improve the buried property of the device isolation layer, a polysilazane (PoliSilaZane, hereinafter, PSZ), which is a type of spin on dielectric (SOD) film deposited by a spin coating method instead of an HDP oxide film, is referred to as PSZ. Has been proposed to fill the trench.

However, unlike the HDP oxide film, PSZ has a material characteristic that the wet etching rate is fast and nonuniform, so that the effective field oxide height (EFH) of the device isolation layer is uneven when the wet etching process is applied. For example, the PSZ has different wet etching in the cell region in which the memory cell is formed and the peripheral circuit region in which the peripheral element is formed, so that the device isolation layer is controlled at different heights in the cell region and the peripheral circuit region after the wet etching process is applied. There is a problem. This problem will be described in detail with reference to Table 1 below.

# 9 EFH (Unit: Å) DIE NO. CC CE LV L (Left) 226 66 906 B (Bottom) 213 173 986 C (Center) 266 146 876 T (Top) 186 120 853 R (Right) 226 186 960 AVERAGE 223 138 916 MAX 266 186 986 MIN 186 66 853 RANGE 80 120 133

Table 1 shows the results of measuring the effective height of the device isolation film (EFH) in the cell region and the peripheral circuit area when the device isolation film is formed using the PSZ according to the prior art. Referring to Table 1, it can be seen that the effective height of the device isolation film formed in the cell region is controlled to be at most 920 Å (986-66 Å) lower than the effective height of the device isolation film formed in the peripheral circuit region. This is because the wet etch rate of the PSZ is larger in the cell region than in the peripheral circuit region.

In Table 1, CC (Cell Center) represents the center portion of the cell region, CE (Cell Edge) represents the edge portion of the cell region, and LV (Low Voltage) is a region in which the low voltage transistor is formed and belongs to the peripheral circuit region.

Accordingly, in recent years, a technique has been proposed in which the PSZ film has a wet etch rate similar to that of an HDP oxide film by performing a high temperature heat treatment of about 700 ° C. or more immediately after the deposition of the PSZ to fill the trench.

However, when the high temperature heat treatment is performed at 700 ° C. or more immediately after the deposition of the PSZ, a problem occurs in that the thickness of the gate oxide film already formed on the substrate becomes thick. For example, in the case of a NAND type flash memory device, a self-aligned (SA) -STI and an advanced self-aligned (ASA) -STI process is applied. In this process, a gate oxide film is formed in advance. In addition, since the device isolation film is formed, the thickness of the gate oxide film becomes thick during the high temperature heat treatment.

Accordingly, the present invention has been proposed to solve the above problems, and has the following objects.

First, it is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device capable of suppressing void generation when forming a device isolation film of a semiconductor device.

Second, another object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of uniformly controlling the effective height of the device isolation film when forming the device isolation film of the semiconductor device.

Third, another object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of suppressing a thickening of a gate insulating film on a substrate when forming the device isolation film of a semiconductor device.

According to an aspect of the present invention, there is provided a method of forming a pad nitride film on an upper surface of a substrate, etching the pad nitride film and the substrate to form a trench, and filling the trench with the pad nitride film. Depositing a device isolation film on the substrate, heat treating the device isolation film at least two times, wherein the heat treatment is performed by increasing the temperature step by step at a temperature of at least 700 ° C. or above, and planarizing the device isolation film. It provides a device isolation film forming method of a semiconductor device comprising the step of.

Here, the device isolation film is preferably formed of a laminated film in which the PSZ layer is formed on the PSZ single film or the oxide film-based insulating film. In addition, after the device isolation layer is planarized, the method may further include performing a dry etching process such that the pad nitride layer remains at a predetermined thickness, and completely removing the pad nitride layer through a wet etching process.

According to the present invention, a plurality of heat treatments are performed after the formation of the device isolation film embedded in the trench, but the temperature is increased step by step, and finally, the heat treatment is performed at a high temperature of at least 700 ° C. or more, thereby forming a material (typically PSZ). The wet etch rate of is controlled uniformly. Therefore, even when the wet etching process is applied, the effective height of the device isolation layer may be uniformly controlled.

In addition, the present invention allows the pad nitride film to remain at a predetermined thickness through a dry etching process, and then completely removes the pad nitride film through a wet etching process, thereby more efficiently and uniformly controlling the effective height of the device isolation layer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same components.

Example

1 to 5 are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention. As a representative example, a method of forming an isolation layer of a flash memory device, specifically, an ASA-STI process, will be described.

First, as shown in FIG. 1, a gate insulating film 101, a conductive film 102 for a gate electrode and a pad nitride film (on a semiconductor substrate 100 including a cell region CELL and a peripheral circuit region PERI) are formed. 103) are formed sequentially. Here, the gate insulating film 101 serves as a tunnel oxide film of a flash memory device, and is formed through an oxidation process, and the conductive film 102 functions as a floating gate, and is formed of a polysilicon film. desirable.

Subsequently, the trench 104 is formed in the cell region CELL and the peripheral circuit region PERI by etching the pad nitride film 103, the conductive film 102, the gate insulating film 101, and the substrate 100 by a predetermined depth. .

Next, as shown in FIG. 2, an insulating film for a device isolation film 105 (hereinafter referred to as a device isolation film) is deposited on the entire structure so that the trench 104 (see FIG. 1) is embedded. The device isolation layer 105 may be formed of a single PSZ layer or may be formed by stacking PSZ on an oxide-based insulating layer. In this case, as an insulating film of an oxide film series, an HDP oxide film or a HARP (High Aspect Ratio Process) oxide film may be used.

That is, the device isolation film 104 may be formed by depositing any one of the PSZ, the HDP oxide film, and the HARP oxide film so that a portion of the trench 104 is filled, and then depositing the PSZ so that the trench 104 is completely embedded. . For example, after depositing any one of the PSZ, the HDP oxide film and the HARP oxide film to a point where 3.5 of the overall trench 104 aspect ratio (so that the thickness on the substrate 100 is 500 Å or less), the trench 104 is completely removed. The PSZ is deposited to be buried.

Next, heat treatment 106 is performed to densify the film quality of the device isolation film 105. In particular, the heat treatment 106 is a process for ensuring that the PSZ constituting the device isolation film 105 has a wet etching rate similar to that of the HDP oxide film as much as possible. It is important to increase the temperature to 700 ° C or more in the subsequent heat treatment step by step. As a result, the PSZ constituting the device isolation layer 105 may have a wet etch rate as close as that of the HDP oxide layer while preventing the thickness of the gate insulating layer 101 from increasing. Therefore, since the device isolation film 105 has a uniform wet etch rate, the effective height of the device isolation film 105 may be uniformly controlled even in the subsequent wet etching process.

For example, the heat treatment 106 may be as follows.

First, the first heat treatment is performed for 30 to 60 minutes at a low temperature of 350 ~ 450 ℃, the second heat treatment is carried out for 30 to 60 minutes at a temperature of 650 ~ 750 ℃. Subsequently, a third heat treatment is finally performed at a high temperature of 850 to 900 ° C. for 30 to 60 minutes.

In addition, such heat treatment 106 is preferably performed first and second heat treatment while the third heat treatment is dry. Here, the wet heat treatment is carried out in an H ₂ and O ₂ gas atmosphere, and refers to applying heat in a steam atmosphere by causing H ₂ and O ₂ to react with a platinum catalyst to cause water vapor (H ₂ O). Further, dry heat treatment refers to heat treatment using a N ₂ gas.

In this heat treatment 106, the first heat treatment is carried out at a temperature significantly lower than 700 ℃ to prevent the thickness of the gate insulating film 101 increases, the second heat treatment is carried out at a high temperature of about 700 ℃ PSZ The film is made to have a wet etch rate as close as possible to the HDP oxide film. In this second heat treatment, the influence on the gate insulating film 101 is very small, and may be performed at about 700 ° C. In addition, the third heat treatment is performed at a higher temperature than the second heat treatment in order to further densify the film quality of the device isolation film 105.

Next, as shown in FIG. 3, a chemical mechanical polishing (CMP) process is performed to remove the device isolation film 105 (see FIG. 2) on the pad nitride film 103. That is, the device isolation film 105A is planarized through a CMP process using the pad nitride film 103 as a polishing stop film. As a result, an isolation device 105A is formed in the trench 104 (refer to FIG. 1).

Next, as shown in FIG. 4, the dry etching process 107 is performed to etch the pad nitride film 103A such that the pad nitride film 103A remains on the conductive film 102 by a predetermined thickness. The dry etching process 107 is preferably performed so that the pad nitride film 103A remains on the conductive film 102 by a thickness of 1 to 50 Å. To this end, the dry etching process 107 is performed by adjusting the etching selectivity between the device isolation film 105B and the pad nitride film 103A to be 1: 1 to 1: 1.5.

In this case, when the etching selectivity between the device isolation film 105B and the pad nitride film 103A is 1: 1, the device isolation film 105B and the pad nitride film 103A are etched and planarized to have the same thickness as in the drawing. For example, both the device isolation film 105B and the pad nitride film 103A are etched at about 400 to 500 microseconds.

In addition, the dry etching process 107 is performed by using CF ₄ and CHF ₃ gas, the mixing ratio of these are adjusted to CF ₄ : CHF ₃ = 1: 3 ~ 1: 5, power conditions of 250 ~ 300W and 50 It is preferable to carry out for 10 to 30 seconds under a pressure condition of ˜150 mTorr.

Subsequently, as shown in FIG. 5, a wet etching process 108 is performed to remove the pad nitride film 103A (see FIG. 4). This wet etching process 108 is performed using a buffered oxide etchant (hereinafter referred to as BOE) and a phosphoric acid solution (H ₃ PO ₄ ). As a result, the device isolation film 105B is recessed to a certain depth and the pad nitride film 103A is completely removed. Here, the BOE is preferably used by mixing HF and NH ₄ F in a ratio of 250: 1 to 350: 1.

Accordingly, the device isolation layers effective heights EFH1 and EFH2 may be equally controlled in the cell region CELL and the peripheral circuit region PERI as in the same figure. Since the wet etching process 108 is performed while the pad nitride film 103A is removed along with the device isolation film 105B through a dry etching process 107, the device isolation film 105B is wet etching process 108. This is because it minimizes the exposure time.

Hereinafter, referring to Table 2 below, the effective height step of the device isolation layer between the cell region and the peripheral circuit region will be described in detail according to the exemplary embodiment of the present invention.

# 9 EFH (Unit: Å) DIE NO. CC CE LV L (Left) 828 763 934 B (Bottom) 828 842 1013 C (Center) 855 802 1039 T (Top) 763 828 934 R (Right) 842 868 986 AVERAGE 823 821 981 MAX 855 868 1039 MIN 763 763 934 RANGE 92 105 105

Table 2 shows the results of measuring the effective height (EFH) of the device isolation layer in the cell region and the peripheral circuit region when the device isolation layer is formed using the PSZ according to the embodiment of the present invention.

Referring to Table 2, it can be seen that the difference between the effective height of the device isolation film formed in the cell region and the effective height of the device isolation film formed in the peripheral circuit region is 276 Å (1039-763 Å). In other words, it can be seen that the reduction in the effective height of the device isolation layer effective height between the existing cell region and the peripheral circuit region (920 Å). This is because the PSZ has a wet etch rate as similar as that of the HDP oxide film as described above, so that the device isolation film 105B has a uniform wet etch rate as a whole. In addition, the process of removing the pad nitride film 103A is performed by dividing the dry etching process 107 and the wet etching process 108 differently from the conventional method.

In Table 2, CC (Cell Center) represents the center portion of the cell region, CE (Cell Edge) represents the edge portion of the cell region, and LV (Low Voltage) is a region in which the low voltage transistor is formed and belongs to the peripheral circuit region.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the embodiment of the present invention has been described for the ASA-STI process for convenience of description, the present invention is not limited thereto and may be applied to all semiconductor memory device manufacturing processes to which the STI process is applied. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, according to the present invention, the generation of voids in the device isolation film can be suppressed by using the PSZ deposited by spin coating in forming the device isolation film of the semiconductor device using the STI process.

Second, according to the present invention, the PSZ is deposited during the formation of the device isolation film, and then a plurality of heat treatments are performed, and the heat treatment temperature is increased step by step, and finally, the heat treatment is performed at a high temperature of 700 ° C. or more, so that the PSZ is formed with the HDP oxide film as much as possible. Similar wet etch rates can be achieved. Through this, the effective height of the device isolation film can be uniformly controlled.

Third, according to the present invention, the first heat treatment performed at the time of the plurality of heat treatments can be performed at a temperature (350-450 ° C.) significantly lower than 700 ° C. to prevent the thickness of the gate insulating film from becoming thick.

Claims (14)

Forming a pad nitride film over the substrate; Etching the pad nitride layer and the substrate to form a trench; Depositing a device isolation layer on the pad nitride layer to fill the trench; Heat-treating the device isolation film at least twice, wherein the heat-treatment is performed stepwise to increase its temperature and finally at a high temperature of at least 700 ° C .; And Planarizing the device isolation layer Device isolation film forming method of a semiconductor device comprising a. The method of claim 1, After planarizing the device isolation layer, Performing a dry etching process so that the pad nitride film remains at a predetermined thickness; And Completely removing the pad nitride layer through a wet etching process. Device isolation film forming method of a semiconductor device further comprising. The method of claim 2, The dry etching process is a device isolation film forming method of the semiconductor device is performed by adjusting the etching selectivity of the pad nitride film relative to the device isolation film to 1: 1 ~ 1: 1.5. The method of claim 2, The dry etching process is a method of forming a device isolation film of a semiconductor device such that the pad nitride film is left to the thickness of 1 ~ 50 1 over the substrate. The method of claim 2, Wherein the dry etching process using a CF ₄ and CHF ₃ gas, a method of forming a device isolation film of a semiconductor device performed by adjusting the mixing ratio of these to CF ₄ : CHF ₃ = 1: 3 ~ 1: 5. The method of claim 2, The dry etching process is a device isolation film forming method of a semiconductor device performed for 10-30 seconds under a power condition of 250 ~ 300W and a pressure condition of 50 ~ 150mTorr. The method of claim 2, The wet etching process is a method of forming a device isolation layer of a semiconductor device using a buffered oxide etchant (BOE) and phosphoric acid solution (H ₃ PO ₄ ). The method of claim 7, wherein The buffered oxide etchant is a method of forming a device isolation layer of a semiconductor device using a mixture of HF and NH ₄ F in a ratio of 250: 1 ~ 350: 1. The method of claim 1, Before forming the pad nitride film, Forming a gate insulating film and a conductive film for a gate electrode on the substrate. The method according to any one of claims 1, 2 and 9, The step of performing the heat treatment, Performing a first heat treatment at a temperature of 350 to 450 ° C .; Performing a second heat treatment at a temperature of 650-750 ° C .; And Performing a third heat treatment at a temperature of 850 ~ 950 ℃ Device isolation film forming method of a semiconductor device comprising a. The method of claim 10, Wherein the first to third heat treatment is a device isolation film forming method of a semiconductor device to proceed for 30 to 60 minutes each. The method of claim 10, Wherein the first and second heat treatments are performed in a wet manner, and the third heat treatment is performed in a dry manner. The method according to any one of claims 1, 2 and 9, The device isolation layer is a device isolation film forming method of a semiconductor device to form a polysilazane (PSZ) single layer or an oxide film-based insulating layer of the PSZ stacked layer. The method according to any one of claims 1, 2 and 9, The planarization of the device isolation layer may include A method of forming a device isolation film for a semiconductor device, comprising performing a chemical mechanical polishing process using the pad nitride film as a polishing stop film.

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