KR100497207B1 - Method of manufacturing semiconductor - Google Patents
Method of manufacturing semiconductor Download PDFInfo
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- KR100497207B1 KR100497207B1 KR10-2003-0006303A KR20030006303A KR100497207B1 KR 100497207 B1 KR100497207 B1 KR 100497207B1 KR 20030006303 A KR20030006303 A KR 20030006303A KR 100497207 B1 KR100497207 B1 KR 100497207B1
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- oxide film
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- silicon substrate
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- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
본 발명의 트렌치를 매립한 후에 실시되는 산화막을 제거하는 과정에서 트렌치에 매립된 산화막이 손상되는 것을 방지할 수 있도록 하는 반도체 소자의 제조방법을 제공하는 것으로, 이에 관련된 제조방법은, a) 실리콘기판 상부에 패드 산화막과 질화막을 순차적으로 적층하는 단계; b) 상기 질화막 상부에 모트 패턴을 형성하며, 상기 모트 패턴을 식각 차단층으로 하여 질화막과 패드 산화막을 식각하는 단계; c) 상기 식각에 의해 드러난 실리콘 기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계; d) 노출된 실리콘기판 전면에 트렌치 갭필(Gap-fill)용 산화막이 치밀(dense)하게 증착되도록, 실리콘(Si) 공급량을 1.400 내지 1.670 ℓ/min로 공급하면서 화학기상증착법으로 증착하여 트렌치를 매립하는 단계; 및 e) 상기 질화막을 버퍼층으로 하여 화학 기계적 연마 방식으로 상기 갭필용 산화막을 연마하여 평탄화―여기서, 상기 평탄화는 상기 트렌치 산화막 내에 형성된 보이드(Void)를 외부로 노출시키지 않게 함―를 실시하는 단계를 포함한다.In the process of removing the oxide film carried out after filling the trench of the present invention to provide a method for manufacturing a semiconductor device that can prevent the oxide film embedded in the trench to be damaged, the manufacturing method related thereto, a) a silicon substrate Sequentially stacking a pad oxide film and a nitride film thereon; b) forming a mort pattern on the nitride layer, and etching the nitride layer and the pad oxide layer using the mort pattern as an etch stop layer; c) etching the silicon substrate exposed by the etching to a predetermined depth to form a trench; d) Filling the trenches by chemical vapor deposition while supplying a silicon (Si) supply amount of 1.400 to 1.670 L / min so that the oxide film for trench gap fill is densely deposited on the exposed silicon substrate. Doing; And e) polishing the gap fill oxide film by a chemical mechanical polishing method using the nitride film as a buffer layer to planarize, wherein the planarization does not expose the voids formed in the trench oxide film to the outside. Include.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 반도체장치의 소자간 분리를 위한 얕은 트렌치 절연(Shallow Trench Isolation; 이하 STI라 칭함) 공정시 갭필된 산화막이 손상되는 것을 방지하는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device which prevents a gap-filled oxide film from being damaged during a shallow trench isolation (STI) process for isolation between devices of a semiconductor device. It is about.
현재 반도체장치의 제조기술의 발달과 그 응용분야가 확장되어 감에 따라 반도세 소자의 집적도 증가에 대한 연구 및 개발이 급속도로 발전되고 있다. 이러한 반도체 소자의 집적도 증가에 따라 미세 공정기술을 기본으로 한 반도체 소자의미세화에 대한 연구가 진행되어 오고 있다. 반도체 소자의 미세화 기술에 있어서, 소자를 집적화하기 위하여 소자 사이를 분리하는 소자분리막의 축소 기술이 중요한 항목중의 하나로 대두되었다.As the development of semiconductor device manufacturing technology and its application field are expanding, research and development on the increase in the degree of integration of semiconductor devices has been rapidly developed. With the increase in the degree of integration of semiconductor devices, researches on the miniaturization of semiconductor devices based on fine process technology have been conducted. In the technology of miniaturization of semiconductor devices, in order to integrate devices, a technology of reducing a device isolation film that separates devices has emerged as one of the important items.
소자분리기술 중에서 STI 기술은 반도체기판에 식각 공정으로 트렌치를 형성하고 트렌치에 절연물질을 매립함으로써 모트와 모트 사이의 미세한 임계치수 설계가 가능한 방법이다.Among the device isolation technologies, STI technology is a method of forming a fine critical dimension between the mort and the mort by forming a trench in the semiconductor substrate by the etching process and filling an insulating material in the trench.
도 1a 내지 도 1e는 종래 기술에 의한 반도체 소자의 제조방법을 설명하기 위한 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 1a에 도시한 바와 같이, 통상적인 공정으로 실리콘기판(1) 상부에 패드 산화막(2)과 질화막(3)을 관통하는 트렌치를 형성하고, 트렌치 내부에 열산화막(4)을 형성한 다음, 기판(1) 전체에 상압화학기상증착법(Atmospheric Pressure Chemical Vapor Deposition)으로 갭필용 산화막(5)을 증착하여 트렌치를 완전히 매립한다.As shown in FIG. 1A, a trench penetrating the pad oxide film 2 and the nitride film 3 is formed on the silicon substrate 1 in a conventional process, and then a thermal oxide film 4 is formed in the trench. The gap fill oxide film 5 is deposited on the entire substrate 1 by Atmospheric Pressure Chemical Vapor Deposition to completely fill the trench.
이러한 증착과정에서 트렌치에 매립되는 갭필용 산화막(5)은 트렌치의 미세한 임계치수로 인해 트렌치의 내부에 해당하는 부분에 보이드(6)가 형성된다.In the deposition process, the gapfill oxide film 5 embedded in the trench has a void 6 formed in a portion corresponding to the inside of the trench due to the minute critical dimension of the trench.
이렇게 보이드(6)가 형성된 상태에서 도 1b에 도시한 바와 같이, 갭필용 산화막(5)을 제거하기 위해 화학기계적연마법을 이용하여 평탄화 작업을 실시하면, 트렌치 산화막의 보이드(6)가 노출에 취약한 상태가 된다.In the state where the voids 6 are formed as shown in FIG. 1B, when the planarization operation is performed using chemical mechanical polishing to remove the gap fill oxide film 5, the void 6 of the trench oxide film is exposed to exposure. You are vulnerable.
그리고 나서 도 1c에 도시한 바와 같이, 모트 습식 식각을 실시하여 질화막(3) 및 패드 산화막(2)의 일부를 제거하고, 도 1d에 도시한 바와 같이 이온 주입시 발생되는 모트 손상을 방지하기 위해 사용된 패드 산화막(2)을 완전히 제거한다. 이 과정에서 갭필용 산화막(5)의 손실이 발생되면서 보이드(6)가 노출된다.Then, as shown in FIG. 1C, the wet wet etching is performed to remove a part of the nitride film 3 and the pad oxide film 2, and to prevent the damage of the mote generated during ion implantation as shown in FIG. 1D. The pad oxide film 2 used is completely removed. In this process, the void 6 is exposed while the loss of the gap fill oxide film 5 occurs.
이렇게 보이드 부분이 손상된 상태에서 그 위에 도 1e에 도시한 바와 같이, 전극 형성용 게이트 폴리(7)를 증착하게 되면, 노출된 보이드(6)의 내부로 게이트 폴리(7)가 인입 증착된다.When the void portion is damaged in this manner, as shown in FIG. 1E, when the gate poly 7 for forming the electrode is deposited, the gate poly 7 is incoming deposited into the exposed void 6.
이와 같이 보이드 부분에 게이트 폴리(7)가 인입 증착된 상태에서 반도체 소자가 완성되면 소자의 작동시 노출된 보이드 부분에서 마이크로 브릿지(micro bridge)에 의한 모트 누설 전류가 발생된다는 문제점이 있다.As described above, when the semiconductor device is completed in the state where the gate poly 7 is drawn in and deposited on the void portion, there is a problem in that a mote leakage current is generated by a micro bridge in the exposed void portion during operation of the device.
상기 문제점을 해결하기 위한 본 발명의 목적은, 트렌치를 매립한 후에 실시되는 산화막을 제거하는 과정에서 트렌치에 매립된 산화막이 손상되는 것을 방지할 수 있도록 하는 반도체 소자의 제조방법을 제공하기 위한 것이다.An object of the present invention for solving the above problems is to provide a method of manufacturing a semiconductor device that can prevent the oxide film embedded in the trench from being damaged in the process of removing the oxide film carried out after filling the trench.
상술한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, a) 실리콘기판 상부에 패드 산화막과 질화막을 순차적으로 적층하는 단계; b) 상기 질화막 상부에 모트 패턴을 형성하며, 상기 모트 패턴을 식각 차단층으로 하여 질화막과 패드 산화막을 식각하는 단계; c) 상기 식각에 의해 드러난 실리콘 기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계; d) 노출된 실리콘기판 전면에 트렌치 갭필(Gap-fill)용 산화막이 치밀(dense)하게 증착되도록, 실리콘(Si) 공급량을 1.400 내지 1.670 ℓ/min로 공급하면서 화학기상증착법으로 증착하여 트렌치를 매립하는 단계; 및 e) 상기 질화막을 버퍼층으로 하여 화학 기계적 연마 방식으로 상기 갭필용 산화막을 연마하여 평탄화―여기서, 상기 평탄화는 상기 트렌치 산화막 내에 형성된 보이드(Void)를 외부로 노출시키지 않게 함―를 실시하는 단계를 포함한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of: a) sequentially depositing a pad oxide film and a nitride film on a silicon substrate; b) forming a mort pattern on the nitride layer, and etching the nitride layer and the pad oxide layer using the mort pattern as an etch stop layer; c) etching the silicon substrate exposed by the etching to a predetermined depth to form a trench; d) Filling the trenches by chemical vapor deposition while supplying silicon (Si) at 1.400-1.670 L / min so that the oxide film for trench gap fill is densely deposited on the exposed silicon substrate. Doing; And e) polishing the gap fill oxide film by a chemical mechanical polishing method using the nitride film as a buffer layer to planarize, wherein the planarization does not expose the voids formed in the trench oxide film to the outside. Include.
이하 본 발명에 따른 바람직한 일 실시예를 첨부된 도면에 의거하여 상세히 설명한다.Hereinafter, a preferred embodiment according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자를 제조하는 과정을 도시한 단면도이다.2A through 2F are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the present invention.
먼저 도 2a에 도시된 바와 같이, 실리콘기판(11) 상부에 패드 산화막(12)과 질화막(13)을 순차적으로 적층하고, 질화막(13) 상부에 모트(moat) 패턴을 형성한 후, 그 모트 패턴을 식각 차단층으로 하여 질화막(13)과 패드 산화막(12)을 식각하고 드러난 실리콘 기판(11)을 소정 깊이로 식각하여 트렌치(14)를 형성한다. 그리고 나서, 질화막(13) 상부의 모트 패턴을 제거한다. 상기 모트 패턴이 제거되면 후속 공정에서 트렌치(14)에 갭필되는 산화막과 실리콘 기판(11)의 접착을 용이하게 하기 위하여 열산화 공정에 의해 트렌치(14) 내벽에 열산화막(15)을 형성한다.First, as shown in FIG. 2A, the pad oxide layer 12 and the nitride layer 13 are sequentially stacked on the silicon substrate 11, and a moat pattern is formed on the nitride layer 13. Using the pattern as an etch stop layer, the nitride film 13 and the pad oxide film 12 are etched and the exposed silicon substrate 11 is etched to a predetermined depth to form the trench 14. Then, the mort pattern on the nitride film 13 is removed. When the moat pattern is removed, a thermal oxide film 15 is formed on the inner wall of the trench 14 by a thermal oxidation process to facilitate adhesion between the oxide film gap-filled in the trench 14 and the silicon substrate 11 in a subsequent process.
다음으로, 도 2b에 도시된 바와 같이, 실리콘기판(11) 전체에 트렌치 갭필용 산화막(16)을 화학기상증착법으로 증착하여 트렌치(14)를 완전히 매립한다. 이렇게 매립하는 과정에서 트렌치(14)의 내부에 매립되는 갭필용 산화막의 중심부에는 보이드(17)가 형성된다. 이러한 증착에 사용되는 산화물은 실리콘(Si) 산화물로서, 공급량이 1.400 내지 1.670 ℓ/min 되도록 공급한다. 여기서, 종래에는 통상적으로 1.683 ℓ/min를 공급하였지만, 본 발명에서는 공급량을 줄여서 1.400 내지 1.670 ℓ/min를 공급한다. 이렇게 공급량을 감소시키게 되면 산화물의 입자들이 천천히 증착됨과 동시에 충돌할 가능성이 줄게 되어 치밀한 증착이 이루어진다. 즉, 상기 트렌치 갭필용 산화막의 막질을 보다 치밀하게 함으로써, Si-O 간의 결합력이 증가되어, 후속적으로 진행되는 식각 및 세정 공정시 발생할 수 있는 트렌치 갭필용 산화막의 손실량을 최소화하게 된다.Next, as shown in FIG. 2B, the trench gap fill oxide film 16 is deposited on the entire silicon substrate 11 by chemical vapor deposition to completely fill the trench 14. In this buried process, a void 17 is formed in the center of the gap fill oxide film embedded in the trench 14. The oxide used for this deposition is silicon (Si) oxide, and is supplied so that the supply amount is 1.400 to 1.670 L / min. Here, in the past, 1.683 L / min was conventionally supplied, but in the present invention, 1.400 to 1.670 L / min is supplied by reducing the supply amount. This reduced supply reduces the chance of colliding with the particles of oxides slowly and at the same time, resulting in dense deposition. That is, by densifying the film quality of the oxide film for the trench gap fill more densely, the bonding force between the Si-O is increased, thereby minimizing the loss of the oxide film for the trench gap fill that can occur during the subsequent etching and cleaning process.
이어서, 도 2c에 도시한 바와 같이, 트렌치(14)에 갭필용 산화막(16)을 매립한 후, 상기 질화막(13)을 버퍼층으로 한 화학 기계적 연마로 갭필용 산화막(16)을 연마한다. 그러면, 화학기계적연마 공정에 의해 질화막(13) 상부에 있는 갭필용 산화막(16)은 모두 제거되고 트렌치 내에만 갭필용 산화막(16)이 매립된다.Subsequently, as shown in FIG. 2C, the gap fill oxide film 16 is embedded in the trench 14, and then the gap fill oxide film 16 is polished by chemical mechanical polishing using the nitride film 13 as a buffer layer. Then, the gap fill oxide film 16 on the nitride film 13 is all removed by the chemical mechanical polishing process, and the gap fill oxide film 16 is embedded only in the trench.
다음으로, 도 2d에 도시한 바와 같이, 모트 습식 식각을 실시하여 질화막(13) 및 패드 산화막(12)의 일부를 제거한다.Next, as shown in FIG. 2D, the wet wet etching is performed to remove a part of the nitride film 13 and the pad oxide film 12.
다음으로, 도 2e에 도시한 바와 같이, 일부 남아 있던 패드 산화막(12)을 불산 처리하여 실리콘기판(11)의 상면이 노출되도록 한다. 이때, 갭필용 산화막(16)의 성장조건에서 Si 공급량의 조절을 통해 치밀한 갭필용 산화막(16)을 형성함으로써 보이드(17)가 노출되는 현상이 발생되지 않게 된다.Next, as shown in FIG. 2E, the remaining portion of the pad oxide film 12 is hydrofluoricated to expose the top surface of the silicon substrate 11. At this time, the phenomenon in which the voids 17 are exposed by forming a dense gap fill oxide film 16 by controlling the amount of Si supplied under the growth conditions of the gap fill oxide film 16 is prevented.
상기 패드 산화막(12)이 완전히 제거되면, 도 2f에 도시한 바와 같이, 실리콘기판(11)의 전체에 게이트 폴리(18)를 증착한다.When the pad oxide film 12 is completely removed, the gate poly 18 is deposited on the entire silicon substrate 11 as shown in FIG. 2F.
본 발명에 따르면, 트렌치 산화막을 치밀화시켜 보이드가 노출되는 것을 방지함으로써, 트렌치 산화막의 증착 후에 증착되는 게이트 폴리가 보이드의 내부에 매립되지 않기 때문에 마이크로 브릿지 현상이 발생되는 것을 차단할 수 있다.According to the present invention, by densifying the trench oxide film to prevent the voids from being exposed, the micro bridge phenomenon can be prevented from occurring because the gate poly deposited after the deposition of the trench oxide film is not embedded in the voids.
따라서, 모트 누설 전류로 인한 반도체 소자의 불량을 미연에 방지할 수 있어 반도체 소자의 신뢰성과 수율을 향상시킬 수 있으며, 또한, 트렌치 산화막 공정시 종, 횡비 증가에 따른 공정 안정성을 향상시킬 수 있다.Therefore, defects of the semiconductor device due to the mort leakage current can be prevented in advance, thereby improving the reliability and yield of the semiconductor device, and also improving the process stability due to the increase in the aspect ratio in the trench oxide process.
삭제delete
도 1a 내지 도 1e는 종래의 기술에 따른 반도체 소자를 제조하는 과정을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the related art.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자를 제조하는 과정을 도시한 단면도이다.2A through 2F are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
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