KR100491396B1 - 반도체 소자의 피이-테오스(pe-teos)막 형성 방법 - Google Patents
반도체 소자의 피이-테오스(pe-teos)막 형성 방법 Download PDFInfo
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- KR100491396B1 KR100491396B1 KR10-2002-0076350A KR20020076350A KR100491396B1 KR 100491396 B1 KR100491396 B1 KR 100491396B1 KR 20020076350 A KR20020076350 A KR 20020076350A KR 100491396 B1 KR100491396 B1 KR 100491396B1
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- Prior art keywords
- teos
- chamber
- wafer
- deposition process
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 98
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 235000012431 wafers Nutrition 0.000 claims abstract description 130
- 238000005137 deposition process Methods 0.000 claims abstract description 45
- 238000004140 cleaning Methods 0.000 claims abstract description 37
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000007789 gas Substances 0.000 claims description 29
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000006227 byproduct Substances 0.000 claims description 4
- 229910001882 dioxygen Inorganic materials 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000003860 storage Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
- C23C16/4405—Cleaning of reactor or parts inside the reactor by using reactive gases
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/54—Apparatus specially adapted for continuous coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/905—Cleaning of reaction chamber
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Physics & Mathematics (AREA)
- Mechanical Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Plasma & Fusion (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (5)
- 챔버 내의 히터 테이블에 탑재된 다수개의 웨이퍼 각각에 대응되게 설치된 샤워 헤드를 통하여 공정 가스를 분사하여 PE-TEOS막을 형성하는 방법으로,(a) PE-TEOS막 증착 공정을 진행할 웨이퍼가 적재된 공급용 웨이퍼 카세트를 준비하는 단계와;(b) 실질적인 PE-TEOS 증착 공정을 진행하기 전에 상기 챔버 내부를 PE-TEOS 증착 공정을 진행할 조건과 동일한 분위기를 형성하는 단계와;(c) PE-TEOS 증착 공정을 진행할 조건과 동일한 분위기가 형성되면 상기 공급용 웨이퍼 카세트에서 웨이퍼들을 차례로 상기 챔버 내부의 상기 히터 테이블로 공급하여 설정된 클리닝 시작 시간이 될 때까지 PE-TEOS 증착 공정을 진행하는 단계와;(d) 상기 클리닝 시작 시간이 되면, 상기 공급용 웨이퍼 카세트에서 챔버로의 웨이퍼 공급을 중단하고 상기 챔버 내의 웨이퍼에 대한 PE-TEOS 증착 공정을 완료한 후 웨이퍼를 챔버 밖으로 반출한 다음 챔버 내부를 RF 클리닝하는 단계; 및(e) 상기 RF 클리닝 과정에서 상승된 상기 샤워 헤드와 챔버 내부의 온도를 낮추기 위해서, RF 파워를 끈 상태에서 상기 샤워 헤드를 통하여 상기 챔버 내부로 TEOS 가스를 분사시켜 상기 샤워 헤드와 챔버 내부의 온도를 낮추는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 피이-테오스(PE-TEOS)막 형성 방법.
- 제 1항에 있어서, 상기 (b) 단계는, 상기 히터 테이블은 350℃로 가열되며, 상기 샤워 헤드를 통하여 TEOS 가스를 분사하고 챔버 내부를 약 2Torr 압력으로 유지시킨 상태에서, RF 파워 300 내지 700W를 인가하여 플라즈마를 형성하는 것을 특징으로 하는 반도체 소자의 피이-테오스(PE-TEOS)막 형성 방법
- 제 2항에 있어서, 상기 (d) 단계는, 3Torr, 390℃의 공정 조건에서 RF 파워 300 내지 700W를 인가한 상태에서, 상기 챔버 내부에 산소 가스와 C2F6 가스를 분사하여 상기 챔버 내부에 노출된 부분에 증착된 PE-TEOS막과 더불어 부산물을 클리닝하는 것을 특징으로 하는 반도체 소자의 피이-테오스(PE-TEOS)막 형성 방법.
- 제 1항에 있어서, 상기 (e) 단계는, 0 내지 20Torr, RF 파워를 끈 상태에서, TEOS 가스를 1㎕ 내지 20㎘를 1초 내지 2시간을 분사하는 것을 특징으로 하는 반도체 소자의 피이-테오스(PE-TEOS)막 형성 방법.
- 제 4항에 있어서, 상기 (e) 단계는, 약 2Torr, RF 파워를 끈 상태에서, TEOS 가스를 2.1㎖/min의 속도로 약 250초 분사하는 것을 특징으로 하는 반도체 소자의 피이-테오스(PE-TEOS)막 형성 방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0076350A KR100491396B1 (ko) | 2002-12-03 | 2002-12-03 | 반도체 소자의 피이-테오스(pe-teos)막 형성 방법 |
US10/693,457 US7268089B2 (en) | 2002-12-03 | 2003-10-27 | Method for forming PE-TEOS layer of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0076350A KR100491396B1 (ko) | 2002-12-03 | 2002-12-03 | 반도체 소자의 피이-테오스(pe-teos)막 형성 방법 |
Publications (2)
Publication Number | Publication Date |
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KR20040048513A KR20040048513A (ko) | 2004-06-10 |
KR100491396B1 true KR100491396B1 (ko) | 2005-05-25 |
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KR10-2002-0076350A KR100491396B1 (ko) | 2002-12-03 | 2002-12-03 | 반도체 소자의 피이-테오스(pe-teos)막 형성 방법 |
Country Status (2)
Country | Link |
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US (1) | US7268089B2 (ko) |
KR (1) | KR100491396B1 (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100712729B1 (ko) * | 2007-02-09 | 2007-05-04 | 주식회사 아토 | 절연막 형성 방법 |
US7723227B1 (en) | 2009-03-24 | 2010-05-25 | Micron Technology, Inc. | Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry |
CN104616956B (zh) * | 2013-11-05 | 2017-02-08 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 等离子体刻蚀设备及方法 |
CN113529057B (zh) * | 2020-04-13 | 2023-02-28 | 长鑫存储技术有限公司 | 半导体制造方法及多片式沉积设备 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07153704A (ja) * | 1993-11-29 | 1995-06-16 | Anelva Corp | 薄膜形成方法および薄膜形成装置 |
JPH07302765A (ja) * | 1994-05-02 | 1995-11-14 | Nippon Asm Kk | 空冷式の処理装置および該装置を利用して連続して被処理体を処理する方法 |
JPH09232298A (ja) * | 1996-02-21 | 1997-09-05 | Nec Corp | プラズマcvd装置およびそのクリーニング方法 |
WO1999054522A1 (en) * | 1998-04-20 | 1999-10-28 | Tokyo Electron Arizona, Inc. | Method of passivating a cvd chamber |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US5000113A (en) * | 1986-12-19 | 1991-03-19 | Applied Materials, Inc. | Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process |
US6127261A (en) * | 1995-11-16 | 2000-10-03 | Advanced Micro Devices, Inc. | Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectric compatible with advanced CMOS technologies |
US5970383A (en) * | 1997-12-17 | 1999-10-19 | Advanced Micro Devices | Method of manufacturing a semiconductor device with improved control of deposition layer thickness |
KR100261564B1 (ko) | 1998-01-24 | 2000-07-15 | 김영환 | 반도체 화학기상증착장비의 가스 분사장치 |
KR19990076407A (ko) * | 1998-03-31 | 1999-10-15 | 윤종용 | 반도체장치의 제조공정에 있어서의 박막 형성방법 |
US6242347B1 (en) * | 1998-09-30 | 2001-06-05 | Applied Materials, Inc. | Method for cleaning a process chamber |
KR100375102B1 (ko) * | 2000-10-18 | 2003-03-08 | 삼성전자주식회사 | 반도체 장치의 제조에서 화학 기상 증착 방법 및 이를수행하기 위한 장치 |
JP2002299316A (ja) * | 2001-03-29 | 2002-10-11 | Toshiba Corp | プラズマ処理方法 |
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2002
- 2002-12-03 KR KR10-2002-0076350A patent/KR100491396B1/ko active IP Right Grant
-
2003
- 2003-10-27 US US10/693,457 patent/US7268089B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07153704A (ja) * | 1993-11-29 | 1995-06-16 | Anelva Corp | 薄膜形成方法および薄膜形成装置 |
JPH07302765A (ja) * | 1994-05-02 | 1995-11-14 | Nippon Asm Kk | 空冷式の処理装置および該装置を利用して連続して被処理体を処理する方法 |
JPH09232298A (ja) * | 1996-02-21 | 1997-09-05 | Nec Corp | プラズマcvd装置およびそのクリーニング方法 |
WO1999054522A1 (en) * | 1998-04-20 | 1999-10-28 | Tokyo Electron Arizona, Inc. | Method of passivating a cvd chamber |
Also Published As
Publication number | Publication date |
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US7268089B2 (en) | 2007-09-11 |
US20040106302A1 (en) | 2004-06-03 |
KR20040048513A (ko) | 2004-06-10 |
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