KR100475929B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR100475929B1
KR100475929B1 KR1019970079305A KR19970079305A KR100475929B1 KR 100475929 B1 KR100475929 B1 KR 100475929B1 KR 1019970079305 A KR1019970079305 A KR 1019970079305A KR 19970079305 A KR19970079305 A KR 19970079305A KR 100475929 B1 KR100475929 B1 KR 100475929B1
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ion implantation
semiconductor substrate
ions
semiconductor device
manufacturing
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KR1019970079305A
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Korean (ko)
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KR19990059108A (en
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윤성렬
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 고온에서 이온 주입 공정을 실시하여 채널링 현상을 방지하고 격자와 이온과의 충돌 확률을 넓혀 필요 이상의 깊이로 이온이 주입되는 것을 방지하는 방법에 관한 것임.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of preventing ionization at a high temperature to prevent channeling and widening a collision probability between a lattice and ions to prevent implantation of ions at a depth greater than necessary. .

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

고집적화된 반도체 소자에서 요구되는 얕은 접합은 이온 주입 공정 중 채널링 현상이 발생하여 불순물 주입 분포를 예측할 수 없는 문제점이 발생함.The shallow junctions required for highly integrated semiconductor devices have a problem in that impurity implantation distribution cannot be predicted due to channeling phenomenon during the ion implantation process.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

고온에서 이온 주입 공정을 실시하여 채널링 현상을 방지하고 격자와 이온과의 충돌 확률을 넓혀 필요 이상의 깊이로 이온이 주입되는 것을 방지함.The ion implantation process is performed at high temperature to prevent channeling phenomenon and to increase the probability of collision between the lattice and the ions, thereby preventing the ions from being implanted to more depth than necessary.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 소자의 접합부 형성 공정.Bonding part formation process of a semiconductor element.

Description

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 고온에서 이온 주입 공정을 실시하여 채널링(channeling) 현상을 방지하고 격자와 이온과의 충돌 확률을 넓혀 필요 이상의 깊이로 이온이 주입되는 것을 방지하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, a method of preventing ionization at a high temperature by preventing ionization by increasing an ion implantation process at a high temperature and increasing a collision probability between a lattice and ions. It is about.

반도체 소자의 제조 공정 중 모스 트랜지스터(MOS transistor)를 형성시키기 위한 소오스(source) 전극 및 드레인(drain) 전극 형성 공정은 가장 기본적이면서 반도체 소자의 전기적 특성을 결정짓는 중요한 기술이다. 그런데 반도체 소자가 초고집적화 됨에 따라 선폭(line width)이 0.1 ㎛ 이하인 게이트(gate)가 형성되면서 소오스 전극 및 드레인 전극의 얕은 접합(shallow junction)은 필수 불가결한 요소가 되어 왔다.A source electrode and a drain electrode forming process for forming a MOS transistor among semiconductor device manufacturing processes are the most basic and important techniques for determining electrical characteristics of semiconductor devices. However, as semiconductor devices are highly integrated, a gate having a line width of 0.1 μm or less is formed, and shallow junctions of the source electrode and the drain electrode have become an indispensable element.

도면을 참조하여 종래의 기술에 의한 반도체 소자의 제조 방법을 설명하고자 한다.With reference to the drawings will be described a method of manufacturing a semiconductor device according to the prior art.

도 1은 종래의 기술에 의한 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도이다. 반도체 기판(11) 상에 산화막(12)을 형성하고, 마스크 패턴(13)을 이용하여 반도체 기판의 선택된 영역에 이온 주입 공정을 실시한다. 이온 주입 공정시 이온 빔(ion beam)은 반도체 기판(11) 표면의 법선 성분과 약 7°의 각으로 경사지게 주입한다. 그러나 이온 주입 공정 중 채널링 현상이 발생하여 주입된 불순물 이온(dose)의 프로파일(profile) 예측을 어렵게 하는 문제점이 발생한다. 이러한 문제점을 해결하기 위한 채널링 방지 기술은 여러 가지가 있지만, 반도체 소자의 크기가 감소되고 고집적화 되어감에 따라, 이온 주입량을 제어하기 매우 어려운 실정이다. 그러므로 얕은 접합은 반도체 소자의 감소 및 고집적화에 필수적인 기술이지만, 이와 같은 채널링 현상이 발생하여 불필요한 깊이로 이온이 주입되고, 이는 반도체 소자의 신뢰성을 떨어뜨리는 요인으로 작용하게 된다.1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the prior art. An oxide film 12 is formed on the semiconductor substrate 11, and an ion implantation process is performed on a selected region of the semiconductor substrate using the mask pattern 13. In the ion implantation process, the ion beam is implanted at an angle of about 7 ° with a normal component on the surface of the semiconductor substrate 11. However, a channeling phenomenon occurs during the ion implantation process, which makes it difficult to predict a profile of the implanted impurity ions. There are a number of channeling prevention techniques to solve this problem, but as the size of the semiconductor device is reduced and highly integrated, it is very difficult to control the ion implantation amount. Therefore, the shallow junction is an essential technique for the reduction and high integration of the semiconductor device, but such a channeling phenomenon occurs and ions are implanted at an unnecessary depth, which acts as a factor that degrades the reliability of the semiconductor device.

본 발명은 얕은 접합을 형성하기 위한 이온 주입 공정시 발생하는 채널링 현상을 방지하고 주입되는 이온 농도를 제어하여 고집적 반도체 소자의 얕은 접합을 형성하는데 그 목적이 있다.An object of the present invention is to form a shallow junction of a highly integrated semiconductor device by preventing the channeling phenomenon occurring during the ion implantation process to form a shallow junction and controlling the implanted ion concentration.

상술한 목적을 달성하기 위한 반도체 소자의 제조 방법은, 반도체 기판상에 산화막을 형성하고 고온 공정에서도 마스크를 유지할 수 있는 마스크 패턴을 이용하여 반도체 기판의 선택된 영역에 이온 주입 공정을 실시하되, 상기 반도체 기판의 격자 진동 폭이 증가되는 고온 영역에서 반도체 기판 표면의 법선 성분에서 기울어진 경사진 방향으로 이온 빔을 이용한 이온 주입 공정을 실시하는 것을 포함하여 이루어지는 것을 특징으로 한다.A method of manufacturing a semiconductor device for achieving the above object is to perform an ion implantation process in a selected region of the semiconductor substrate using a mask pattern that can form an oxide film on the semiconductor substrate and maintain the mask even at a high temperature process, the semiconductor And performing an ion implantation process using an ion beam in an inclined direction inclined from a normal component of the surface of the semiconductor substrate in a high temperature region where the lattice vibration width of the substrate is increased.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도이고, 도 3(a) 및 도 3(b)는 이온 주입 농도에 따른 이온 주입 깊이를 도시한 그래프도이다.2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the present invention, and FIGS. 3A and 3B are graphs illustrating ion implantation depths according to ion implantation concentrations.

도 2에 도시된 것과 같이, 반도체 기판(21) 상에 스크린 산화막(screen oxide film ; 22)을 형성하고, 마스크 패턴(23)을 이용하여 반도체 기판(21)의 선택된 영역에 이온 주입 공정을 실시한다. 이 때 마스크 패턴(23)은 감광막을 사용하지 않고, 고온 공정에서도 마스크가 유지되도록 폴리마이드(polymide)를 사용한다. 도면에 도시된 것과 같이, 반도체 기판(21)의 선택된 영역에 이온 주입 공정을 실시하되, 250 ℃ ∼ 500 ℃의 온도 범위에서, 이온 빔을 반도체 기판(21) 표면의 법선 성분과 약 7°의 각으로 경사지게 주입한다. 위와 같은 고온에서는 반도체 기판(21) 내부의 격자(24)가 진동하는 폭이 넓어져 주입되는 이온과 충돌할 수 있는 확률이 높아진다. 따라서 위와 같이 이온 주입 공정을 고온에서 진행함으로써, 반도체 기판(21) 내의 격자(24) 진동 폭을 넓게 하여 이온 빔으로 주입되는 이온과 충돌을 야기시키고 이러한 현상으로 인해 채널링이 방지되어 이온 주입 길이 및 이온 주입량이 제어되도록 한다.As shown in FIG. 2, a screen oxide film 22 is formed on the semiconductor substrate 21, and an ion implantation process is performed on a selected region of the semiconductor substrate 21 using the mask pattern 23. do. In this case, the mask pattern 23 does not use a photosensitive film, and uses polymide to maintain the mask even at a high temperature process. As shown in the figure, an ion implantation process is performed in a selected region of the semiconductor substrate 21, but in a temperature range of 250 ° C. to 500 ° C., the ion beam is placed at about 7 ° with the normal component of the surface of the semiconductor substrate 21. Inject obliquely at an angle. At such a high temperature, the width at which the lattice 24 inside the semiconductor substrate 21 vibrates becomes wider, thereby increasing the probability of colliding with the implanted ions. Therefore, by performing the ion implantation process at a high temperature as described above, the vibration width of the lattice 24 in the semiconductor substrate 21 is widened to cause collision with the ions implanted into the ion beam, and channeling is prevented due to this phenomenon, thereby preventing ion implantation length and Allow the amount of ion implantation to be controlled.

도 3(a)는 종래의 방법으로 이온 주입 공정을 진행할 때 이온 주입 농도에 따른 이온 주입 깊이를 나타낸다. 이 경우 그래프의 중간에 채널링 현상이 발생하여 이온 주입 깊이가 제어 되지 않는 것을 알 수 있다. 그러나 도 3(b)의 본 발명에 따른 이온 주입 깊이는 채널링 현상이 방지되어 쉽게 제어할 수 있음을 나타내고 있다.Figure 3 (a) shows the ion implantation depth according to the ion implantation concentration when the ion implantation process by the conventional method. In this case, it can be seen that the channeling phenomenon occurs in the middle of the graph, and thus the ion implantation depth is not controlled. However, the ion implantation depth according to the present invention of FIG. 3 (b) shows that the channeling phenomenon is prevented and can be easily controlled.

상술한 바와 같이 본 발명에 의하면, 고집적 소자에 필요한 얕은 접합 형성 시 고온에서의 이온 주입 공정을 실시함으로써, 반도체 기판의 격자진동을 이용하여 채널링 현상을 방지하고 이온 주입 깊이를 제어할 수 있다. 따라서 신뢰성이 향상된 반도체 소자의 수율을 증가시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, by performing an ion implantation process at a high temperature when forming a shallow junction required for a highly integrated device, the channeling phenomenon can be prevented and the ion implantation depth can be controlled using the lattice vibration of the semiconductor substrate. Therefore, there is an excellent effect that can increase the yield of the semiconductor device with improved reliability.

도 1은 종래의 기술에 의한 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Sectional drawing shown for demonstrating the manufacturing method of the semiconductor element by a prior art.

도 2는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도.2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the present invention.

도 3(a) 및 도 3(b)는 이온 주입 농도에 따른 이온 주입 깊이를 도시한 그래프도.3 (a) and 3 (b) is a graph showing the ion implantation depth according to the ion implantation concentration.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 및 21 : 반도체 기판 12 및 22 : 산화막11 and 21: semiconductor substrate 12 and 22: oxide film

13 및 23 : 마스크 패턴 14 및 24 : 반도체 기판의 격자13 and 23: mask pattern 14 and 24: lattice of semiconductor substrate

Claims (3)

반도체 기판 상에 산화막을 형성하는 단계; 및Forming an oxide film on the semiconductor substrate; And 상기 반도체 기판의 격자 진동 폭이 증가되면서 마스크 패턴이 견딜 수 있는 250℃ 내지 500℃의 온도에서 상기 반도체 기판 표면의 법선 성분에서 기울어진 경사진 방향으로 반도체 기판의 선택된 영역에 이온 빔을 이용한 이온 주입 공정을 실시하는 것을 단계를 포함하는 반도체 소자의 제조 방법.Ion implantation using an ion beam in a selected region of the semiconductor substrate in an inclined direction inclined from a normal component of the surface of the semiconductor substrate at a temperature of 250 ° C. to 500 ° C. as the lattice vibration width of the semiconductor substrate is increased to withstand the mask pattern. A method of manufacturing a semiconductor device comprising the step of performing a step. 제 1 항에 있어서,The method of claim 1, 상기 마스크 패턴은 폴리마이드로 이루어진 것을 특징으로 하는 반도체 소자의 제조 방법.The mask pattern is a method of manufacturing a semiconductor device, characterized in that made of polyamide. 제 1 항에 있어서,The method of claim 1, 상기 반도체 기판 표면의 법선 성분에서 기울어진 경사진 방향은 반도체 기판 표면의 법선 성분과 7˚의 각을 이루는 것을 특징으로 하는 반도체 소자의 제조 방법.The inclined direction inclined from the normal component of the semiconductor substrate surface forms an angle of 7 ° with the normal component of the semiconductor substrate surface.
KR1019970079305A 1997-12-30 1997-12-30 Manufacturing method of semiconductor device KR100475929B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187923A (en) * 1988-01-22 1989-07-27 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH038323A (en) * 1989-06-06 1991-01-16 Nec Corp Method and apparatus for ion implantation
JPH0415916A (en) * 1990-05-09 1992-01-21 Mitsubishi Electric Corp Apparatus for ion implantation
JPH04249315A (en) * 1991-02-05 1992-09-04 Oki Electric Ind Co Ltd Manufacture of semiconductor element

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187923A (en) * 1988-01-22 1989-07-27 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH038323A (en) * 1989-06-06 1991-01-16 Nec Corp Method and apparatus for ion implantation
JPH0415916A (en) * 1990-05-09 1992-01-21 Mitsubishi Electric Corp Apparatus for ion implantation
JPH04249315A (en) * 1991-02-05 1992-09-04 Oki Electric Ind Co Ltd Manufacture of semiconductor element

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