KR950011023B1 - Structure of transistor and its making method - Google Patents

Structure of transistor and its making method Download PDF

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KR950011023B1
KR950011023B1 KR1019920015307A KR920015307A KR950011023B1 KR 950011023 B1 KR950011023 B1 KR 950011023B1 KR 1019920015307 A KR1019920015307 A KR 1019920015307A KR 920015307 A KR920015307 A KR 920015307A KR 950011023 B1 KR950011023 B1 KR 950011023B1
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insulating film
transistor
oxide film
guide ring
active region
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KR1019920015307A
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KR940004843A (en
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한정수
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금성일렉트론주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

a gate electrode formed in a predetermined portion of active area on a substrate; a guide ring formed within a field insulating film to cover the active area and for absorbing an accumulated charge. The guide ring is comprised of an insulating film thiner than the field insulating film.

Description

트랜지스터의 구조 및 제조방법Structure and manufacturing method of transistor

제1도는 종래 게이트 파괴 발생 부위를 나타낸 평면도.1 is a plan view showing a portion of a conventional gate break generation.

제2도는 종래 셀 및 주변회로의 트랜지스터 부위 공정단면도.2 is a process cross-sectional view of a transistor site of a conventional cell and peripheral circuit.

제3도는 종래 정전기 충격 방지용 트랜지스터 부위 공정단면도.3 is a cross-sectional view of a conventional electrostatic shock transistor transistor site.

제4도는 본 발명 셀 및 주변회로의 트랜지스터 부위의 공정단면도.4 is a process cross-sectional view of a transistor portion of a cell and a peripheral circuit of the present invention.

제5도는 본 발명 정전기 충격방지용 트랜지스터 부위 공정단면도.Figure 5 is a cross-sectional view of the electrostatic impact prevention transistor site of the present invention.

제6도는 제5(c)도의 평면도.6 is a plan view of FIG. 5 (c).

제7도는 본 발명의 가이드링으로의 전하 유입을 설명하기 위한 단면도.7 is a cross-sectional view for explaining charge inflow into the guide ring of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 초기산화막1 substrate 2 initial oxide film

2a : 게이트산화막 3 : 질화막2a: gate oxide film 3: nitride film

4 : 필드산화막 5 : 게이트4: field oxide film 5: gate

10 : 가이드링10: guide ring

본 발명은 정전기 충격방지용 트랜지스터의 구조 및 제조방법에 관한 것으로, 특히 필드산화막 형성시 필드산화막에 가이드링을 형성하여 이온주입으로 이한 게이트 파괴를 방지할 수 있도록 한 것이다.The present invention relates to a structure and a manufacturing method of an electrostatic shock preventing transistor, in particular to form a guide ring in the field oxide film when forming the field oxide film to prevent the gate destruction by ion implantation.

일반적으로 정전기 충력방지용 트랜지스터는 이온주입할 부분을 포토레지스트 등으로 한정(Define)하고 이온주입을 실시함으로써 대부분의 면적이 포토레지스트로 덮여 있고 이온주입할 부분도 산화막등으로 덮여있어 전하 축적에 의한 게이트 파괴의 위험성이 크다.In general, electrostatic impulse prevention transistors are limited by photoresist and the like to be implanted, and ion implantation is carried out so that most of the area is covered with photoresist and the portions to be implanted are covered with oxide film. There is a high risk of destruction.

이러한 전하 축적에 의한 게이트 파괴를 최소화하고자 전자공급 장치를 사용하여 웨이퍼 표면을 중화시키고 있으나 전자공급장치가 오염되거나 필라멘트의 단락 등 여러가지 기계, 전자적인 결함으로 인해 게이트 파괴가 발생하고 있다.In order to minimize the gate breakage caused by the charge accumulation, the wafer surface is neutralized using an electron supply device, but the gate breakdown occurs due to various mechanical and electronic defects such as contamination of the electron supply device or short circuit of the filament.

또한, 정전기 충격방지용 트랜지스터는 그 특성상 LDD 구조를 사용하고 있지 않기 때문에 특히 LDD 구조를 가지는 고집적 디바이스에서 셀 부위의 트랜지스터와 정전기 충격 방지용 트랜지스터를 동시에 형성할 수 없기 때문에 해당 트랜지스터만을 별도로 한정하므로 게이트 파괴 문제가 더욱 심각하다.In addition, since the transistor for preventing an electrostatic shock does not use an LDD structure due to its characteristics, the transistor in the cell portion and the electrostatic shock protection transistor cannot be formed at the same time, especially in a high-density device having an LDD structure. Is even more serious.

제2도의 종래 셀 및 주변회로의 트랜지스터 부위 제조공정에서 필드산화막 형성까지의 공정을 차례로 도시한 것으로 제2(a)도와 같이 실리콘 기판(1)에 초기 산화막(2)을 성장시키고 제2(b)도와 같이 초기산화막(2) 위에 질화막(3)을 형성한 후 제2(c)도와 같이 마스킹 공정에 의해 질화막(3)을 한정하며 제2(d)도와 같이 필드산화막(4)을 성장시킨 후 질화막(3)을 제거한다.FIG. 2 shows the steps from the process of fabricating the transistor region of the conventional cell and the peripheral circuit to the field oxide film formation. The initial oxide film 2 is grown on the silicon substrate 1 as shown in FIG. After the nitride film 3 is formed on the initial oxide film 2 as shown in FIG. 2, the nitride film 3 is defined by a masking process as shown in FIG. 2C, and the field oxide film 4 is grown as shown in FIG. After that, the nitride film 3 is removed.

그리고 제2(e)도와 같이 게이트(5)와 측벽(6) 형성 및 이온주입에 의한 소오스/드레인 영역(7)을 형성하여 트랜지스터를 완성한다.As shown in FIG. 2 (e), the transistor is completed by forming the source / drain regions 7 by forming the gate 5 and the sidewalls 6 and implanting the ions.

제3도는 정전기 충격방지용 트랜지스터 부위의 제조공정을 나타낸 것으로 제3(a)도 내지 제3(d)도까지는 제2(a)도 내지 제2(d)도와 동일하나 제2(e)도에서는 셀 및 주변회로의 트랜지스터 부위에만 선택적으로 포토레지스트(8)를 형성하여 이온이 주입되지 못하도록 하였고 제3(e)도에서는 정전기 충격방지용 트랜지스터 부위에 포토레지스트를 형성하지 않아 이온이 그대로 주입되도록 하였다.3 is a view illustrating a process of manufacturing a portion of an electrostatic shock preventing transistor, and FIGS. 3 (a) to 3 (d) are the same as FIGS. 2 (a) to 2 (d), but in FIG. The photoresist 8 was selectively formed only in the transistor portion of the cell and the peripheral circuit to prevent the ion from being implanted. In FIG. 3 (e), the photoresist was not formed in the transistor portion for preventing the electrostatic impact, thereby allowing the ion to be implanted as it is.

따라서, 제3도와 같은 경우 이온이 주입되면 전하들이 전기 포텐셔리 낮은 게이트 산화막 등으로 모이게 되므로 축적된 전하들에 의해 게이트 산화막 및 게이트 전극등이 파괴되었다.Accordingly, in the case of FIG. 3, when the ions are implanted, charges are collected in the electric potential low gate oxide film or the like, so that the gate oxide film and the gate electrode are destroyed by the accumulated charges.

제1도는 제3(e)도의 평면도로 게이트 파괴발생 부위(빗금친 부분)를 나타낸 것으로 9는 활성영역이다.FIG. 1 is a plan view of FIG. 3 (e), which shows a gate break generation part (hatched portion), and 9 is an active region.

본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로 정전기 충격 방지용 트랜지스터의 소오스/드레인 형성을 위한 이온 주입시 트랜지스터로 모여드는 전하들을 도중에 흡수하도록 가이드링을 형성시키는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to form a guide ring to absorb electric charges collected in a transistor during ion implantation for source / drain formation of an anti-electrostatic impact transistor.

이와 같은 목적을 달성하기 위한 본 발명은 필드산화막 형성시 폐쇄 가이드링을 필드산화막 영역에 아령형상으로 형성함을 특징으로 한다.The present invention for achieving the above object is characterized by forming a closed guide ring in the form of a dumbbell in the field oxide film area when forming the field oxide film.

이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

먼저 제4도는 본 발명의 셀 및 주변회로의 트랜지스터 부위 제조공정을 단면으로 나타낸 것으로, 제4(a)도와 같이 기판(1)에 초기산화막(2)을 형성하고 그 위의 활성영역에만 질화막(3)이 남도록 폐터닝하여 열산화 공정으로 필드영역에 필드산화막(4)을 성장시킨다.First, FIG. 4 is a cross-sectional view illustrating a process of manufacturing a transistor portion of a cell and a peripheral circuit of the present invention. As shown in FIG. 4 (a), an initial oxide film 2 is formed on a substrate 1, and only a nitride film ( 3) is left closed to grow the field oxide film 4 in the field region by the thermal oxidation process.

그리고 제4(b)도와 같이 질화막(3)을 제거하고 게이트(5)를 형성한 후 전면에 포토레지스트(8)를 형성한다.Then, as shown in FIG. 4 (b), the nitride film 3 is removed, the gate 5 is formed, and the photoresist 8 is formed on the entire surface.

여기서, 제5도는 본 발명의 정전기 충격방지용 트랜지스터 부위의 제조공정을 나타낸 것으로, 제5(a)도와 같이 기판(1) 위에 초기산화막(2)을 형성하고 그 위에 질화막(3)을 형성한 후 마스킹 공정에 의해 액티브 영역과 가이드링이 형성될 부분(액러브영역을 감싸도록 필드영역에 형성됨)의 질화막(3)만 남기고 나머지 부분의 질화막은 모두 제거한다.FIG. 5 is a view illustrating a process of manufacturing an antistatic shock transistor according to an embodiment of the present invention. As shown in FIG. 5 (a), an initial oxide film 2 is formed on a substrate 1 and a nitride film 3 is formed thereon. By the masking process, only the nitride film 3 of the portion where the active region and the guide ring are to be formed (formed in the field region to surround the love region) is left, and all the nitride layers of the remaining portion are removed.

다음에 제5(b)도와 같이 필드산화막(4)을 성장시킨 후 질화막(3)을 제거하여 가이드링(10)을 형성하고 이어서 제5(c)도와 같이 게이트산화막(2a)과 게이트(5) 및 산화막측벽(6)을 형성하고 셀 부위 및 주변회로만 선택적으로 포토레지스트(제4도의 포토레지스트(8)와 마찬가지이므로 제5도에는 도시하지 않음)로 코팅한 후 한정하고 이온주입을 실시한다.Next, after growing the field oxide film 4 as shown in FIG. 5 (b), the nitride film 3 is removed to form the guide ring 10. Then, as shown in FIG. 5 (c), the gate oxide film 2a and the gate 5 are formed. ) And the oxide side wall 6 is formed, and only the cell part and the peripheral circuit are coated with a photoresist (the same as the photoresist 8 of FIG. 4, not shown in FIG. 5), and then limited and ion implantation is performed. do.

여기서, 상기 가이드링(10)에 얇은 산화막을 형성할 수 있다.Here, a thin oxide film may be formed on the guide ring 10.

따라서, 제5(c)도에 화살표로 도시한 바와 같이 정전기 충격방지용 트랜지스터 부위 위에서 가이드링(10)이 형성된 부분으로 많은 전하가 흡수되어 액티브 영역과 게이트 접면으로 전하가 흡수되는 경우 또는 필드산화막과 게이트 전극의 접면으로 전하가 흡수되는 경우에 전하의 흡수율을 감소시켜 준다.Therefore, as shown by an arrow in FIG. 5 (c), when a large amount of charge is absorbed to the portion where the guide ring 10 is formed on the portion of the electrostatic shock protection transistor, the charge is absorbed to the active region and the gate contact surface, When the charge is absorbed to the contact surface of the gate electrode reduces the absorption rate of the charge.

제6도는 상기 제5(c)도의 평면도를 나타낸 것으로, 가이드링(10)이 아령 형상으로 형성되어 있음을 알 수 있으며 여기서, 11영역은 Vcc전원 공급부이다.FIG. 6 is a plan view of FIG. 5 (c), and it can be seen that the guide ring 10 is formed in a dumbbell shape, where region 11 is a Vcc power supply unit.

또한, 제7도는 가이드링(10)에서 전하를 흡수하는 원리를 설명하기 위한 도면으로 이러한 전하흡수는 게이트산화막(2a)과 필드산화막(4) 사이의 두께의 차에 따른 전위 분포의 차에 의한 것으로 예를 들어 필드산화막(4)의 두께를 S1이라고 하고 게이트산화막(2a)의 두께를 S2라고 하면 각각의 전위가및로 표시되므로 두께의 차이에 의해 일어나는 전위차로 인하여 가이드링(10)에서 전하를 흡수할 수 있는 것이다.7 is a view for explaining the principle of absorbing charge in the guide ring 10. The charge absorption is caused by the difference in potential distribution according to the difference in thickness between the gate oxide film 2a and the field oxide film 4; For example, if the thickness of the field oxide film 4 is S 1 and the thickness of the gate oxide film 2a is S 2 , each potential is And Since it is indicated by the potential difference caused by the difference in thickness will be able to absorb the charge in the guide ring (10).

이상에서 설명한 바와 같이 본 발명은 필드산화막(4) 형성시 동시에 가이드링(10)을 형성하여 이온주입시 전하를 흡수하므로 게이트(5)가 파괴되는 것을 방지할 수 있는 효과가 있다.As described above, the present invention has the effect of preventing the gate 5 from being destroyed because the guide ring 10 is formed at the same time when the field oxide film 4 is formed to absorb charges when implanting ions.

Claims (3)

기판의 액티브영역 소정부위에 형성된 게이트전극과, 상기 액티브영역을 감싸도록 필드절연막 내에 형성된 축적전하를 흡수하는 가이드링을 포함하여 구성됨을 특징으로 하는 트랜지스터의 구조.And a gate electrode formed on a predetermined portion of the active region of the substrate, and a guide ring for absorbing the accumulated charge formed in the field insulating layer to surround the active region. 기판위에 제1절연막과 제2절연막을 형성하고 상기 제2절연막을 선택적으로 식각하여 액티브영역과 액티브영역을 감싸도록 필드영역에 잔존시키는 공정과, 선택 식각된 제2절연막을 마스크로 이용하여 필드절연막을 형성하고 제2절연막을 제거하는 공정과, 상기 액티브영역에 게이트전극을 형성하고 상기 게이트전극을 마스크로 이용하여 액티브영역의 기판에 불순물 이온주입하는 공정을 포함하여 이루어짐을 특징으로 하는 트랜지스터의 구조.Forming a first insulating film and a second insulating film on the substrate and selectively etching the second insulating film to remain in the field region to surround the active region and the active region; and using the selective etched second insulating layer as a mask, a field insulating film. And forming a gate electrode in the active region and implanting impurity ions into a substrate in the active region using the gate electrode as a mask. . 제1항에 있어서, 상기 가이드링은 필드절연막보다 얇은 절연막으로 형성됨을 특징으로 하는 트랜지스터의 구조.The structure of a transistor according to claim 1, wherein the guide ring is formed of an insulating film thinner than a field insulating film.
KR1019920015307A 1992-08-25 1992-08-25 Structure of transistor and its making method KR950011023B1 (en)

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