KR100472174B1 - Manufacturing Method of Liquid Crystal Display Using Overlapping Exposure - Google Patents
Manufacturing Method of Liquid Crystal Display Using Overlapping Exposure Download PDFInfo
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- KR100472174B1 KR100472174B1 KR1019970025332A KR19970025332A KR100472174B1 KR 100472174 B1 KR100472174 B1 KR 100472174B1 KR 1019970025332 A KR1019970025332 A KR 1019970025332A KR 19970025332 A KR19970025332 A KR 19970025332A KR 100472174 B1 KR100472174 B1 KR 100472174B1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
이 발명은 액정 표시 장치의 패널에서 샷간의 미세한 불연속성에 의해 스티치가 발생하는 화소 전극 또는 소스/드레인의 패터닝(patterning)에 적합한 액정 표시 장치의 제조방법에 관한 것으로서, BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display device suitable for patterning a pixel electrode or a source / drain in which stitches are generated due to minute discontinuity between shots in a panel of a liquid crystal display device.
형성하고자 하는 패턴의 물질이 도포된 기판에 감광제를 표면 전체에 걸쳐 도포하는 제1공정; 상기 제1공정 후, 상하 방향으로 서로 인접하는 두 샷이 적어도 1열 이상의 화소패턴들이 서로 중첩하도록 마스크를 위치시킨 상태에서 자외선을 조사시키는 노광 공정을 전체 기판에 대해 수행하는 제2공정; 및 현상에 의해 노광된 영역을 제거하고, 노광되지 않은 감광막의 패턴을 마스크로 하여 식각 공정을 수행하여 의도하는 패턴을 형성하는 제3공정을 포함하며,A first step of applying a photosensitive agent over the entire surface of the substrate on which the material of the pattern to be formed is applied; A second step of performing an exposure step on the entire substrate after the first step, irradiating ultraviolet rays with two shots adjacent to each other in the vertical direction in a state where a mask is positioned so that at least one column or more pixel patterns overlap each other; And a third step of removing the region exposed by the development and performing an etching process using the pattern of the unexposed photosensitive film as a mask to form an intended pattern.
각 샷의 경계부분에 해당하는 화소전극을 형성함에 있어 중첩 노광을 수행함으로써 상하 방향으로 인접하는 두 샷의 불연속성으로 인한 스티치 불량을 감소시킬 수 있다In forming the pixel electrode corresponding to the boundary of each shot, the overlapping exposure can be performed to reduce the stitch defect due to the discontinuity of two adjacent shots in the vertical direction.
Description
이 발명은 중첩 노광을 이용한 액정 표시 장치의 제조방법에 관한 것으로서, 더욱 상세하게는 액정 표시 장치의 패널에서 샷간의 미세한 불연속성에 의해 스티치가 발생하는 화소 전극 또는 소스/드레인의 패터닝(patterning)에 적합한 포토 레지스트 공정에 관한 것이다. The present invention relates to a method for manufacturing a liquid crystal display device using superimposed exposure, and more particularly, is suitable for patterning a pixel electrode or a source / drain in which a stitch is generated due to minute discontinuity between shots in a panel of the liquid crystal display device. It relates to a photoresist process.
일반적인 액정 표시 장치에서, 데이타 라인 또는 소스/드레인과 같은 금속 패터닝 또는 화소 전극과 같은 ITO(indium tin oxide) 패터닝을 수행하기 위해서는 포토 레지스트 공정이 수행되어야 한다. In a typical liquid crystal display, a photoresist process must be performed to perform metal patterning such as data lines or sources / drains or indium tin oxide (ITO) patterning such as pixel electrodes.
그런데, 액정 표시 장치 패널의 화소전극은 미세한 불연속성에도 큰 영향을 받는다. 예를 들어, 노광을 한 번 실시하는 단위인 샷을 수행함에 있어서, 마스크가 인접 샷과 조금만 일치하지 않아도 패널의 특성에 큰 영향이 생긴다. 도1에는 데이타 라인 패턴을 형성한 상태에서 화소전극을 형성하기 위한 ITO 패터닝을 수행하는 과정이 도시되어 있으며, 특히, 두 샷에서 미스얼라인(misalign)으로 인해 데이타 라인 패턴과 ITO 패턴간의 거리가 불일치함을 볼 수 있다. However, the pixel electrode of the liquid crystal display panel is also greatly influenced by fine discontinuities. For example, in performing a shot, which is a unit of performing exposure once, a large influence on the characteristics of the panel may occur even if the mask does not coincide with the adjacent shot only slightly. FIG. 1 illustrates a process of performing ITO patterning for forming a pixel electrode in a state in which a data line pattern is formed. In particular, the distance between the data line pattern and the ITO pattern due to misalignment in two shots is shown. You can see the inconsistency.
상기 도1에 도시된 바와 같이, A샷에서는 데이타 라인의 패턴과 ITO 패턴간의 거리가 a인 반면, B샷에서는 그 거리가 b이며, a>b보다 크다. 이에 따라, 데이타 라인과 화소 전극간의 커플링 커패시턴스(coupling capacitance)는 C2>C1이 된다. 여기서, C1은 A샷에서의 커플링 커패시턴스이고, C2는 B샷에서의 커플링 커패시턴이다. 상기한 커플링 커패시턴스의 차이로 인해, 도1의 영역(10)에 도시된 바와 같이, 두 샷에 해당하는 화소들의 경계면에서는 밝기 차이가 생기며, 이것은 액정 표시 장치의 품질에 치명적인 결함을 가져온다. 상기한 두 샷간의 불연속성으로 인한 불량을 스티치 불량이라고 부르고 있으며, 당업계에서는 액정 표시 장치의 제조공정에서 이를 제거하는 방안이 모색되고 있다.As shown in FIG. 1, in the shot A, the distance between the data line pattern and the ITO pattern is a, while in the shot B, the distance is b, which is greater than a> b. Accordingly, the coupling capacitance between the data line and the pixel electrode becomes C2> C1. Where C1 is the coupling capacitance at A-shot and C2 is the coupling capacitance at B-shot. Due to the difference in coupling capacitance described above, as shown in the
본 발명은 상기와 같은 종래의 기술적 문제점을 해결하기 위한 것으로서, 다중 노광을 이용하여 샷의 경계면에서 발생하는 스티치 불량을 제거할 수 있는 액정 표시 장치의 제조방법을 제공하는 데 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a liquid crystal display device capable of eliminating the above-described technical problem and eliminating stitch defects occurring at an interface of a shot using multiple exposures.
이 발명에 따른 액정 표시 장치의 제조방법은, 형성하고자 하는 패턴의 물질이 도포된 기판에 감광제를 표면 전체에 걸쳐 도포하는 제1공정; 상기 제1공정 후, 상하 방향으로 서로 인접하는 두 샷이 적어도 1열 이상의 화소패턴들이 서로 중첩하도록 마스크를 위치시킨 상태에서 자외선을 조사시키는 노광 공정을 전체 기판에 대해 수행하는 제2공정; 및 현상에 의해 노광된 영역을 제거하고, 노광되지 않은 감광막의 패턴을 마스크로 하여 식각 공정을 수행하여 의도하는 패턴을 형성하는 제3공정을 포함한다.The manufacturing method of the liquid crystal display device which concerns on this invention is the 1st process of apply | coating a photosensitive agent on the whole surface to the board | substrate with which the substance of the pattern to form is apply | coated; A second step of performing an exposure step on the entire substrate after the first step, irradiating ultraviolet rays with two shots adjacent to each other in the vertical direction in a state where a mask is positioned so that at least one column or more pixel patterns overlap each other; And a third step of removing the region exposed by development and performing an etching process using the pattern of the unexposed photosensitive film as a mask to form an intended pattern.
상기한 이 발명의 목적, 특징 및 잇점은 도면을 참조한 아래의 상세한 실시예 설명으로부터 보다 명백해질 것이다. The objects, features and advantages of this invention described above will become more apparent from the following detailed description of the embodiments with reference to the drawings.
이하, 첨부된 도면을 참조하여 이 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2는 이 발명의 실시예에 따른 제조방법에 의해 형성되는 액정 표시 장치의 패턴도이고,2 is a pattern diagram of a liquid crystal display device formed by a manufacturing method according to an embodiment of the present invention;
도3은 이 발명의 실시예에 따른 제조방법의 공정 순서도이다.3 is a process flowchart of a manufacturing method according to an embodiment of the present invention.
먼저, 도3의 순서도를 참조하여 이 발명의 실시예에 따른 액정 표시 장치의 제조방법을 공정순서에 따라 설명한다.First, a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the flowchart of FIG. 3.
상기 도3의 순서도는 액정 표시 장치의 전체 제조공정 중 포토 레지스트 공정에 해당하는 것으로서, 기판 상에 데이타 라인 패턴과 게이트 패턴이 이미 형성되어 있는 것으로 가정한다. The flowchart of FIG. 3 corresponds to a photoresist process in the entire manufacturing process of the liquid crystal display, and assumes that a data line pattern and a gate pattern are already formed on the substrate.
공정이 시작되면(S1), 기판 표면에 감광제가 도포된다(S2). 다음으로, 상기 도포된 감광제를 경화시키기 위한 1차 열처리가 수행되며(S3), 이 열처리는 소프트 베이크(soft bake)라 일컬어진다. When the process starts (S1), a photosensitive agent is applied to the surface of the substrate (S2). Next, a primary heat treatment for hardening the applied photosensitive agent is performed (S3), and this heat treatment is called a soft bake.
상기 열처리 공정이 완료되면, 마스크를 이용하여 자외선을 조사시키는 중첩 노광 공정이 수행된다. 상기 마스크에는 화소 전극이 패터닝되어 있으며, 특히, 상부 1열과 하부 1열은 각각 화소 전극의 1/2에 해당하는 크기가 형성되어 있다. 그리고, 상기 마스크는 상하방향으로 인접하는 샷에 1열의 화소전극들이 중첩되도록 위치한다. 본 실시예에서는 중첩 노광시 상하방향으로 인접하는 샷의 화소전극들이 1열씩 중첩하도록 마스크를 위치시켰으나, 본 발명의 기술적 범위는 여기에 한정되지 않고, 적어도 1열 이상의 화소전극들이 중첩되도록 마스크를 위치시키는 것이 가능하다. 이러한 노광에 의해, 도2에 도시된 바와 같이, A샷의 가장 아래열의 화소전극은 A샷에 의한 반의 화소전극과 B샷에 의한 반의 화소전극으로 이루어지며, B샷의 가장 윗열의 화소전극은 A샷에 의한 반의 화소전극과 B샷에 의한 반의 화소전극으로 이루어진다. 따라서, 두 샷의 경계부분에 위치하는 화소전극에 의한 커플링 커패시턴스는 각 샷의 커플링 커패시턴스(C1, C2)의 산술 평균값[(C1+C2)/2]이 되며, 영역(20)에 도시된 바와 같이, 전체 패널에서 상기 두 샷의 경계부분에 위치하는 화소 전극들은 중간 밝기를 유지하여 밝기에 있어서 완충작용을 한다. When the heat treatment process is completed, an overlapping exposure process of irradiating ultraviolet rays using a mask is performed. Pixel masks are patterned on the mask, and in particular, upper and lower rows are formed to have a size corresponding to 1/2 of the pixel electrodes, respectively. The mask is positioned so that one column of pixel electrodes overlaps a shot adjacent to each other in the vertical direction. In the present exemplary embodiment, the mask is positioned so that pixel electrodes of shots adjacent to each other in the vertical direction overlap each other in the overlapping exposure. However, the technical scope of the present invention is not limited thereto, and the mask is positioned such that at least one pixel electrode overlaps. It is possible to let. As a result of this exposure, as shown in Fig. 2, the pixel electrode in the bottom row of the A shots is composed of half the pixel electrodes by the A shots and the half pixel electrodes by the B shots, and the pixel electrodes in the top row of the B shots are It consists of a half pixel electrode by A shot and a half pixel electrode by B shot. Therefore, the coupling capacitance by the pixel electrode positioned at the boundary of the two shots is the arithmetic mean value [(C1 + C2) / 2] of the coupling capacitances C1 and C2 of each shot, and is shown in the
상기 노광 공정이 완료하면, 노광된 영역을 제거하기 위한 현상공정이 수행되며(S5), 이어서, 상기 현상 공정에 의해 약화된 감광막을 강화시키기 위한 2차 열처리가 수행된다(S6). 상기 2차 열처리는 하드 베이크(hard bake)라고 불리워진다.When the exposure process is completed, a developing process for removing the exposed region is performed (S5), and then a second heat treatment for strengthening the photosensitive film weakened by the developing process is performed (S6). The secondary heat treatment is called a hard bake.
다음으로, 상기 제거되지 않은 감광막을 마스크로 하여 식각 공정이 수행되며, 이로 인해 화소 전극의 ITO패턴이 형성된다(S7). 상기 식각 공정이 완료되면, 상기 감광막을 제거하기 위한 박리 공정이 수행되며(S8), ITO 패턴을 형성하기 위한 포토 레지스트 공정이 완료된다(S9).Next, an etching process is performed using the non-removed photoresist as a mask, thereby forming an ITO pattern of the pixel electrode (S7). When the etching process is completed, a peeling process for removing the photoresist film is performed (S8), and a photoresist process for forming an ITO pattern is completed (S9).
상기 도2를 참조하면, A샷의 가장 하부에 형성되는 화소전극들의 반은 A샷 아래의 B샷 수행시 형성되며, B샷의 가장 상부에 형성되는 화소전극들의 반은 A샷 수행시 형성된다. 이에 따라, 각 샷의 경계 부분에 형성되는 화소전극들은 상하 방향으로 인접하는 두 샷의 중간적인 속성을 가지며, 커플링 커패시턴스도 산술 평균값이다. 상기한 산술 평균적인 커플링 커패시턴스에 의해 상기 경계부분에서의 화소전극은 중간적인 밝기를 가지므로, 부드러운 밝기 변화가 이루어지며, 스티치 불량을 감소시킨다. Referring to FIG. 2, half of the pixel electrodes formed at the bottom of the A shot are formed when performing the B shot under the A shot, and half of the pixel electrodes formed at the top of the B shot are formed when the A shot is performed. . Accordingly, the pixel electrodes formed at the boundary of each shot have intermediate properties of two shots adjacent in the vertical direction, and the coupling capacitance is also an arithmetic mean value. Due to the arithmetic average coupling capacitance, the pixel electrode at the boundary portion has an intermediate brightness, so that a smooth brightness change is made and the stitch defect is reduced.
상기한 바와 같이, 이 발명의 실시예에 따른 액정 표시 장치의 제조방법은 각 샷의 경계부분에 해당하는 화소전극을 형성함에 있어 중첩 노광을 수행함으로써 상하 방향으로 인접하는 두 샷의 불연속성으로 인한 스티치 불량을 감소시킬 수 있다. 특히, 상기 방법은 도트 반전(dot inversion) 구동용 패널에 사용하기에 적합하며, 고정세의 패널을 제작시에 화소전극 보정 공정을 스킵하는 것을 가능하게 한다. 또한, 추가 공정없이 마스크의 간단한 변경만으로 실현할 수 있다는 잇점이 있다. As described above, the manufacturing method of the liquid crystal display according to the exemplary embodiment of the present invention stitches due to discontinuity of two adjacent shots in the vertical direction by performing overlapping exposure in forming the pixel electrode corresponding to the boundary of each shot. Defects can be reduced. In particular, the method is suitable for use in a panel for driving dot inversion, and makes it possible to skip the pixel electrode correction process when producing a high-definition panel. In addition, there is an advantage that it can be realized by a simple change of the mask without an additional process.
비록 이 발명은 가장 실제적이며 바람직한 실시예를 참조하여 설명되었지만, 이 발명은 상기 개시된 실시예에 한정되지 않으며, 후술되는 청구의 범위 내에 속하는 다양한 변형 및 등가물들도 포함한다.Although this invention has been described with reference to the most practical and preferred embodiments, the invention is not limited to the embodiments disclosed above, but also includes various modifications and equivalents which fall within the scope of the following claims.
도1은 종래의 기술에 따른 노광시 샷간의 경계면에서 발생하는 불연속성을 설명하는 패턴도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a pattern diagram illustrating discontinuity occurring at the interface between shots during exposure according to the prior art.
도2는 이 발명의 실시예에 따른 제조방법에 의해 형성되는 액정 표시 장치의 패턴도.2 is a pattern diagram of a liquid crystal display device formed by the manufacturing method according to the embodiment of the present invention.
도3은 이 발명의 실시예에 따른 제조방법의 공정 순서도. 3 is a process flowchart of a manufacturing method according to an embodiment of the present invention.
Claims (4)
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|---|---|---|---|---|
| JPH01108526A (en) * | 1987-10-22 | 1989-04-25 | Fujitsu Ltd | Manufacture of thin film transistor matrix |
| JPH05107547A (en) * | 1991-10-14 | 1993-04-30 | Canon Inc | Liquid crystal display element |
| KR950003895A (en) * | 1993-07-26 | 1995-02-17 | 이또 겐 | Method for manufacturing a substrate having a window type and a frame type coating film formed on the surface |
| JPH07287248A (en) * | 1994-04-15 | 1995-10-31 | Sharp Corp | Manufacture of active matrix substrate |
| KR960018698A (en) * | 1994-11-24 | 1996-06-17 | 사토 후미오 | Electrode substrate, its manufacturing method and display device using same |
| KR960032059A (en) * | 1995-02-11 | 1996-09-17 | 김광호 | Method for manufacturing thin film transistor substrate for fully self-aligning liquid crystal display |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01108526A (en) * | 1987-10-22 | 1989-04-25 | Fujitsu Ltd | Manufacture of thin film transistor matrix |
| JPH05107547A (en) * | 1991-10-14 | 1993-04-30 | Canon Inc | Liquid crystal display element |
| KR950003895A (en) * | 1993-07-26 | 1995-02-17 | 이또 겐 | Method for manufacturing a substrate having a window type and a frame type coating film formed on the surface |
| JPH07287248A (en) * | 1994-04-15 | 1995-10-31 | Sharp Corp | Manufacture of active matrix substrate |
| KR960018698A (en) * | 1994-11-24 | 1996-06-17 | 사토 후미오 | Electrode substrate, its manufacturing method and display device using same |
| KR960032059A (en) * | 1995-02-11 | 1996-09-17 | 김광호 | Method for manufacturing thin film transistor substrate for fully self-aligning liquid crystal display |
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