JPH09179141A - Liquid crystal display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a difference in luminance generated at the border line of split exposure to be viewed by an observer and suppress display unevenness of an image display as much as possible by providing a drain electrode which projects from a drain bus line while overlapping with a gate electrode and pixel electrodes which are connected to 1st and 2nd source electrodes arranged opposite across the gate electrode. SOLUTION: This panel is provided with the gate electrode 12 of a thin film transistor, the drain electrode 17 of the thin film transistor which projects from the drain bus line 17A while overlapping with the gate electrode 12, and 1st and 2nd source electrodes 16A and 16B of the thin film transistor which are arranged opposite across the gate electrode 12. Even if a reticle shifts in position at the time of split exposure, to cause the patterns of, specially, the patterns of the gate electrode 12 and 1st and 2nd source electrodes 16A and 16B shift in position, the area of overlaps with the respective electrodes is constant on the whole since the 1st and 2nd source electrodes 16A and 16B are arranged opposite across the gate electrode 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a thin film transistor.
This invention relates to a liquid crystal display panel in which a sistor (TFT) matrix is formed. 2. Description of the Related Art In recent years, a liquid crystal display panel (hereinafter referred to as a TFT liquid crystal panel) equipped with a TFT matrix has been required to have improved image display quality in accordance with higher definition and higher gradation.

[0002]

2. Description of the Related Art The structure of a conventional TFT liquid crystal panel will be described below. FIG. 8A shows the TF according to the conventional example.
9 is a top view illustrating the structure of the T liquid crystal panel, and FIG.
(B) is the sectional view on the AA line of the same figure (a). In FIG. 8, 1 is a transparent substrate made of a glass substrate, 2 is a gate electrode, 2A is a gate bus line, and 3 is a gate insulating film. Further, 4 is an operating semiconductor layer made of amorphous silicon, 5 is a channel protective film, and 6 is a source electrode. Further, 7 is a drain electrode, and 7A is a drain bus line. Further, 8 is a pixel electrode, and 9 is an auxiliary capacitance bus line forming an auxiliary capacitance of the pixel.

First, the layout of the respective parts of the TFT liquid crystal panel as viewed from above will be described with reference to FIG. As shown in FIG. 8A, the gate bus line 2
A and the drain bus line 7A are orthogonally arranged in a matrix, and the pixel electrode 8 is arranged in a region surrounded by these. Further, the auxiliary capacitance bus line 9 is connected to the pixel electrode 8
It is arranged so as to cross the center of.

From the gate bus line 2A to the gate electrode 2
Are projected in the direction of the pixel electrode 8, and two drain electrodes 7 are arranged so as to project in the direction of the gate electrode 2 from the drain bus line. Further, the two source electrodes 6 connected to one end of the pixel electrode 8 are arranged so as to project in the direction of the gate electrode 2, and thus two TFTs having a common gate for one pixel are formed. It will be.

Next, the sectional structure of this device is shown in FIG.
This will be described with reference to FIG. As shown in FIG. 8B, a gate electrode 2 is formed on a transparent substrate 1 made of glass or the like, and a gate insulating film 3 is formed so as to cover it. An operating semiconductor layer 4 that forms the channel layer of the TFT is formed thereon. An insulating channel protective film 5 is formed in a region where a channel is formed on the operating semiconductor layer 4, and a source electrode 6 and a drain electrode 7 are formed on both sides of the insulating channel protective film 5 to form a TFT. A pixel electrode 8 made of an ITO (Indium TiN Oxide) film is formed on the source electrode 6, and the pixel electrode 8 is formed up to the pixel region.

A transparent substrate (not shown) having a counter electrode made of a transparent conductive film formed on the surface of the above-mentioned substrate is disposed so as to face the substrate, and liquid crystal LC is sealed between these substrates.
An FT liquid crystal panel is constructed. FIG. 9 shows an equivalent circuit diagram of FIG. 8 for one pixel. As shown in FIG. 9, two TFTs are connected in parallel, and a pixel electrode is connected to the source thereof.

In FIG. 9, CL is the capacitance of the liquid crystal in the pixel region, Cs is the auxiliary capacitance related to the auxiliary capacitance bus line, Cgs1 and Cgs2 are the capacitances between the gate and the source, the magnitude of which is the gate electrode of FIG. 2 depends on the sum of the overlapping areas of 2 and the source electrode 6. When the gate-source capacitances Cgs1 and Cgs2 are increased, even if the same gate voltage is applied to the gate electrode 2 from the gate bus line, the potential of the source electrode 6, that is, the pixel electrode 8 is affected by the fall of the gate voltage. Since the voltage drops, the potential applied to the pixel electrode 8 becomes lower and the brightness of the pixel lowers as compared with the case where both the gate-source capacitances Cgs1 and Cgs2 are small.

When manufacturing a TFT liquid crystal panel having the above structure, an exposure step is essential because a photolithography method is used for patterning. In general, a TFT liquid crystal panel is as large as about 10 to 14 inches, and therefore it is difficult to manufacture one reticle that can handle the TFT liquid crystal panel. Method is used.

In this method, one TFT liquid crystal panel LP is used.
Is a method of dividing a panel area into a plurality of areas, preparing a reticle for each area, and exposing.
Specifically, as shown in FIG. 10, the panel LP is divided into four regions A1 to A4, and the divided region A1 is divided into four regions.
.. A4 reticle r1 to r4 corresponding to the exposure patterns A4 to A4 are prepared, and one large TFT liquid crystal panel is exposed by changing exposure for each region.

[0010]

However, when a TFT liquid crystal panel is manufactured by using the above divided exposure, the following problems occur. That is, for the convenience of preparing and exposing a plurality of reticles, in many areas near the boundary between the different reticles, a misalignment of the reticles often causes a deviation in image display.

As an example, as shown in FIG. 11A, for the pixel LG on the left side of the boundary line TM when using different reticles for division exposure, the corresponding reticles are correctly aligned. However, in the pixel RG on the right side of the boundary line TM, a case where the corresponding reticle is slightly displaced in the X direction will be described.

With respect to the pixel LG on the left side, the alignment of the reticle was correctly performed, so that the gate electrode 2 and the source electrode 6 were
The overlapping area of is a value expected in the design, and the capacitances Cgs1 and Cgs2 between these are the same as the values expected in the design, but for the pixel RG on the right side, the alignment of the reticle is misaligned. , The overlapping area of the gate electrode 2 and the source electrode 6 is smaller than a value expected by design, and the capacitances Cgs1 and Cgs2 between them are also smaller than that of the pixel LG on the left side.

Therefore, even if the same gate voltage is applied,
Due to the phenomenon that the potential of the source electrode 6 decreases in accordance with the fall of the gate voltage, the capacitance Cgs is larger than the voltage actually applied to the pixel electrode 8 where the capacitances Cgs1 and Cgs2 are large.
Since the voltage actually applied to the pixel electrode 8 having a smaller gs1 and Cgs2 becomes higher, the difference in luminance between the left pixel LG and the right inter-pixel RG as shown in FIG. 11B. Occurs. Since this difference in brightness occurs along the dividing line TM, a difference in brightness occurs across the boundary line, especially when a monochrome screen of a still image, for example, a blue sky is displayed on one side. Therefore, there is a problem in that the display is unevenly displayed, which causes uneven display.

The present invention has been made in view of the problems of the conventional example, and it is possible to reduce the difference in brightness generated at the boundary line of the above-described divided exposure and make the brightness difference visible to an observer. An object of the present invention is to provide a liquid crystal display panel capable of suppressing display unevenness during image display as much as possible.

[0015]

The present invention has been made in view of the above problems, and as shown in FIG. 1, a plurality of gate bus lines 12 and drain bus lines 17A are formed on a transparent insulating substrate 11. A thin film transistor for driving is arranged in a matrix form via an interlayer insulating film, a driving thin film transistor is arranged in the vicinity of an intersection of the gate bus line 12 and the drain bus line 17A, and a pixel electrode 18 is provided on a source electrode 16A, 16B of the thin film transistor. A liquid crystal display panel configured by sandwiching a liquid crystal layer between a first transparent substrate that is connected and a second transparent substrate having at least a counter electrode formed on a transparent insulating substrate, the gate bus line The gate electrode 12 of the thin film transistor formed of a part of the thin film transistor 12 and the drain of the thin film transistor protruding from the drain bus line 17A so as to overlap with the gate electrode 12. A liquid crystal display panel characterized by having a gate electrode 17 and first and second source electrodes 16A, 16B of the thin film transistor which are arranged to face each other with the gate electrode 12 interposed therebetween, and the gate bus line 12 is The liquid crystal according to the present invention is arranged so as to cross the center of the pixel electrode 18, and auxiliary capacitance bus lines 19A and 19B are arranged at both ends of the pixel electrode 18 in parallel with the gate bus line 12. A display panel, a liquid crystal display panel according to the present invention in which the area of the pixel electrode 18 is small in a region intersecting with the gate bus line 12, and the gate bus line 22 as shown in FIG. The liquid crystal display panel according to the present invention is characterized in that the pixel electrodes 28A and 28B are divided in a region intersecting with the above problem.

Subsequently, the function and effect of the present invention will be described below. According to the present invention, the drain electrode protruding from the drain bus line so as to overlap with the gate electrode formed of a part of the gate bus line, and the first and second source electrodes arranged to face each other with the gate electrode interposed therebetween. , And a pixel electrode connected to the first and second source electrodes.

Therefore, even if the reticle is misaligned during the divided exposure, and especially if the patterns of the gate electrode and the first and second source electrodes are misaligned, the first and the second electrodes sandwich the gate electrode. Since the second source electrodes are arranged so as to face each other, even if the overlapping area of the first source electrode and the gate electrode decreases, the overlapping area of the second source electrode and the gate electrode increases by the decrease amount. Therefore, as a whole, the area where the gate electrode and the first and second source electrodes overlap with each other remains constant.

Since this is always constant regardless of any positional deviation in the divided exposure, the total capacitance between the first and second source electrodes and the gate electrode is constant regardless of the divided regions. . Therefore, if the voltage applied to the gate bus line is constant because the sum of the above capacitances is constant, the voltage applied between the gate and the source is always kept constant over the entire exposure area. It is possible to suppress the occurrence of display unevenness due to a difference in brightness between these areas, which is visually recognized.

In the present invention, the area of the pixel electrode may be reduced in the region intersecting with the gate bus line.
In this case, since the area where the gate bus line and the pixel electrode intersect becomes small and the capacitance generated between them is reduced, even if this capacitance varies a little due to the displacement, the effect of the display unevenness is almost visible. It becomes possible to suppress it to the extent that it is not done.

Further, in the present invention, the pixel electrode may be divided in a region intersecting with the gate bus line. In this case, the area where the gate bus line and the pixel electrode intersect is 0.
Since no capacitance is generated between them, it is possible to suppress display unevenness that may occur due to the variation in capacitance.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

(1) First Embodiment FIG. 1 shows an embodiment of the present invention. FIG. 1 shows the TF of the present invention.
It is a top view explaining the structure of the pixel periphery of T liquid crystal panel. 2A is a sectional view taken along line XX of FIG. 1, and FIG. 2B is an equivalent circuit diagram of FIG.

1 and 2A, 11 is a transparent substrate, 12 is a gate electrode, 13 is a gate insulating film, 14 is an operating semiconductor layer made of amorphous silicon, 15 is a channel protective film, and 16 is a source electrode. Is a drain electrode, and 18 is a pixel electrode. Reference numerals 19A and 19B are auxiliary capacitance bus lines. The structure of this TFT liquid crystal panel will be described below. First, the positional relationship between the respective parts of the TFT liquid crystal panel as viewed from above will be described with reference to FIG.

This TFT liquid crystal panel has a gate bus line 12A and a drain bus line 17 as shown in FIG.
A and A are orthogonally arranged in a matrix. Although the pixel electrode 19 is formed at each of these intersections as in the conventional case, the gate bus line is arranged at the end of the pixel electrode in the related art, whereas in the present embodiment, the pixel electrode 18 is formed. The gate bus line 12A is arranged so as to cross the center of the gate bus line 12A, and a point that a part of the gate bus line 12A serves as the gate electrode 12 is different.

Further, auxiliary capacitance bus lines 19A, 19B
Conventionally, it was arranged so as to cross the center of the pixel electrode, but in the present embodiment, it is arranged so as to cross both ends of the pixel electrode 18, and two auxiliary capacitance bus lines 19A and 19B are formed for one pixel. This is different from conventional methods. Further, the pixel electrode 18 has a thin central portion,
TFT for driving pixels in the area where this is not formed
Has been arranged.

One drain electrode 17 is arranged so as to project from the drain bus line 17A toward the gate electrode 12, and the gate electrode 12 and the drain electrode 17 are arranged so as to overlap each other. In addition, the two source electrodes 16
A and 16B are arranged so as to sandwich the gate electrode 12, and each of them is connected to the pixel electrode 18, whereby two Ts having a common gate and drain for one pixel are provided.
The FT has been formed.

Next, the sectional structure of this device is shown in FIG.
This will be described with reference to FIG. A gate electrode 12 is formed on a transparent substrate 11 made of glass or the like, and a gate insulating film 13 is formed so as to cover it. An operating semiconductor layer 14 made of amorphous silicon, which constitutes the channel layer of the TFT, is formed thereon. Insulating channel protection films 15A and 15B are formed at regular intervals in a region where a channel is formed on the operating semiconductor layer 14, and a drain electrode 17 is formed between them.

Further, source electrodes 16A and 16B are formed on both sides of the channel protective films 15A and 15B.
Configure two TFTs. This source electrode 16A, 16B
A pixel electrode 18 made of an ITO (Indium TiN Oxide) film is formed on the top. A transparent substrate (not shown) having a counter electrode made of a transparent conductive film formed on the surface of the above-mentioned substrate is disposed so as to face it, and liquid crystal LC is sealed between these substrates to form a TFT liquid crystal panel.

Next, an equivalent circuit for one pixel of the above TFT liquid crystal panel will be described. FIG. 2 (b)
FIG. 3 is an equivalent circuit diagram of the TFT liquid crystal panel for one pixel. As shown in FIG. 2B, the two TFTs Q1 and Q
2 are connected in parallel, and the pixel electrode is connected to the source thereof. Incidentally, Q1 is a TFT composed of the gate electrode 12, drain electrode 17 and source electrode 16A in the same figure (a), and Q2 is a gate electrode 12, drain electrode 17 and source electrode 16B in the same figure (a).
It is a TFT composed of.

In FIG. 2B, CL is a capacitance of the liquid crystal of the pixel, Cs1 is an auxiliary capacitance related to the auxiliary capacitance bus line 19A, and Cs2 is an auxiliary capacitance related to the auxiliary capacitance bus line 19B. Furthermore, Cgs1 is TFTQ
Cg between the source electrode 16A of 1 and the gate electrode 12
s2 is a capacitance between the source electrode 16B and the gate electrode 12, and the size of these is dependent on the overlapping area of the gate electrode 12 and the source electrodes 16A and 16B in FIG.

Further, unlike the prior art, as shown in FIG. 1, since the gate electrode 12 and the pixel electrode 18 overlap each other, a capacitance is also generated between them, which is shown in FIG.
In (b), it is Cgg. In the conventional structure of the TFT liquid crystal panel, the above-mentioned Cgs1 and Cgs2 change due to the positional deviation of the reticle corresponding to each region of the divided exposure, and the brightness difference between the Cgs1 and Cgs2 causes a difference in brightness between the regions. The display unevenness is caused as described with reference to FIGS. 10 and 11. However, in the TFT liquid crystal panel according to the present embodiment, this Cgs1 + C
Since the structure is such that gs2 is kept constant, it is possible to suppress the occurrence of a brightness difference.

Details of this action and effect will be described with reference to FIG. FIG. 3 is a partially enlarged view illustrating the positional relationship near the gate electrode 12 and the source electrodes 16A and 16B. In FIG. 3, 16A 'and 16B' show patterns when the source electrodes 16A and 16B are properly aligned, and 16A and 16B are slightly displaced in the X and Y directions due to the displacement of the reticle. The pattern is shown. Further, S1 and S2 are the source electrodes 16
The overlapping areas of A and 16B and the gate electrode 12 are shown.

As shown in FIG. 3, in this embodiment, the drain electrodes 16A and 16B are arranged to face each other with the gate electrode 12 interposed therebetween. Although the overlapping areas S1 and S2 of the source electrodes 16A and 16B and the gate electrode 12 change due to the position of the reticle shifting in the X and Y directions, even if S2 decreases as shown in FIG. Since S1 is increasing, the total area is always constant no matter how the positional deviation occurs.

When the total sum of these areas becomes constant, the total sum Cgs1 + Cgs2 of the capacitances between the source electrodes 16A and 16B and the gate electrode 12 is also kept constant. Actually, the sum of these capacitances Cgs1 + Cgs2 affects the voltage applied between the gate and the source, so the sum of capacitances Cgs
If 1 + Cgs2 is constant, the voltage applied between the gate and the source is also kept constant.

Therefore, even if the reticle is misaligned in each area of the divided exposure and the variations occur, the gate-
Since the voltage applied between the sources is kept constant in all regions, it is possible to suppress the occurrence of display unevenness due to a difference in luminance between these regions and display unevenness as much as possible. Furthermore, as shown in FIG.
Similarly, the sum of the areas of the regions where A and 19B and the pixel electrode overlap becomes constant, and the auxiliary capacitors Cs1 and Cs shown in FIG.
Since the sum of s2 is constant, it is possible to prevent the display unevenness caused by the variation of the auxiliary capacitance in each divided area.

Further, in the present embodiment, as shown in FIG. 1, the width of the pixel electrode 18 is narrowed at the overlapping portion of the gate bus line 12 and the pixel electrode 18, and the overlapping area thereof is reduced. The capacitance Cgg generated during the period becomes small, and even if the capacitance Cgg varies from region to region due to displacement, display unevenness can be suppressed to such an extent that its influence is hardly visible.

A method of manufacturing the above TFT liquid crystal panel will be briefly described below with reference to FIGS. First, as shown in FIG. 4A, the transparent substrate 11 made of glass is used.
A metal film such as a chrome film is vapor-deposited on the gate electrode 12 and then patterned to form the gate electrode 12 and the auxiliary capacitance bus lines 19A, 1
9B is selectively formed at the same time, and a gate insulating film 13 made of an oxide film is formed thereon.

Next, as shown in FIG. 3B, after an amorphous silicon layer 14 and an oxide film are sequentially formed on the entire surface,
The oxide film is patterned by a conventional method, and the channel protection films 15A and 15B are selectively formed on the gate electrode 12 at regular intervals. Next, as shown in FIG. 3C, a metal layer 16 of molybdenum or the like is formed on the entire surface, photoresist is applied, and patterning is performed by photolithography to select the resist film PR on the formation region of the gate electrode 12. After the formation, the metal layer 16 and the amorphous silicon layer 14 are etched and removed by using this as a mask to form the operating semiconductor layer 14 as shown in FIG. 5A.

Next, as shown in FIG. 7B, the entire surface is I
The TO film 20 is formed by a sputtering method or the like, a resist film PR is selectively formed by a photolithography method, and the ITO film 20 and the metal layer 16 are etched and removed using the resist film PR as a mask.
After that, a counter substrate having a counter electrode made of an ITO film formed on the surface is disposed so as to face the substrate formed through the above-described steps, and the liquid crystal layer LC is sealed between them, so that the structure shown in FIG. It is possible to form a TFT liquid crystal panel whose cross section is shown in FIG.

(2) Second Embodiment A second embodiment of the present invention will be described below with reference to FIGS. 6 and 7. Descriptions of matters common to the first embodiment will be omitted to avoid duplication. FIG. 6 is a top view for explaining the structure around the pixel of the TFT liquid crystal panel of the present invention. 7A is a sectional view taken along line XX of FIG. 6, and FIG. 7B is an equivalent circuit diagram of FIG.

This embodiment is different from the first embodiment in that, as shown in FIG. 6, the pixel electrode 28 corresponding to one pixel is used.
A and 28B are divided at the portion overlapping the gate electrode 22,
It is the same as the first embodiment except that it does not overlap the gate electrode 22 at all. 6 and 7A, 21 is a transparent substrate, 22 is a gate electrode, 23 is a gate insulating film, 24 is an operating semiconductor layer made of amorphous silicon, 25 is a channel protective film, 26
Is a source electrode, 27 is a drain electrode, and 28 is a pixel electrode. 29A and 29B are auxiliary capacitance bus lines.

The structure of this TFT panel will be described below. First, the positional relationship between the respective parts of the TFT liquid crystal panel as viewed from above will be described with reference to FIG. As shown in FIG. 6, the gate bus lines 22A and the drain bus lines 27A are orthogonally arranged in a matrix. As in the first embodiment, the pixel electrodes 29A and 29B are formed at these intersections, respectively.
The pixel electrodes 28A and 28B corresponding to the pixels are divided, and the first point is that they do not overlap with the gate electrode 22.
Is different from the embodiment. The other arrangement relationships are the same as those in the first embodiment, and thus the description thereof will be omitted.

Next, the sectional structure of this device is shown in FIG.
This will be described with reference to FIG. A gate electrode 22 is formed on a transparent substrate 21 made of glass or the like, and a gate insulating film 23 is formed so as to cover it. An operating semiconductor layer 24, which constitutes the channel layer of the TFT and is made of amorphous silicon, is formed thereon. Insulating channel protective films 25A and 25B are formed at regular intervals in a region where a channel is formed on the operating semiconductor layer 24, and a drain electrode 27 is formed between them.

Further, source electrodes 26A and 26B are formed on both sides of the channel protective films 25A and 25B.
Configure two TFTs. The source electrodes 26A and 26B
Pixel electrodes 28A and 28B each made of an ITO (Indium TiN Oxide) film are formed on the top. FIG. 7 (b)
FIG. 3 is an equivalent circuit diagram for one pixel of the TFT liquid crystal panel of this embodiment. As shown in FIG. 7B, two TFTs Q1 and Q2 are connected in parallel, and a pixel is connected to the source thereof. Note that Q1 is a TFT composed of the gate electrode 22, the drain electrode 27, and the source electrode 26A in FIG. 4A, and Q2 is Q2 in FIG.
Of the gate electrode 22, the drain electrode 27, and the source electrode 26B.

In FIG. 7B, CL is a capacitance of the liquid crystal of the pixel, Cs1 is an auxiliary capacitance related to the auxiliary capacitance bus line 29A, and Cs2 is an auxiliary capacitance related to the auxiliary capacitance bus line 29B. Furthermore, Cgs1 is TFTQ
Capacitance between the source electrode 26A and the gate electrode 22 of No. 1, Cg
s2 is a capacitance between the source electrode 26B and the gate electrode 22.

Further, unlike the first embodiment, the gate electrode 22 and the pixel electrodes 28A and 28B do not overlap each other as shown in FIG. 6, so that they occur between them in the first embodiment. The capacity Cgg is 0 in this embodiment. Therefore, since the capacitance Cgg does not change for each exposure area due to the positional deviation, it is possible to suppress display unevenness that may occur due to the variation of the capacitance Cgg.

The manufacturing method of the TFT panel is the same as that of the first embodiment except that the patterning process of the pixel electrodes 29A and 29B is different from that of the first embodiment. Is omitted.

[0047]

As described above, according to the present invention,
A drain electrode protruding from the drain bus line so as to overlap with a gate electrode formed of a part of the gate bus line; first and second source electrodes arranged to face each other with the gate electrode interposed therebetween; Since it has a pixel electrode connected to the source electrode of each of the exposure regions, the displacement between the reticle corresponding to each region of the divided exposure as in the conventional art causes the capacitance between the gate electrode and the source electrode to change and each exposure region to be exposed. The voltage applied between the gate and the source is kept constant over the entire exposure area even if it varies from one area to another, so that there is a difference in brightness between these areas, which is visually recognized and display unevenness occurs. It becomes possible to suppress as much as possible.

In the present invention, the area of the pixel electrode may be reduced in the region intersecting with the gate bus line.
In this case, since the area where the gate bus line and the pixel electrode intersect becomes small and the capacitance generated between them is reduced, variations in the applied voltage that occur between the divided exposure regions when the same voltage is applied are reduced. It can be reduced. Further, the pixel electrode may be divided in a region intersecting with the gate bus line. In this case, no capacitance is generated between the area where the gate bus line and the pixel electrode intersect with each other at 0. Therefore, when the same voltage is applied, variations in the applied voltage that occur between the divided exposure regions are caused. It becomes possible to deter.

[Brief description of the drawings]

FIG. 1 is a top view illustrating a liquid crystal display panel according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view and an equivalent circuit diagram illustrating a liquid crystal display panel according to a first embodiment of the present invention.

FIG. 3 is a top view illustrating a function and effect of the liquid crystal display panel according to the first embodiment of the present invention.

FIG. 4 is a first cross-sectional view explaining the method of manufacturing the liquid crystal display panel according to the first and second embodiments of the present invention.

FIG. 5 is a second cross-sectional view explaining the method of manufacturing the liquid crystal display panel according to the first and second embodiments of the present invention.

FIG. 6 is a top view illustrating a liquid crystal display panel according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view and an equivalent circuit diagram illustrating a liquid crystal display panel according to a second embodiment of the present invention.

FIG. 8 is a top view and a cross-sectional view illustrating a liquid crystal display panel according to a conventional example.

FIG. 9 is an equivalent circuit diagram of a conventional liquid crystal display panel.

FIG. 10 is a diagram illustrating a method of divided exposure.

FIG. 11 is a diagram illustrating a conventional problem.

[Explanation of symbols]

Reference Signs List 11 transparent substrate (first transparent substrate) 12 gate bus line 13 gate insulating film 14 operating semiconductor layers 15A, 15B channel protective film 16 metal layer 16A first source electrode 16B second source electrode 17 drain electrode 18 pixel electrode LC Liquid crystal layer CL Capacitance of liquid crystal Cs1, Cs2 Auxiliary capacitance Cgs1 Capacitance between first source electrode and gate electrode Cgs2 Capacitance between first source electrode and gate electrode Q1, Q2 TFT (thin film transistor)

Claims (4)

[Claims] 1. A plurality of gate bus lines and drain bus lines are arranged in a matrix on a transparent insulating substrate via an interlayer insulating film, and a driving thin film transistor is provided in the vicinity of an intersection of the gate bus lines and the drain bus lines. And a liquid crystal layer is sandwiched between a first transparent substrate having a pixel electrode connected to the source electrode of the thin film transistor and a second transparent substrate having at least a counter electrode formed on a transparent insulating substrate. A liquid crystal display panel comprising: a gate electrode of the thin film transistor, which is a part of the gate bus line; and a drain electrode of the thin film transistor, which is arranged to project from the drain bus line so as to overlap with the gate electrode, A first source electrode and a second source electrode of the thin film transistor, which are opposed to each other with the gate electrode interposed therebetween. A liquid crystal display panel characterized by: 2. The gate bus line is arranged so as to cross the center of the pixel electrode, and auxiliary capacitance bus lines are arranged at both ends of the pixel electrode in parallel with the gate bus line. The liquid crystal display panel according to claim 1. 3. The liquid crystal display panel according to claim 1, wherein the area of the pixel electrode is small in a region intersecting with the gate bus line. 4. The pixel electrode is divided in a region intersecting with the gate bus line.
The liquid crystal display panel according to claim 2.