KR100462370B1 - Flash memory device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same; a field insulating film defining an active region on a first conductive semiconductor substrate, an erase gate formed to be embedded in a groove formed in the field insulating film, and a predetermined portion on the semiconductor substrate. A floating gate formed by interposing a gate oxide film in a portion thereof and overlapping the erase gate with a tunneling oxide film interposed therebetween, and a control gate elongated in the direction of a channel so as to overlap the floating gate by interposing an interlayer dielectric film on the semiconductor substrate. And a source and drain region of a second conductivity type formed on both sides of the control gate of the semiconductor substrate. Therefore, since the overlapping area of the floating gate and the erase gate is increased without increasing the cell area, the erase efficiency can be improved. In addition, since the gate is formed in the field insulating film and then the erase gate is formed in the groove, the process is simple.

Description

Flash memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a flash memory device and a method of manufacturing the same, which can easily erase programmed data, and can reduce cell area and simplify processing.

A flash memory device is a nonvolatile memory device having a high erase speed because it can erase data stored in memory array cells at the same time.

The flash memory device has at least a two-layer gate structure of a floating gate and a control gate, and hot-electron generated in a channel near the drain region by a power supply voltage Vdd applied to the drain region. ) Is injected into the floating gate by the high voltage applied to the control gate and accumulated.

The flash memory device also uses an ETOX (EEPROM Tunneling Oxide) structure that erases programmed data by Fowler-Nordheim tunneling (hereinafter referred to as FN tunneling) to the source region of electrons accumulated in the floating gate, and a separate erase gate. And a split gate structure that erases electrons accumulated in the floating gate through an erase gate. That is, the flash memory device having the ETOX structure is a floating gate by a high electric field between the source region and the floating gate formed by applying a high voltage of about 12V to the source region while grounding the semiconductor substrate and the control gate and floating the drain region. The electrons charged in the tunnel are tunneled into the source region to erase the data. In addition, the flash memory device having the isolation gate structure erases data by tunneling electrons charged in the floating gate formed by applying a high voltage of about 12V to the erase gate instead of the source region.

1 is a cross-sectional view of a flash memory device having a conventional ETOX structure. In FIG. 1, the region L1 is a region in which the flash memory device is cut in the length direction of the channel, and the region W1 is a region in the width direction of the channel.

In a flash memory device having a conventional ETOX structure, a field insulating film 13 defining an active region of a device is formed on a P-type semiconductor substrate 11. A thin gate oxide film 15 used as a tunneling oxide film is formed in a predetermined portion of the active region of the device on the semiconductor substrate 11, and a floating gate 17 is formed on the gate oxide film 15. In addition, an interlayer dielectric film 19 having a structure of silicon oxide / silicon nitride / silicon oxide (hereinafter referred to as ONO) is formed on the field insulating film 13 and the floating gate 17. The control gate 21 is formed long on the dielectric layer 19 in the width direction perpendicular to the length direction of the channel.

Source and drain regions 25 and 27 doped with N-type impurities at high concentration are formed on both sides of the control gate 21 of the active region of the device of the semiconductor substrate 11. The low concentration region 23 surrounding the source region 25 is formed in the semiconductor substrate 11. The low concentration region 23 is formed so as to surround the source region 25 to prevent the junction from being broken by the high voltage applied to the source region 25.

The flash memory device having the above-described ETOX structure has a structure in which the floating gate and the control gate are overlapped, so that the structure is simple and the cell size is small.

However, the flash memory device having the ETOX structure has a problem in that the breakdown voltage characteristic is degraded because the gate oxide film is thinly formed in order to facilitate F-N tunneling of electrons during erasing.

Therefore, a flash memory device having a separate gate structure capable of forming a thick gate oxide layer by erasing by using an erase gate and having improved breakdown voltage characteristics during erasing can improve device reliability.

2 is a cross-sectional view of a flash memory device having a conventional isolation gate structure. In FIG. 2, the region L2 is a region in which the flash memory device is cut in the length direction of the channel, and the region W2 is a region in the width direction of the channel.

In a conventional flash memory device having a split gate structure, a field insulating film 33 is formed on a P-type semiconductor substrate 31 to define an active region of a device. The gate oxide film 39 is formed in a predetermined portion of the active region of the element on the semiconductor substrate 31, and the floating gate 41 is formed on the gate oxide film 39.

The control gate 45 is formed so that one side thereof overlaps with the floating gate 41 through the interlayer dielectric film 43 having the ONO structure in the active region of the device on the semiconductor substrate 31. From above

Although not shown, the control gate 45 is formed to be elongated in the width direction perpendicular to the longitudinal direction of the channel, and the control gate 45 is provided with a groove 53 by removing a predetermined portion between the floating gates 41. do. An erase gate 55 is formed in the groove 53, and the erase gate 55 is formed on the side of the floating gate 41 to electrically insulate the erase gate 55 from the floating gate 41 and the control gate 45. The tunneling oxide film 51 is formed, and a cap layer 47 and sidewalls 49 are formed on the top and side surfaces of the control gate 45.

Source and drain regions 35 and 37 doped with a high concentration of N-type impurities are formed in the semiconductor substrate 31. In this case, the source region 35 overlaps with the other side of the control gate 45 by a predetermined portion, and the drain region 37 is formed so as to overlap with a side of the floating gate 41 by a predetermined portion.

The flash memory device having the above-described isolation gate structure erases electrons accumulated in the floating gate by F-N tunneling to the erase gate through the tunneling oxide film, thereby improving the breakdown voltage characteristics of the gate oxide film, thereby improving reliability of the device.

However, in the above-described flash memory device having the isolation gate structure, since the erase gate is to be formed, not only the cell area is increased but also the overlapping area with the floating gate is small, thereby reducing the erase efficiency. In addition, since the groove for forming the erase gate is formed by etching the cap layer, the control gate and the interlayer dielectric layer, there is a problem that a long process time is required.

Accordingly, an object of the present invention is to provide a flash memory device capable of improving the erase efficiency by increasing the area overlapping with the floating gate without increasing the cell area.

Another object of the present invention is to provide a method of manufacturing a flash memory device which can reduce a process time by forming a groove and an erase gate in a field insulating film.

A flash memory device according to the present invention for achieving the above object comprises a field insulating film defining an active region on a first conductive semiconductor substrate, an erase gate formed to be buried in a groove formed in the field insulating film, and on the semiconductor substrate. A control gate formed in a predetermined portion through a gate oxide film and overlapping the erase gate with a tunneling oxide film interposed therebetween, and a control formed long in the direction of a channel so as to overlap the floating gate by interposing an interlayer dielectric film on the semiconductor substrate; A gate and a source and drain region of a second conductivity type formed on both sides of the control gate of the semiconductor substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method including forming a field insulating film defining an active region on a first conductive semiconductor substrate, forming a groove in the field insulating film, Forming an erase gate in the semiconductor substrate; forming a gate oxide film on the semiconductor substrate; forming a tunneling oxide film on the erase gate; and forming a gate oxide film on the semiconductor substrate; and a first polysilicon layer overlapping the erase gate on the gate oxide film and the tunneling oxide film. Forming an interlayer dielectric film on the exposed portion of the semiconductor substrate and the field insulating film so as to cover the first polysilicon layer on the exposed portion of the semiconductor substrate and forming a second polysilicon layer on the interlayer dielectric film; Forming a photoresist on the second polysilicon layer in the width direction of the channel; And forming a control gate and a floating gate by sequentially patterning the second polysilicon layer, the interlayer dielectric layer, the first polysilicon layer, and the gate oxide layer using the photoresist as a mask, and the control gate as a mask. And forming a source and drain region of a second conductivity type in the semiconductor substrate.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view of a flash memory device according to the present invention. In FIG. 3, the region L3 is a region in which the flash memory device is cut in the length direction of the channel, and the region W3 is a region in the width direction of the channel.

In the flash memory device according to the present invention, a field insulating film 63 defining an active region of an element is formed on a P-type semiconductor substrate 61. The field insulating layer 63 is formed by a local oxide of silicon (LOCOS) method or a shallow trench isolation (STI) method.

An erase gate 67 made of polysilicon is formed in the groove 65 formed in a predetermined portion of the field insulating layer 63. The gate oxide film 69 is formed in a predetermined portion of the active region of the device on the semiconductor substrate 61, and the floating gate 79 is formed on the gate oxide film 69. In the above, the floating gate 79 is formed to overlap a predetermined portion via the erase gate 67 and the tunneling oxide film 71. Since the erase gate 67 is buried in the field insulating layer 63, the contact area with the floating gate 79 can be increased without increasing a separate area.

In addition, an interlayer dielectric film 75 having an ONO structure is formed on the floating gate 79 to cover the tunneling oxide film 71. The control gate 81 is perpendicular to the longitudinal direction of the channel on the interlayer dielectric film 75. It is formed long in the width direction.

Source and drain regions 83 and 85 doped with N-type impurities at high concentration are formed on both sides of the control gate 81 of the active region of the device of the semiconductor substrate 61.

In the flash memory device having the above-described structure, when the semiconductor substrate 61 and the source region 83 are grounded, when a voltage of about 5V is applied to the drain region 85 and a high voltage of about 12V is applied to the control gate 81, the drain is drained. Hot electrons are generated in the vicinity of the region 85, and the data is programmed by injecting the hot electrons into the floating gate 79 by a high voltage applied to the control gate 81.

Then, the semiconductor substrate 61 and the control gate 81 are grounded and the drain region 85 is floated, and a high voltage of about 12 V is applied to the erase gate 67 so that electrons are transferred through the tunneling gate 71. The FN tunnels to the erase gate 67 at 79 to erase the programmed data.

Since the electrons are tunneled and erased from the floating gate 79 to the erasing gate 67 through the tunneling gate 71, the low concentration region surrounding the source region 83 is not necessary, and the erasing gate 67 is a field. Since the insulating layer 63 is buried, the contact area with the floating gate 79 can be increased without increasing a separate area, thereby increasing the erase efficiency.

4A to 4D are manufacturing process diagrams of a flash memory device according to the present invention.

Referring to FIG. 4A, a field insulating film 63 defining an active region of an element is formed on a P-type semiconductor substrate 61 by the LOCOS method or the STI method. The groove 65 is formed by etching a predetermined portion on the field insulating layer 63 to a predetermined depth by a photolithography method.

Polysilicon is deposited on the entire surface of the structure described above to fill the grooves 65. Then, the polysilicon is etched back by using a reactive ion etching method (RIE) so as to expose the semiconductor substrate 61 and the field insulating layer 63. 67). Since the groove 65 is formed in the field insulating film 63 and the polysilicon is filled in the groove 65 to form the erase gate 67, the process is simple.

Referring to FIG. 4B, the gate oxide film 69 is formed on the exposed portion of the semiconductor substrate 61 by a thermal oxidation method. At this time, the exposed portion of the erase gate 67 is also oxidized to form the tunneling oxide film 71.

The first polycrystalline silicon layer 73 is formed on the gate oxide film 69 and the tunneling oxide film 71 by chemical vapor deposition (hereinafter, referred to as CVD) to cover the field insulating film 63. Then, the first polysilicon layer 73 is patterned to expose the semiconductor substrate 61 by a photolithography method so as to be formed long in the longitudinal direction of the channel. At this time, the first polysilicon layer 73 is separated in the width direction perpendicular to the longitudinal direction of the channel, so that the large area and the erase gate 67 overlap.

Referring to FIG. 4C, an interlayer dielectric film 75 having an ONO structure is formed on the exposed portion of the semiconductor substrate 61 and the field insulating film 63 to cover the first polysilicon layer 73.

The second polysilicon layer 77 is formed on the interlayer dielectric film 75 by the CVD method.

Referring to FIG. 4D, a photoresist (not shown) is applied on the second polysilicon layer 77 and then patterned in the width direction of the channel by exposure and development.

Using the photoresist as a mask, the second polysilicon layer 77, the interlayer insulating film 75, the first polysilicon layer 73, and the gate oxide film 69 are sequentially patterned to expose the semiconductor substrate 61. At this time, the first and second polysilicon layers 73 and 77 remaining without being removed become the floating gate 79 and the control gate 81. Since the first polysilicon layer 73 is not patterned in the width direction of the channel, the floating gate 79 overlaps the erase gate 67 with a large area.

Remove the photoresist. Then, by using the control gate 81 as a mask, an ion-implanted N-type impurity such as phosphorus (P) or arsenic (As) is injected into the exposed portion of the semiconductor substrate 61 with a high dose to obtain a high concentration of source and Drain regions 83 and 85 are formed.

As described above, in the flash memory device according to the present invention, an erase gate is embedded in a groove formed in the field insulating layer, and the floating gate is formed so that a large area overlaps with the erase gate through a tunneling oxide film.

Therefore, the present invention increases the overlapping area of the floating gate and the erase gate without increasing the cell area, thereby improving the erase efficiency. In addition, since the gate is formed in the field insulating film and then the erase gate is formed in the groove, the process has a simple advantage.

1 is a cross-sectional view of a flash memory device having a conventional ETOX structure.

2 is a cross-sectional view of a flash memory device having a conventional isolation gate structure.

3 is a cross-sectional view of a flash memory device according to the present invention.

4A to 4D are manufacturing process diagrams of a flash memory device according to the present invention.

Claims (5)

A field insulating film defining an active region on the first conductive semiconductor substrate; An erase gate formed in the groove formed in the field insulating film; A gate insulating film and a tunneling oxide film formed on a predetermined portion of the semiconductor substrate having the erase gate and formed by oxidizing the erase gate; A floating gate formed to partially overlap the erase gate on the erase gate; A control gate formed long in the direction of the channel so as to overlap the floating gate by interposing an interlayer dielectric film on the semiconductor substrate; And a source and drain region of a second conductivity type formed on both sides of the control gate of the semiconductor substrate. The flash memory device of claim 1, wherein the erase gate is formed of polycrystalline silicon. The flash memory device of claim 2, wherein the tunneling oxide layer is formed by oxidizing a surface of the erase gate. Forming a field insulating film defining an active region on the first conductive semiconductor substrate; Forming a groove in the field insulating film and an erase gate in the groove; Forming a tunneling oxide film by oxidizing a surface of the erase gate while forming a gate insulating film on the substrate including the erase gate; Forming a first polysilicon layer on the tunneling oxide layer in the channel direction of the device so as to partially overlap the erase gate on the erase gate; Forming an interlayer dielectric film on the exposed portion of the semiconductor substrate and the field insulating film to cover the first polycrystalline silicon layer and forming a second polysilicon layer on the interlayer dielectric film; Forming a photoresist on the second polysilicon layer in the width direction of the channel and patterning the second polysilicon layer, the interlayer insulating film, the first polysilicon layer, and the gate oxide film sequentially using the photoresist as a mask. Forming a control gate and a floating gate, And forming a source and drain region of a second conductivity type on the semiconductor substrate using the control gate as a mask. The method of claim 4, wherein the erase gate is formed by depositing polysilicon on the semiconductor substrate so as to fill the groove, and then etching back the semiconductor substrate to expose the semiconductor substrate.