KR100406582B1 - method for forming conductive plug - Google Patents
method for forming conductive plug Download PDFInfo
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- KR100406582B1 KR100406582B1 KR10-2001-0082676A KR20010082676A KR100406582B1 KR 100406582 B1 KR100406582 B1 KR 100406582B1 KR 20010082676 A KR20010082676 A KR 20010082676A KR 100406582 B1 KR100406582 B1 KR 100406582B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 도전 플러그(conductive plug) 간의 접촉면적을 증가시킬 수 있는 도전 플러그 형성 방법에 관해 개시한다.The present invention discloses a method for forming a conductive plug that can increase the contact area between conductive plugs.
개시된 본 발명의 도전 플러그 형성 방법은 반도체 기판 상에 제 1산화막, 질화막 및 제 2산화막을 차례로 형성하는 단계와, 제 2산화막, 질화막 및 제 1산화막을 식각하여 기판의 일부를 노출시키는 제 1콘택홀을 형성하는 단계와, 제 1콘택홀을 포함한 제 2산화막 상에 제 1도전막을 형성하는 단계와, 제 2산화막을 연마 멈춤막으로 이용하고, 제 1도전막을 연마하여 제 1콘택홀을 채우며, 제 2산화막 표면으로 상단 부분이 일부 돌출된 형상을 가진 제 1도전 플러그를 형성하는 단계와,결과물 상에 제 3산화막을 형성하는 단계와, 제 3산화막을 식각하여 돌출된 제 1도전 플러그의 상단 및 측면 일부를 노출시키는 제 2콘택홀을 형성하는 단계와, 제 2콘택홀을 채워 제 1도전 플러그와 연결되는 제 2도전 플러그를 형성하는 단계를 포함한다.The disclosed method for forming a conductive plug includes sequentially forming a first oxide film, a nitride film, and a second oxide film on a semiconductor substrate, and etching the second oxide film, the nitride film, and the first oxide film to expose a portion of the substrate. Forming a hole, forming a first conductive film on the second oxide film including the first contact hole, using the second oxide film as a polishing stop film, and polishing the first conductive film to fill the first contact hole. Forming a first conductive plug having a shape in which the upper portion is partially protruded from the surface of the second oxide film, forming a third oxide film on the resultant, and etching the third oxide film to protrude the first conductive plug. Forming a second contact hole exposing a portion of the top and side surfaces, and forming a second conductive plug connected to the first conductive plug by filling the second contact hole.
Description
본 발명은 반도체장치의 형성 방법에 관한 것으로, 보다 상세하게는 도전 플러그(conductive plug) 간의 접촉면적을 증가시킬 수 있는 도전 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a conductive plug capable of increasing a contact area between conductive plugs.
일반적으로 알려진 바와 같이, 칩사이즈가 축소됨에 따라 콘택홀 크기가 축되고, 따라서 콘택홀을 채우는 도전 플러그의 접촉 면적 또한 축소되는 추세이다.As is generally known, as the chip size is reduced, the contact hole size is reduced, so that the contact area of the conductive plug filling the contact hole is also reduced.
도 1a 내지 도 1e는 종래 기술에 따른 도전 플러그 형성 방법을 보인 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a conductive plug according to the related art.
종래 기술에 따른 도전 플러그 형성 방법은, 도 1a에 도시된 바와 같이, 먼저 반도체기판(100) 상에 화학기상증착(Chemical Vapor Deposition)공정에 의해 제 1산화막(102) 및 질화막(104)을 차례로 형성한다. 이때, 상기 제 1산화막(102)은 6000∼8000Å 두께로 형성하고, 상기 질화막(104)은 1500∼2500Å 두께로 형성한다.In the method of forming a conductive plug according to the related art, as shown in FIG. 1A, first, the first oxide film 102 and the nitride film 104 are sequentially ordered on a semiconductor substrate 100 by a chemical vapor deposition process. Form. In this case, the first oxide film 102 is formed to a thickness of 6000 ~ 8000 Å, the nitride film 104 is formed to a thickness of 1500 ~ 2500 Å.
이어서, 상기 질화막(104) 상에 감광막을 도포하고 노광 및 현상하여 제 1콘택홀 형성영역이 정의된 제 1감광막 패턴(120)을 형성한다.Subsequently, a photoresist film is coated on the nitride film 104, exposed to light, and developed to form a first photoresist film pattern 120 having a first contact hole formation region defined therein.
그 다음, 도 1b에 도시된 바와 같이, 상기 제 1감광막 패턴(120)을 마스크로 하고 상기 질화막 및 제 1산화막을 제거하여 제 1콘택홀(103)을 형성한다. 이후, 상기 제 1감광막 패턴을 제거하고 나서, 상기 콘택홀(103)을 포함한 질화막(104) 상에 스퍼터링(sputtering) 방식으로 제 1금속막을 증착하고 나서, 상기 제 1금속막에 화학적-기계적 연마(Chemical Mechanical Polishing) 공정을 진행하여 제 1도전 플러그(110)를 형성한다.Next, as shown in FIG. 1B, the first photoresist layer pattern 120 is used as a mask to form the first contact hole 103 by removing the nitride layer and the first oxide layer. Thereafter, the first photoresist layer pattern is removed, a first metal layer is deposited on the nitride layer 104 including the contact hole 103 by a sputtering method, and then chemical-mechanical polishing is performed on the first metal layer. (Chemical Mechanical Polishing) process to form a first conductive plug 110.
이어서, 도 1c에 도시된 바와 같이, 상기 결과물 상에 제 2산화막(112)을 화학기상증착한 다음, 상기 제 2산화막(112) 상에 적어도 상기 제 1도전 플러그(110)와 대응된 일부분을 노출시키는 제 2감광막 패턴(122)을 형성한다. 이때, 상기 제 2산화막(112)은 3500∼4500Å 두께로 형성한다.Subsequently, as illustrated in FIG. 1C, a chemical vapor deposition of the second oxide film 112 on the resultant is performed, and then at least a portion corresponding to the first conductive plug 110 is deposited on the second oxide film 112. A second photoresist pattern 122 is formed to be exposed. At this time, the second oxide film 112 is formed to have a thickness of 3500 ~ 4500Å.
그 다음, 도 1d에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하고상기 제 2산화막을 식각하여 제 2콘택홀(113)을 형성한다. 이때, 상기 잔류된 질화막(104)은 상기 제 2콘택홀 형성을 위한 식각 공정 진행 시 식각정지막으로서의 역할을 한다.Next, as shown in FIG. 1D, the second photoresist pattern is used as a mask, and the second oxide layer is etched to form a second contact hole 113. In this case, the remaining nitride film 104 serves as an etch stop film during the etching process for forming the second contact hole.
이 후, 제 2감광막 패턴을 제거한다. 그 다음, 도 1e에 도시된 바와 같이, 상기 제 2콘택홀(113)을 포함한 제 2산화막(112) 상에 제 2금속막을 증착하고 나서, 상기 제 2금속막을 화학적-기계적 연마하여 상기 제 1도전 플러그(110)와 연결되는 제 2도전 플러그(130)를 형성한다.Thereafter, the second photosensitive film pattern is removed. Next, as illustrated in FIG. 1E, a second metal film is deposited on the second oxide film 112 including the second contact hole 113, and then the first metal film is chemically mechanically polished to form the first metal film. A second conductive plug 130 connected to the conductive plug 110 is formed.
그러나, 종래의 기술에서는 반도체 칩이 고집적화됨에 따라, 제 1도전 플러그와 제 2도전 플러그 간의 접촉 면적이 작아지는 문제점이 있었다.However, in the related art, as the semiconductor chip is highly integrated, there is a problem in that the contact area between the first conductive plug and the second conductive plug is reduced.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 제 1도전 플러그 및 상기 제 1도전 플러그와 연결되는 제 2도전 플러그 간의 접촉면적을 증가시킬 수 있는 도전 플러그 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and provides a method for forming a conductive plug that can increase the contact area between the first conductive plug and the second conductive plug connected to the first conductive plug. There is this.
도 1a 내지 도 1e는 종래 기술에 따른 도전 플러그 형성 방법을 보인 공정단면도.1A to 1E are cross-sectional views illustrating a method of forming a conductive plug according to the related art.
도 2a 내지 도 2e는 본 발명에 따른 도전 플러그 형성 방법을 보인 공정단면도.2A to 2E are cross-sectional views illustrating a method of forming a conductive plug according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
200. 반도체기판 202, 206, 212. 산화막200. Semiconductor substrates 202, 206, and 212 oxide film
204. 질화막 203, 213. 콘택홀204. Nitride layers 203 and 213. Contact holes
210, 230. 도전 플러그 220, 222. 감광막 패턴210, 230. Conductive plugs 220, 222. Photosensitive film pattern
상기 목적을 달성하기 위한 본 발명의 도전 플러그 형성 방법은 반도체 기판 상에 제 1산화막, 질화막 및 제 2산화막을 차례로 형성하는 단계와, 제 2산화막, 질화막 및 제 1산화막을 식각하여 기판의 일부를 노출시키는 제 1콘택홀을 형성하는 단계와, 제 1콘택홀을 포함한 제 2산화막 상에 제 1도전막을 형성하는 단계와, 제 2산화막을 연마 멈춤막으로 이용하고, 제 1도전막을 연마하여 제 1콘택홀을 채우며, 제 2산화막 표면으로 상단 부분이 일부 돌출된 형상을 가진 제 1도전 플러그를 형성하는 단계와,결과물 상에 제 3산화막을 형성하는 단계와, 제 3산화막을 식각하여 돌출된 제 1도전 플러그의 상단 및 측면 일부를 노출시키는 제 2콘택홀을 형성하는 단계와, 제 2콘택홀을 채워 제 1도전 플러그와 연결되는 제 2도전 플러그를 형성하는 단계를 포함한 것을 특징으로 한다.The conductive plug forming method of the present invention for achieving the above object comprises the steps of sequentially forming a first oxide film, a nitride film and a second oxide film on a semiconductor substrate, and etching a portion of the substrate by etching the second oxide film, the nitride film and the first oxide film. Forming a first contact hole to be exposed; forming a first conductive film on the second oxide film including the first contact hole; using the second oxide film as a polishing stop film, polishing the first conductive film (1) forming a first conductive plug having a contact hole, the upper portion of which is partially protruded into the surface of the second oxide layer, forming a third oxide layer on the resultant, and etching the third oxide layer to protrude Forming a second contact hole exposing a portion of the top and side surfaces of the first conductive plug; and forming a second conductive plug connected to the first conductive plug by filling the second contact hole. It characterized.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 도전 플러그 형성 방법을 보인 공정단면도.2A to 2E are cross-sectional views illustrating a method of forming a conductive plug according to the present invention.
본 발명의 도전 플러그 형성 방법은, 도 2a에 도시된 바와 같이, 먼저, 반도체기판(200) 상에 제 1산화막(202), 질화막(204) 및 제 2산화막(206)을 차례로 화학기상증착한다. 이때, 상기 제 1산화막(202)은 6000∼8000Å 두께로 형성하고, 상기 질화막은 1500∼2500Å 두께로 증착한다. 또한, 상기 제 2산화막(206)은 1000∼2000Å 두께로 증착한다.In the conductive plug forming method of the present invention, as shown in FIG. 2A, first, the first oxide film 202, the nitride film 204, and the second oxide film 206 are sequentially chemically vapor deposited on the semiconductor substrate 200. . In this case, the first oxide film 202 is formed to a thickness of 6000 ~ 8000 Å, and the nitride film is deposited to a thickness of 1500 ~ 2500 Å. In addition, the second oxide film 206 is deposited to a thickness of 1000 to 2000 GPa.
이어서, 상기 제 2산화막(206) 상에 감광막을 도포하고 노광 및 현상하여 제 1콘택홀 형성영역이 정의된 제 1감광막 패턴(220)을 형성한다.Subsequently, a photoresist film is coated on the second oxide film 206, exposed to light, and developed to form a first photoresist film pattern 220 in which a first contact hole formation region is defined.
그 다음, 도 2b에 도시된 바와 같이, 상기 제 1감광막 패턴(220)을 마스크로 하고 포토리소그라피 공정에 의해 상기 제 2산화막, 질화막 및 제 1산화막을 식각하여 제 1콘택홀(203)을 형성한다. 이 후, 상기 제 1감광막 패턴을 제거한다. 이때, 상기 제 1콘택홀(203) 형성 시, 제 2산화막(206)과 질화막(204)의 식각 속도비가 1:0.7∼1:1.3이 되도록 하여 질화막의 식각을 용이하게 한다.Next, as shown in FIG. 2B, the first photoresist pattern 220 is used as a mask and the second oxide film, the nitride film, and the first oxide film are etched by a photolithography process to form a first contact hole 203. do. Thereafter, the first photoresist pattern is removed. At this time, when the first contact hole 203 is formed, the etching rate ratio between the second oxide film 206 and the nitride film 204 is 1: 0.7 to 1: 1.3 to facilitate etching of the nitride film.
이어, 상기 제 1콘택홀(203)을 포함한 제 2산화막(206) 상에 스퍼터링 공정에 의해 텅스텐 등의 제 1도전막을 4000∼5000Å 두께로 증착한 후, 상기 제 2산화막(206)이 노출되는 시점까지 상기 제 1도전막을 화학적-기계적 연마하여 제 1콘택홀을 채우는 제 1도전 플러그(210)를 형성한다. 이때, 상기 화학적-기계적 연마 공정 시, 상기 제 2산화막(206)은 연마 멈춤막으로서의 역할을 한다. 또한, 상기 화학적-기계적 연마 공정 시, 제 2산화막(206)에 대한 제 1도전막의 연마 속도비가 6:1∼8:1이 되도록 하여 과도하게 연마 공정이 진행된다 할지라도 연마 멈춤막인 제 2산화막의 손실이 1000Å 이하가 되도록 한다.Subsequently, a first conductive film, such as tungsten, is deposited to a thickness of 4000 to 5000 micrometers by a sputtering process on the second oxide film 206 including the first contact hole 203, and then the second oxide film 206 is exposed. The first conductive film is chemically-mechanically polished to a point in time to form a first conductive plug 210 filling the first contact hole. At this time, in the chemical-mechanical polishing process, the second oxide film 206 serves as a polishing stop film. In addition, during the chemical-mechanical polishing process, the polishing rate ratio of the first conductive film to the second oxide film 206 is 6: 1 to 8: 1 so that the polishing stop film is excessive even if the polishing process is excessively performed. The loss of the oxide film is set to 1000 mW or less.
그런 다음, 도 2c에 도시된 바와 같이, 상기 제 1도전 플러그를 포함한 제 2산화막(206) 상에 제 3산화막(212)을 4000∼6000Å 두께로 증착한 다음, 상기 제 3산화막(212) 상에 제 2콘택홀 형성영역(미도시)이 정의된 제 2감광막 패턴(222)을 형성한다.Then, as illustrated in FIG. 2C, a third oxide film 212 is deposited to a thickness of 4,000 to 6000 microseconds on the second oxide film 206 including the first conductive plug, and then on the third oxide film 212. A second photoresist layer pattern 222 having a second contact hole forming region (not shown) is formed in the substrate.
이 후, 도 2d에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하고 포토리쏘그라피 공정에 의해 상기 제 3절연막을 식각하여 상기 제 1도전 플러그(210)의 상단 및 측면 일부분을 노출시키는 제 2콘택홀(213)을 형성한다. 그리고 제 2감광막 패턴을 제거한다.Subsequently, as shown in FIG. 2D, the second photoresist pattern is used as a mask, and the third insulating layer is etched by a photolithography process to expose the upper and side portions of the first conductive plug 210. Two contact holes 213 are formed. Then, the second photosensitive film pattern is removed.
이어, 도 2e에 도시된 바와 같이, 상기 제 2콘택홀(213)을 포함한 제 3절연막(213) 상에 다시 스퍼터링 공정에 의해 텅스텐 등의 제 2도전막을 4000∼5000Å 두께로 증착한 후, 상기 제 3절연막을 화학적-기계적 연마하여 제 2도전 플러그(230)를 형성한다.Subsequently, as shown in FIG. 2E, a second conductive film such as tungsten is deposited to a thickness of 4000 to 5000 kV by a sputtering process again on the third insulating film 213 including the second contact hole 213. The third insulating film is chemically-mechanically polished to form the second conductive plug 230.
이때, 상기 제 2도전 플러그(220)는 상기 제 2콘택홀을 통해 상기 제 1도전 플러그(210)의 상단 및 측면의 일부와 연결되므로 접촉 면적이 증가된다.In this case, since the second conductive plug 220 is connected to a part of the top and side surfaces of the first conductive plug 210 through the second contact hole, the contact area is increased.
이상에서와 같이, 본 발명의 방법에서는 제 2도전 플러그가 제 1도전 플러그의 상단 및 측면과 접촉함으로써, 상기 제 1 및 제 2도전 플러그 간의 접촉면적이 커질 뿐만 아니라 접착력 또한 증가되는 잇점이 있다.As described above, in the method of the present invention, as the second conductive plug contacts the top and side surfaces of the first conductive plug, not only the contact area between the first and second conductive plugs is increased but also the adhesive force is increased.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR10-2001-0082676A KR100406582B1 (en) | 2001-12-21 | 2001-12-21 | method for forming conductive plug |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1126580A (en) * | 1997-07-04 | 1999-01-29 | Nec Corp | Manufacture of semiconductor device |
| KR19990060919A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Metal wiring formation method of semiconductor device |
| KR19990075358A (en) * | 1998-03-19 | 1999-10-15 | 윤종용 | Manufacturing method of DRAM cell capacitor |
| JP2000077622A (en) * | 1998-08-31 | 2000-03-14 | Texas Instr Inc <Ti> | Semiconductor memory device and its manufacture |
| KR20000021156A (en) * | 1998-09-26 | 2000-04-15 | 윤종용 | Method for forming metal contact in semiconductor device |
| KR20020066569A (en) * | 2001-02-12 | 2002-08-19 | 삼성전자 주식회사 | Method of forming a storage node in an integrated circuit device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1126580A (en) * | 1997-07-04 | 1999-01-29 | Nec Corp | Manufacture of semiconductor device |
| KR19990060919A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Metal wiring formation method of semiconductor device |
| KR19990075358A (en) * | 1998-03-19 | 1999-10-15 | 윤종용 | Manufacturing method of DRAM cell capacitor |
| JP2000077622A (en) * | 1998-08-31 | 2000-03-14 | Texas Instr Inc <Ti> | Semiconductor memory device and its manufacture |
| KR20000021156A (en) * | 1998-09-26 | 2000-04-15 | 윤종용 | Method for forming metal contact in semiconductor device |
| KR20020066569A (en) * | 2001-02-12 | 2002-08-19 | 삼성전자 주식회사 | Method of forming a storage node in an integrated circuit device |
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