KR100218246B1 - Process for forming contact hole - Google Patents
Process for forming contact hole Download PDFInfo
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- KR100218246B1 KR100218246B1 KR1019960031340A KR19960031340A KR100218246B1 KR 100218246 B1 KR100218246 B1 KR 100218246B1 KR 1019960031340 A KR1019960031340 A KR 1019960031340A KR 19960031340 A KR19960031340 A KR 19960031340A KR 100218246 B1 KR100218246 B1 KR 100218246B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 상부 도전층과 하부 도전층을 전기적으로 연결하기 위한 접촉개구부의 제조방법에 관한 것이다. 본 발명에서는, 반도체 기판상에 형성된 하부 도전층상에 제1절연층을 침적한 뒤, 상기 제1절연층 전면을 소정 깊이로 식각한다. 이어서, 상기 식각된 제1절연층상에 제2절연층을 침적한 후 순차적으로 등방성 식각과 이방성 식각을 수행함으로써, 접촉개구부 형성시에 발생되는 보이드 및 끊어짐 문제를 해소할 수 있다.The present invention relates to a method of manufacturing a contact opening for electrically connecting an upper conductive layer and a lower conductive layer. In the present invention, after the first insulating layer is deposited on the lower conductive layer formed on the semiconductor substrate, the entire surface of the first insulating layer is etched to a predetermined depth. Subsequently, by depositing a second insulating layer on the etched first insulating layer and sequentially performing isotropic etching and anisotropic etching, it is possible to solve the problem of voids and breaks generated when the contact openings are formed.
Description
본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 반도체 장치의 접촉개구부 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a contact opening of a semiconductor device.
일반적으로 집적회로 제조시에 발생되는 메탈층의 끊김이나 보이드(Void)를 방지하기 위하여 메탈 콘택 프로파일(Profile)을 완만하게 유지하거나 콘택이 형성되어질 개구부의 에스팩트 비(Aspect ratio)를 줄일 수 있는 방법들이 요구되고 있다. 따라서, 종래에는 사진식각(Photolithography)공정으로 접촉개구부의 패턴을 형성한 후에 순차적으로 습식화학공정(Wet Chemical)등으로 등방성식각을 진행하고, 이어서 건식식각등으로 이방성 식각을 진행하여 완만한 접촉 개구부 모양을 형성하는 방법이 사용되었다. 상기한 방법을 실시함에 있어서, 등방성 식각 모양은 하부 절연막의 종류에 따라 달라지게 되는데 메탈 콘택을 형성하기 전에 반도체 기판 표면을 평탄화시키기 위해 주로 BPSG(Borophosphosilicate glass)나 PSG(Phosphosilicate glass)와 같은 막질이 사용되었다. 그러나 이러한 막질은 깊이 방향의 식각비율(Etch rate)보다 포토 레지스터와 산화막(Oxide)간 계면의 식각 비율이 크다는 문제점이 있었다.In general, in order to prevent breakage or voids in the metal layer generated during integrated circuit fabrication, the metal contact profile may be kept soft or the aspect ratio of the opening to be contacted may be reduced. Methods are required. Therefore, conventionally, after forming a contact opening pattern by a photolithography process, isotropic etching is sequentially performed by a wet chemical process or the like, and then anisotropic etching is performed by dry etching. A method of forming the shape was used. In the above-described method, the isotropic etching shape depends on the type of the lower insulating film. In order to planarize the surface of the semiconductor substrate before forming the metal contact, a film quality such as borophosphosilicate glass (PSG) or phosphosilicate glass (PSG) is mainly used. Was used. However, this film quality has a problem that the etching rate of the interface between the photoresist and the oxide (Oxide) is larger than the etching rate in the depth direction.
따라서, 반도체 장치가 점차 고집적화되면서 제조공정중 히트 사이클(Heat cycle)을 줄어드는 경향에 따라 평탄화를 위한 리플로우(Reflow)공정이 필요한 상기 BPSG 또는 PSG보다 리플로우 공정을 수행함이 없이도 반도체 기판 표면을 평탄화시킬 수 있는 O3TEOS(Tetraethylosilicate)와 같은 막질이 주로 이용되고 있다. 그러나 상기 O3TEOS는 BPSG나 PSG와는 달리 포토 레지스터와 옥사이드계면에서의 식각비율 보다 깊이 방향으로서 식각비율이 커서 등방성 식각후 프로파일이 급경사를 나타내기 때문에 후속 단계에서 메탈과 같이 단차피복성(Step coverage)이 취약한 층을 침적할 경우 메탈이 끊어지는 문제점이 발생된다. 한편, 등방성식각후 모양을 보다 완만하게 유지하기 위하여 등방성 식각량을 줄일 경우 이방성 식각량이 증가해야 하며, 이에 따라 에스팩트 비가 증가하여 후속 메탈층 침적시 보이드(Void)가 발생할 가능성이 높아지게 되고, 메탈이 콘택을 채우지 못해 끊어짐이 발생할 수 있다.Accordingly, as semiconductor devices become more highly integrated, the surface of semiconductor substrates are planarized without performing a reflow process than the BPSG or PSG, which requires a reflow process for planarization as the heat cycle of the manufacturing process is reduced. Membrane such as O 3 TEOS (Tetraethylosilicate), which can be used, is mainly used. However, unlike the BPSG or PSG, the O 3 TEOS has a higher etch rate than the etch rate at the photoresist and oxide interface, so that the profile shows a steep slope after isotropic etching. ) Depositing a weak layer causes the metal to break. On the other hand, if the isotropic etching amount is reduced to maintain the shape more smoothly after isotropic etching, the anisotropic etching amount should be increased. Accordingly, the aspect ratio increases, and thus, the possibility of voids in the subsequent metal layer deposition is increased. Failure to fill this contact can result in a break.
제1도를 참조하여 종래의 문제점을 부연하면, 반도체 장치를 제조함에 있어서 메탈층을 형성하기 이전에 실시하는 절연층(103) 형성 공정에서는 일반적으로 평탄화 공정, 예를들면 BPSG 리플로우(Reflow)공정을 실시한다. 왜냐하면, 메탈층을 형성하기전에 실시된 여러 가지 하부층 형성공정으로 인하여 반도체 기판 표면의 단차가 심하므로, 평탄화 공정을 실시하지 않을 경우 메탈층에 대한 사진공정시 난반사로 인해 메탈모양이 불량해지기 때문이다. 그런데 반도체 디바이스가 점차 미세화됨에 따라 경션이 깊이를 가능하면 얕게 유지하는 것이 디바이스 제작에 유리하기 때문에 경션형성 이후의 열처리는 줄이는 것이 좋고, 이를 위해 메탈층 전 평탄화에서도 리플로우등의 열처리가 없는 O3TEOS를 이용한 평탄화공정이 많이 쓰이고 있다.Referring to FIG. 1, the conventional problem is further described. In the process of forming the insulating layer 103, which is performed before forming the metal layer in the manufacture of a semiconductor device, a planarization process such as BPSG reflow is generally performed. Carry out the process. Because the step of the surface of the semiconductor substrate is severe due to the various lower layer forming process performed before the metal layer is formed, if the planarization process is not performed, the metal shape becomes poor due to the diffuse reflection during the photo process on the metal layer. to be. However O 3 without the heat treatment because gyeongsyeon this is advantageous for the device processing to keep a shallow if possible, the deep heat treatment after gyeongsyeon formation is good and to reduce, the metal layer for this purpose before flattening in reflow, etc. As the semiconductor device gradually miniaturization The planarization process using TEOS is used a lot.
특히, 메탈과 메탈사이의 평탄화에서는 하부 메탈층이 열처리를 견디지 못하기 때문에 O3TEOS등을 사용한 저온 평탄화가 필수적이다. 그러나 O3TEOS를 평탄화에 사용할 때 문제점은 앞에서도 언급한 바와 같이 습식식각시 모양이 불량하여 메탈침적시 끊어짐(참조부호 A)과 같은 불량이 발생하는것이다.In particular, in the planarization between metal and metal, low temperature planarization using O 3 TEOS is essential because the lower metal layer cannot withstand heat treatment. However, when O 3 TEOS is used for flattening, the problem is that, as mentioned above, the shape of the wet etching is poor, so that a defect such as breaking during metal deposition (reference A) occurs.
따라서, 본 발명의 목적은 평탄화공정이 필요 없으면서도 완만한 모양을 가지는 접촉개구부 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a contact opening having a gentle shape without the need for a planarization process.
본 발명의 다른 목적은 메탈층을 형성할 때 발생되는 보이드 문제를 해소할 수 있는 접촉개구부 제조방법을 제공함에 있다.Another object of the present invention is to provide a method for manufacturing a contact opening that can solve a void problem generated when forming a metal layer.
제1도는 종래의 기술에 따라 형성된 반도체 소자의 접촉개구부를 나타낸 단면도.1 is a cross-sectional view showing a contact opening of a semiconductor device formed according to the prior art.
제2(a)도 내지 제2(d)도는 본 발명의 일 실시예에 따라 반도체 소자의 접촉개구부 형성과정을 설명하기 위한 단면도들.2 (a) to 2 (d) are cross-sectional views illustrating a process of forming contact openings of a semiconductor device according to an exemplary embodiment of the present invention.
제3(a)도 내지 제3(e)도는 본 발명의 다른 실시예에 따라 반도체 소자의 접촉개구부 형성과정을 설명하기 위한 단면도들.3 (a) to 3 (e) are cross-sectional views illustrating a process of forming contact openings of a semiconductor device according to another exemplary embodiment of the present invention.
이하, 본 발명의 바람직한 실시예들을 첨부된 도면들을 참조하여 설명하고자 한다. 도면들중 동일한 구성요소 및 부분들은 가능한 한 어느곳에서든지 동일한 부호들을 나타내고 있음을 유의하여야 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.
제2(a)도 내지 제2(d)도는 본 발명의 일 실시예에 따른 접촉개구부 제조과정을 설명하기 위한 단면도들이다.2 (a) to 2 (d) are cross-sectional views for explaining a manufacturing process of the contact opening according to an embodiment of the present invention.
제2(a)도는 실리콘 기판상(201)에 통상의 방법으로 도전층(202)을 형성한 후 제1절연층(203)을 형성한 단면도이다. 이때, 상기 제1절연층(203)은O 3TEOS를 이용하여 430℃, 상압,O 3농도 150g/㎤, Si-소오스N 20.378 slm,O 29ℓ 조건하에서 약 3000Å∼7000Å로 침적하는 것이 바람직하다.FIG. 2 (a) is a cross-sectional view of the first insulating layer 203 formed after the conductive layer 202 is formed on the silicon substrate 201 in a conventional manner. At this time, the first insulating layer 203 is deposited at about 3000 kPa to 7000 kPa under conditions of 430 DEG C, atmospheric pressure, O 3 concentration of 150 g / cm 3 , Si-source N 2 0.378 slm, and O 2 9L using O 3 TEOS. desirable.
제2(b)도는 상기 제1절연층(203)의 두께가 약 1000Å∼5000Å이 되도록 전면 식각한 후, 그 상부에 제2절연층(204)을 형성한 단면도이다. 이때, 제2절연층(204)은 PE-SiH4(또는 PE-TEOS)를 이용하여 400℃, 2.8∼2.9torr, 400mils,SiII 495 sccm,N 2 O1800 sccm의 조건하에서 약 2000Å∼5000Å의 두께로 침적하는 것이 바람직하다.FIG. 2 (b) is a cross-sectional view of the first insulating layer 203 having the entire surface etched to have a thickness of about 1000 kPa to 5000 kPa, and then forming a second insulating layer 204 thereon. At this time, the second insulating layer 204 is about 2000 kPa to 5000 kPa under conditions of 400 ° C, 2.8 to 2.9torr, 400mils, SiII 4 95 sccm and N 2 O 1800 sccm using PE-SiH4 (or PE-TEOS). It is preferable to deposit in thickness.
제2(c)도는 포토레지스터(205)를 이용하여 즉 이방성 식각을 할 수 있는 폭 C의 개구부를 통하여 BOE(Buffered Oxide Etchant)로 약 2500Å∼5500Å 식각한 후의 등방성 식각 모양(206)을 표시한 도면이다.FIG. 2 (c) shows an isotropic etching pattern 206 after etching about 2500Å to 5500Å with BOE (Buffered Oxide Etchant) through the photoresist 205, i.e., through an opening of width C capable of anisotropic etching. Drawing.
제2(d)도는 건식식각을 통한 이방성식각 모양(207)과 상기 포토레지스터(205)를 스트립(Strip)한 후의 단면도이다.FIG. 2 (d) is a cross-sectional view after stripping the anisotropic etching shape 207 and the photoresist 205 through dry etching.
상기 공정중 제1절연층(203)을 소정 깊이로 식각하는 것은 다음과 같은 이유에서이다. 즉, 저온 평탄화가 가능한 예를 들면 O3TEOS와 같은 절연층의 경우 침적하는 두께가 두꺼울수록 평탄화가 잘되는 반면, 제1절연층(203)과 제2절연층(204)전체 두께가 두꺼우면 접촉 개구부의 에스펙트 비가 커져서 후속 메탈층 침적시 보이드(Void)나 끊어짐과 같은 문제가 발생할 수 있기 때문에 제1절연층(203)을 두껍게 침적하여 평탄도를 향상시킨 후, 소정두께 식각하여 전체 절연층의 두께를 낮춤으로써 평탄도 향상과 절연층 두께 감소로 인한 접촉 개구부의 에스펙트 비가 감소를 이룰 수 있다. 이러한 경우 등방성 식각량은 제2절연층(204)의 두께보다 약 200Å∼1000Å 정도 더 많은 것이 바람직하다. 그 이유는 제1절연층(203)의 경우 제2절연층(204)과의 경계면이 전면 식각에 의한 접촉부위여서 후속 메탈층 침적전에 세척(Cleaning)시 예를 들면 100:1 HF를 사용할 경우 이 부위에서 데미지(Damage)에 의한 식각량 증가로 홈처럼 파인 모양이 발생할 수 있기 때문이다. 그런데, 홈이 건식식각 부위에 발생하게 되면, 메탈층 침적시 보이드나 메탈층의 끊어짐 등을 유발할 수 있기 때문에 홈이 발생할 수 있는 부위를 등방성 식각 모양내의 경사부위에 존재하게 하여 홈이 발생해도 보이드나 메탈층의 끊어짐이 발생하지 않도록 방지할 필요가 있게 되었다. 그러므로 등방성 식각량을 제2절연층 두께보다 약 200Å∼1000Å 정도 많도록 조절하는 것이 바람직하다.During the process, the first insulating layer 203 is etched to a predetermined depth for the following reason. That is, in the case of an insulating layer such as O 3 TEOS, which is capable of low temperature planarization, the thicker the deposition thickness, the better the planarization, while the thicker the entire thickness of the first insulating layer 203 and the second insulating layer 204 is in contact. Since the aspect ratio of the opening may increase, problems such as voids or breakage may occur during subsequent metal layer deposition, so that the first insulating layer 203 is thickly deposited to improve flatness, and then the entire insulating layer is etched by a predetermined thickness. By reducing the thickness of the substrate, the aspect ratio of the contact opening due to the improved flatness and the reduced thickness of the insulating layer may be reduced. In this case, the isotropic etching amount is preferably about 200 kPa to 1000 kPa more than the thickness of the second insulating layer 204. The reason for this is that in the case of the first insulating layer 203, the interface with the second insulating layer 204 is a contact region by the entire etching, so that 100: 1 HF is used during cleaning before subsequent metal layer deposition. This is because grooves like a groove may occur due to an increase in etching amount due to damage. However, when the groove is formed in the dry etching area, it may cause voids or breakage of the metal layer when the metal layer is deposited, so that the groove may be present in the inclined portion in the isotropic etching shape so that the groove is visible. It is necessary to prevent the chip | tip or the metal layer from breaking. Therefore, it is preferable to adjust the isotropic etching amount to be about 200 kPa to 1000 kPa more than the thickness of the second insulating layer.
제3(a)도 내지 제3(e)도는 본 발명의 다른 실시예에 따른 접촉개구부 제조공정을 설명하기 위한 단면도들이다.3 (a) to 3 (e) are cross-sectional views illustrating a manufacturing process of the contact opening according to another embodiment of the present invention.
제3(a)도는 실리콘 기판(301)상에 통상의 방법으로 도전층(302)을 형성한 후 제1절연층(303)을 형성한 단면도이다. 이때, 상기 제1절연층(303)은 03TEOS를 이용하여O 3농도 150g/㎤, Si-소오스N 20.378 slm,O 29ℓ 조건하에서 약 3000Å∼7000Å로 침적하는 것이 바람직하다.FIG. 3A is a cross-sectional view of the first insulating layer 303 after the conductive layer 302 is formed on the silicon substrate 301 by a conventional method. In this case, the first insulating layer 303 is preferably deposited at about 3000 kPa to 7000 kPa under O 3 concentration of 150 g / cm 3 , Si-source N 2 0.378 slm, and O 2 9 L using 0 3 TEOS.
제3(b)도는 상기 제1절연층(303)의 두께가 약 1000Å∼5000Å이 되도록 전면 식각한 후, 그 상부에 제2절연층(304)을 형성한 단면도이다. 이때, 제2절연층(304)은 PE-SiH4(또는 PE-TEOS)를 이용하여 400℃, 2.8∼2.9torr, 400mils,SiII 495 sccm,N 2 O1800 sccm의 조건하에서 약 2000Å∼5000Å의 두께로 침적하는 것이 바람직하다.FIG. 3B is a cross-sectional view of the first insulating layer 303 having the entire surface etched to have a thickness of about 1000 kPa to 5000 kPa, followed by forming a second insulating layer 304 thereon. At this time, the second insulating layer 304 of about 2000 kPa to 5000 kPa under conditions of 400 ° C, 2.8-2.9torr, 400mils, SiII 4 95 sccm, N 2 O 1800 sccm using PE-SiH4 (or PE-TEOS). It is preferable to deposit in thickness.
제3(c)도는 포토레지스터(305)를 이용하여 폭 C의 개구부를 형성한 후 약 500Å∼1500Å을 건식식각한 후의 식각 모양(310)을 나타낸 단면도이다.FIG. 3 (c) is a cross-sectional view showing the etching pattern 310 after the dry etching of about 500 kV to 1500 kV after the opening of the width C is formed using the photoresist 305. FIG.
제3(d)도는 BOE(Buffered Oxide Etchant)로 약 2000Å∼4500Å 식각한 후의 등방성 식각 모양(306)을 표시한 도면이다.FIG. 3 (d) shows an isotropic etching pattern 306 after etching about 2000 kPa to 4500 kPa with BOE (Buffered Oxide Etchant).
제3(e)도는 건식식각을 통한 이방성식각 모양(307)과 상기 코토레지스터(205)를 스트립(Strip)한 후의 단면도이다. 이 공정에서는 건식식각후 습식식각을 진행하여 완만한 식각모양(306)을 얻을 수 있다는 것을 보여주는 도면이다.FIG. 3 (e) is a cross-sectional view after stripping the anisotropic etched shape 307 and the koto register 205 through dry etching. In this process, it is a view showing that a gentle etching pattern 306 can be obtained by performing wet etching after dry etching.
전술한 바와 같이 본 발명에 따르면, 본 발명은 고온평탄화공정이 필요 없으면서도 완만한 모양의 접촉개구부를 얻을 수 있는 이점을 가진다. 또한 본 발명은 접촉개구부 형성시 발생될 수 있는 보이드와 끊어짐을 방지할 수 있는 이점을 가진다.As described above, according to the present invention, the present invention has the advantage of obtaining a smooth contact opening without the need for a high temperature flattening process. In addition, the present invention has the advantage of preventing voids and breakage that may occur when the contact opening is formed.
Claims (11)
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| KR1019960031340A KR100218246B1 (en) | 1996-07-29 | 1996-07-29 | Process for forming contact hole |
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| KR1019960031340A KR100218246B1 (en) | 1996-07-29 | 1996-07-29 | Process for forming contact hole |
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