KR100361572B1 - a manufacturing method of a contact structure of a semiconductor device - Google Patents
a manufacturing method of a contact structure of a semiconductor device Download PDFInfo
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- KR100361572B1 KR100361572B1 KR1019990067694A KR19990067694A KR100361572B1 KR 100361572 B1 KR100361572 B1 KR 100361572B1 KR 1019990067694 A KR1019990067694 A KR 1019990067694A KR 19990067694 A KR19990067694 A KR 19990067694A KR 100361572 B1 KR100361572 B1 KR 100361572B1
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- Prior art keywords
- film
- forming
- silicide
- plasma treatment
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 33
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000009832 plasma treatment Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 abstract description 5
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 4
- 125000006850 spacer group Chemical group 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract 1
- 229920000642 polymer Polymers 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 반도체 집적회로 공정에서 접촉 구조의 형성 방법에 관한 것으로서, 반도체 기판 위에 STI와 게이트 산화막, 게이트 전극을 형성한 다음, LDD 영역을 형성한다. 이어, 게이트 측벽 스페이서를 형성한 후, 소스 및 드레인을 형성하고 Ti막을 스퍼터링한다. 열처리 공정으로 Ti막을 실리사이드화 한 후 CHF3를 이용하여 1차 플라스마 처리하고 이어 O2를 이용하여 2차 플라스마 처리한다. 다음, TEOS막과 BPSG막을 증착하고 식각하여 게이트 전극 상부의 실리사이드막, 그리고 게이트 전극과 STI 사이의 실리사이드막을 각각 드러내는 접촉구를 형성하고, 드러난 실리사이드막을 O2플라스마 처리한다. 본 발명에서는 심한 거칠기를 가지는 실리사이드막을 플라스마 처리하여 거칠기를 감소시키므로 그 상부에 형성될 배선층과 접촉 면적이 넓어져 접촉 저항을 감소시킬 수 있다.The present invention relates to a method of forming a contact structure in a semiconductor integrated circuit process, wherein an STI, a gate oxide film, and a gate electrode are formed on a semiconductor substrate, and then an LDD region is formed. Subsequently, after forming the gate sidewall spacers, a source and a drain are formed and the Ti film is sputtered. After the silicide of the Ti film by the heat treatment process, the primary plasma treatment using CHF 3 and then the secondary plasma treatment using O 2 . Next, a TEOS film and a BPSG film are deposited and etched to form a contact hole exposing the silicide film on the gate electrode and the silicide film between the gate electrode and the STI, and the exposed silicide film is subjected to O 2 plasma treatment. In the present invention, since the silicide film having a severe roughness is treated by plasma to reduce the roughness, the contact area with the wiring layer to be formed on the upper portion is increased, thereby reducing the contact resistance.
Description
본 발명은 반도체 소자의 접촉 구조 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact structure of a semiconductor device.
최근 반도체 회로에서는 그 크기가 더욱 감소됨에 따라, 집적 회로에서의 배선을 다층화하고 이 배선들을 접촉구를 통해 연결하는 다층 배선 방법이 주로 사용되고 있다.In recent years, as the size of a semiconductor circuit is further reduced, a multilayer wiring method of multilayering wirings in an integrated circuit and connecting the wirings through contact holes is mainly used.
접촉구를 통하여 상부 배선과 하부 배선이 접촉할 때 생기는 접촉 저항은 접촉 면적과 접촉구 내의 폴리머 유무 그리고 접촉구 표면의 거칠기(roughness)에 의해 그 크기가 변한다.The contact resistance generated when the upper wiring and the lower wiring contact through the contact hole is changed in size by the contact area, the presence of polymer in the contact hole, and the roughness of the contact surface.
접촉구 하부에는 실리사이드막을 형성하기 위해 Ti와 같은 금속막을 증착하는데, Ti막은 미세한 기둥 구조(columnar structure)를 이루며 증착되고 이는 실리사이드막의 구조에도 영향을 미치므로 실리사이드막 표면은 거칠기가 크게 된다. 따라서, 막 표면의 빈틈(void) 사이에 형성되는 폴리머를 제거하기 어렵고 접촉 면적이 감소되어 접촉 저항을 증가시킨다.A metal film such as Ti is deposited below the contact hole to form a silicide film, and the Ti film is formed in a fine columnar structure, which affects the structure of the silicide film, thereby increasing the surface of the silicide film. Therefore, it is difficult to remove the polymer formed between voids of the film surface and the contact area is reduced to increase the contact resistance.
한편, 게이트 측벽 스페이서 위의 Ti막이 후속 공정에 의해 완전히 제거되지 않아, 게이트와 접촉구에 형성되는 배선 사이에 단락이 발생할 수도 있다.On the other hand, the Ti film on the gate sidewall spacer is not completely removed by a subsequent process, and a short circuit may occur between the gate and the wiring formed in the contact hole.
본 발명의 과제는 접촉구에서의 접촉 저항을 최소화하는 데 있다.An object of the present invention is to minimize the contact resistance at the contact.
본 발명의 다른 과제는 접촉구를 통해 드러난 표면의 거칠기를 감소시키는 데 있다.Another object of the present invention is to reduce the roughness of the surface exposed through the contact hole.
본 발명의 다른 과제는 배선과 게이트 사이의 단락을 방지하는 데 있다.Another object of the present invention is to prevent a short circuit between the wiring and the gate.
도 1 내지 도 4는 본 발명에 따른 접촉 구조 형성 방법을 공정 순서에 따라 나타낸 단면도이고,1 to 4 are cross-sectional views showing a method for forming a contact structure according to the present invention in a process sequence,
도 5 및 도 6은 각각 실리사이드막을 플라스마 처리하기 전과 후의 AFM 사진이다.5 and 6 are AFM photographs before and after plasma treatment of the silicide film, respectively.
이러한 과제를 해결하기 위해 본 발명에서는 실리사이드막의 표면을 플라스마 처리한다.In order to solve this problem, in the present invention, the surface of the silicide film is plasma treated.
본 발명에 따른 반도체 소자의 접촉 구조 형성 방법에서는 다수의 확산 영역을 포함하는 반도체 기판 위에 금속막을 증착한 다음, 열처리하여 확산 영역 위에 실리사이드막을 형성한다. 이어, 금속막을 제거하고 실리사이드막 표면을 플라스마 처리한다.In the method for forming a contact structure of a semiconductor device according to the present invention, a metal film is deposited on a semiconductor substrate including a plurality of diffusion regions, and then heat-treated to form a silicide film on the diffusion region. Next, the metal film is removed and the silicide film surface is plasma treated.
여기서, 플라스마 처리 단계는 CHF3를 이용하는 제1 플라스마 처리 단계 및O2를 이용하는 제2 플라스마 처리 단계를 포함하는 것이 좋다.Here, the plasma treatment step preferably includes a first plasma treatment step using CHF 3 and a second plasma treatment step using O 2 .
실리사이드막의 형성은 RTP 공정으로 이루어질 수 있다.The silicide film may be formed by an RTP process.
한편, 금속막은 NH4OH와 H2O2그리고 H2O의 혼합물로 이루어진 용액에 담그어 초음파 세척함으로써 제거할 수 있다.On the other hand, the metal film can be removed by immersing in a solution consisting of a mixture of NH 4 OH, H 2 O 2 and H 2 O by ultrasonic cleaning.
본 발명에서 금속막은 Ti, Co 및 W 중의 어느 하나로 이루어질 수 있다.In the present invention, the metal film may be formed of any one of Ti, Co, and W.
본 발명에서는 실리사이드막 표면을 처리한 다음, 절연막을 증착하는 단계, 감광막을 도포하고 패터닝하여 감광막 패턴을 형성하는 단계, 감광막 패턴을 마스크로 절연막을 식각하여 실리사이드막을 드러내는 접촉구를 형성하는 단계를 더 포함할 수 있다. 이어, 접촉구를 통해 드러난 실리사이드막을 O2플라스마 처리하는 단계를 더 포함할 수도 있다.In the present invention, the method further comprises the steps of: treating the surface of the silicide film, depositing an insulating film, applying and patterning the photosensitive film to form a photosensitive film pattern, and etching the insulating film using the photosensitive film pattern as a mask to form a contact hole exposing the silicide film. It may include. Subsequently, the method may further include O 2 plasma treatment of the silicide layer exposed through the contact hole.
이와 같이 본 발명에서는 건식 식각에 사용되는 가스를 이용하여 실리사이드막을 플라스마 처리함으로써 거칠기를 감소시키므로 그 상부에 형성될 배선층과의 접촉 면적이 넓어진다. 또한, 플라스마 처리시 접촉구 내의 폴리머도 제거할 수 있으므로 접촉 저항을 감소시킬 수 있다.As described above, in the present invention, the roughness is reduced by plasma treatment of the silicide film using a gas used for dry etching, so that the contact area with the wiring layer to be formed thereon is widened. In addition, since the polymer in the contact hole can be removed during the plasma treatment, the contact resistance can be reduced.
그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 공정에 대하여 상세하게 설명한다.Next, a process according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 반도체 소자의 접촉 구조 형성 방법을 공정 순서에 따라 나타낸 단면도이다.1 to 4 are cross-sectional views illustrating a method of forming a contact structure of a semiconductor device according to the present invention in a process sequence.
도 1에 도시한 바와 같이, 규소 기판(1) 위에 산화막으로 채워진 소자 분리영역 STI(shallow trench isolation)(2)를 형성한 다음, 게이트 산화막(3)과 다결정 규소로 이루어진 게이트 전극(4)을 형성한다. 이어, 이온을 저농도로 주입하여 LDD(lightly doped drain) 영역을 형성하고, 게이트 측벽 스페이서(5)를 형성한 후 고농도의 불순물을 주입하여 소스 및 드레인 영역(6)을 형성한다. 이어, 기판(1)을 HF 용액에 담그어 공기 중의 산소와 접촉하여 생긴 게이트 전극(3) 및 소스/드레인 영역(5) 표면의 산화막을 제거한 후, Ti막(7)을 스퍼터링한다. 여기서, Ti막(7) 대신 Co막이나 W막을 형성할 수도 있다.As shown in FIG. 1, a device isolation region STI (shallow trench isolation) 2 filled with an oxide film is formed on the silicon substrate 1, and then the gate oxide film 3 and the gate electrode 4 made of polycrystalline silicon are formed. Form. Subsequently, lightly doped drain (LDD) regions are formed by implanting ions at low concentration, and gate and sidewall spacers 5 are formed, and then high concentrations of impurities are implanted to form source and drain regions 6. Subsequently, the Ti film 7 is sputtered after removing the oxide film on the surface of the gate electrode 3 and the source / drain region 5 formed by immersing the substrate 1 in HF solution and contacting oxygen in the air. Here, a Co film or a W film may be formed instead of the Ti film 7.
다음, 도 2에 도시한 바와 같이 750℃, 질소(N2) 분위기에서 30초 동안 급속 열처리 과정(RTP : rapid thermal processing)을 이용하여 저항이 낮은 C49상의 TiSi 실리사이드막(71)을 형성하고, NH4OH와 H2O2그리고 H2O의 혼합물로 이루어진 용액에 담그어 초음파 세척함으로써 실리사이드화되지 않은 Ti막(7)을 제거한다. 다음, 실리사이드막(71)을 저항이 더 낮은 C54상의 TiSi로 형성하기 위해 910℃, 질소 분위기에서 약 10초 동안 열처리한다.Next, as shown in FIG. 2, a low resistance C49 TiSi silicide layer 71 is formed by using rapid thermal processing (RTP) for 30 seconds at 750 ° C. and nitrogen (N 2 ). The non-silicided Ti film 7 is removed by soaking in a solution composed of a mixture of NH 4 OH, H 2 O 2 and H 2 O. Next, the silicide film 71 is heat-treated for about 10 seconds at 910 DEG C and a nitrogen atmosphere to form TiSi having a lower resistance.
다음, 실리사이드막(71)을 플라스마 처리하는데, 다음과 같은 두 단계를 거친다. 먼저, 낮은 전력(power)를 이용하여 CHF3를 포함하는 기체로 플라스마를 형성하여 실리사이드막(71) 표면을 식각하고, 다음으로 낮은 전력, O2를 포함하는 기체로 플라스마 식각하여 실리사이드막(71)의 거칠기를 감소시키는 한편 실리사이드막(71) 표면의 폴리머를 제거한다. 이때, 스페이서(5) 상부에 제거되지 않고 남아있던 Ti막(7)도 함께 제거되므로 게이트 전극(4)과 소스/드레인 영역(6) 사이에 단락이 생기는 것을 방지할 수 있다.Next, the silicide film 71 is subjected to plasma treatment, and is subjected to the following two steps. First, plasma is formed using a gas containing CHF 3 using low power to etch a surface of the silicide layer 71, and plasma etching using a gas containing low power and O 2 is performed to etch the silicide layer 71. ), The polymer on the surface of the silicide film 71 is removed. At this time, since the Ti film 7 remaining on the spacer 5 without being removed is also removed, a short circuit can be prevented between the gate electrode 4 and the source / drain region 6.
다음, 도 3에 도시한 바와 같이, TEOS(tetraethyl orthosilicate)막(8)을 PECVD(plasma enhanced chemical vapor deposition) 방법으로 증착하고, 그 위에 BPSG(borophosphosilicate)막(9)을 증착한 후 CMP(chemical mechanical polishing)를 실시하여 BPSG막(9)을 평탄화한다. 여기서, TEOS막(8) 대신 질화막을 형성할 수도 있다.Next, as shown in FIG. 3, a TEOS (tetraethyl orthosilicate) film 8 is deposited by a plasma enhanced chemical vapor deposition (PECVD) method, and a BPSG (borophosphosilicate) film 9 is deposited thereon, followed by CMP (chemical). mechanical polishing) to planarize the BPSG film 9. Here, a nitride film may be formed instead of the TEOS film 8.
이어, 도 4에 도시한 바와 같이 감광막(10)을 도포하고 패터닝한 후, 감광막(10)을 마스크로 BPSG막(9), TEOS막(8)을 건식 식각하여, 게이트 전극(4) 상부의 실리사이드막(71)과 게이트 전극(4)과 트렌치(2) 사이의 실리사이드막(71)을 드러내는 접촉구(C1, C2)를 형성한다. 다음, O2를 포함한 식각 기체를 이용하여 플라스마 처리함으로써 식각 후 생성된 폴리머를 제거한다.Subsequently, as shown in FIG. 4, after the photoresist film 10 is applied and patterned, the BPSG film 9 and the TEOS film 8 are dry-etched using the photoresist film 10 as a mask, and the upper portion of the gate electrode 4 is dried. Contact holes C1 and C2 exposing the silicide film 71 and the silicide film 71 between the gate electrode 4 and the trench 2 are formed. Next, the polymer produced after etching is removed by plasma treatment using an etching gas containing O 2 .
다음, 감광막(10)을 제거하고 습식 세정을 실시한다.Next, the photosensitive film 10 is removed and wet cleaning is performed.
도 5 및 도 6은 실리사이드막(71)의 표면을 찍은 사진으로서, 각각 플라스마 처리하기 전과 후의 원자 힘 현미경(AFM : atomic force microscope) 사진이다. 도면에 나타난 바와 같이 플라스마 처리 후 실리사이드막(71) 표면의 거칠기가 감소되는 것을 알 수 있다.5 and 6 are photographs taken of the surface of the silicide film 71, and are atomic force microscope (AFM) photographs before and after plasma treatment, respectively. As shown in the figure, it can be seen that the roughness of the surface of the silicide film 71 after the plasma treatment is reduced.
이와 같이 본 발명에 따른 공정은 접촉구 하부의 실리사이드막을 플라스마 처리하여 표면의 거칠기를 감소시킴으로써 접촉 저항을 감소시킬 수 있으며, 플라스마 처리시 게이트 측벽 스페이서 위의 금속막도 제거할 수 있으므로 배선과 게이트 사이의 단락을 방지할 수 있다.As described above, the process according to the present invention can reduce the contact resistance by plasma treatment of the silicide film under the contact hole to reduce the roughness of the surface. Short circuit can be prevented.
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