KR19990084622A - Semiconductor device manufacturing method - Google Patents

Abstract

A semiconductor device manufacturing method according to the present invention comprises the steps of sequentially forming a pad oxide film, an anti-oxidation film and a photoresist pattern in an active region on the substrate so that a predetermined portion of the surface of the semiconductor substrate is exposed; Flowing the photoresist pattern on sidewalls of the anti-oxidation film and the pad oxide film using a heat treatment process; Forming a trench by etching a surface exposed portion of the substrate by using the photoresist pattern flowed by the heat treatment process as a mask; Forming an insulating film along an interface in the trench; Sequentially forming a first and a second USG on the antioxidant film including the inside of the trench; CMP treating the first and second USGs until the surface of the antioxidant film is exposed; And removing the anti-oxidation layer and the pad oxide layer in the active region, and thus it is possible to bring both edge portions of the STI higher than the surface of the substrate in the active region, so that the semiconductor device is generated at the interface between the active region and the inactive region. It is possible to prevent the deterioration of characteristics (for example, deterioration of the gate insulating film due to strong electric field concentration and inducing unwanted characteristics of the semiconductor device due to remaining polysilicon).

Description

Semiconductor device manufacturing method

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, through the securing of a stable profile of shallow trench isolation (STI), deterioration of characteristics of the semiconductor device generated at the interface between the active region and the inactive region without additional process. It relates to a semiconductor device manufacturing method to prevent the.

As semiconductor devices have been highly integrated, fine patterns have been required in fabricating devices, and channel widths of transistors and widths of field oxide films for isolation are also reduced. Accordingly, various techniques such as an isolation method, a LOCOS method, a modified LOCOS method, a trench isolation method, and the like have been developed.

1 to 6 show a process flowchart showing a device isolation method of a conventional semiconductor device to which TI technology directly related to the present invention is applied. Referring to this, the manufacturing method is briefly described as follows.

As a first step, as shown in FIG. 1, a pad oxide film 12, an anti-oxidation film 14 of nitride material, and a CVD oxide film 18 are sequentially formed on a semiconductor substrate (eg, a silicon substrate) 10. The photoresist pattern 18 is formed thereon so that the surface of the CVD oxide film 16 in the inactive region is exposed.

As a second step, as shown in FIG. 2, the CVD oxide film 16, the antioxidant film 14, and the pad oxide film 12 are exposed so that the surface of the substrate 10 in the inactive region is exposed using the photoresist pattern 18 as a mask. ) Is sequentially etched and the photoresist pattern 18 is removed to leave the CVD oxide film 16, the antioxidant film 14, and the pad oxide film 12 only in the active region where the active device is to be formed. Subsequently, the surface exposed portion of the substrate 10 is etched by a predetermined thickness using the remaining CVD oxide film 16 and the antioxidant film 14 as a mask to form a trench t.

As a third step, as shown in FIG. 3, an insulating film 20 made of a thermal oxide film is formed along the inner surface of the trench t, and a plasma treatment is performed under an NH ₃ atmosphere to form a gap fill in the trench t. It makes a good environmental condition to fill. Subsequently, a first USG (undoped silicate glass) 22a made of O ₃ -TEOS and a second USG made of PE-TEOS are formed on the entire surface of the resultant including the trench (t) to completely fill the inside of the trench (t). ) Are sequentially formed and the heat treatment process is performed to cure the first and second USGs 22a and 22b. As described above, the film deposition process is performed because the first USG 22a of the O ₃ -TEOS material has a better gap fill capability than the second USG 22b of the PE-TEOS material.

As a fourth step, as shown in FIG. 4, a first photoresist film (not shown) is formed on the second USG 22b and an etching process is performed such that the first photoresist film remains only in an inactive region by using a photoetch process. Then, it is reflowed at a predetermined temperature to be planarized by the first photosensitive film. Subsequently, a second photoresist film (not shown) is formed on the second USG 22b including the reflowed first photoresist film, and the first and second photoresist films and the first and second USGs 22a and 22b are formed. Etch back at the same time. The etch back at this time is carried out only until the CVD oxide film 16 having a predetermined thickness remains on the antioxidant film 14 as shown in FIG.

As a fifth step, as shown in FIG. 5, the first USG 22a and the CVD oxide film 16, which are etched back, are subjected to CMP again until the surface of the antioxidant film 14 is exposed, thereby forming a trench (t). An STI 24 made of an insulating film 20 and a first USG 22a is formed therein, and an anti-oxidation film 14 and a pad oxide film 12 having a predetermined thickness are left in an active region on the substrate 10.

As a sixth step, as shown in FIG. 6, the antioxidant layer 14 and the pad oxide layer 12 of the active region are sequentially removed, and a buffer oxide layer (not shown) is formed in the active region on the substrate 10. After performing the ion implantation process for forming a well and the ion implantation process for adjusting the threshold voltage (Vth), the buffer oxide layer is removed. Subsequently, the gate insulating film 26 is formed again in the portion where the buffer oxide film is removed, and the polysilicon film 28 is formed on the gate insulating film 26 including the STI 24, thereby completing the device isolation process.

However, when the device separation process proceeds as described above, the following two problems occur after the process progress is completed.

First, as shown in part I of FIG. 6, a concave valley is formed between both edge portions of the STI 24 and the substrate 10, so that the STI 24 is formed at the interface between the active and inactive regions. The phenomenon that the height is lower than the substrate surface occurs. This phenomenon occurs because silicon constituting the substrate is etched into the inside of the CVD oxide film 16 which acts as a mask when etching the substrate 10 to form the trench t. It is further intensified in the process of growing the thermal oxide film 20 along the interface. As such, when the STI 24 becomes lower than the surface of the substrate 10 of the active region at the interface between the active region and the inactive region, some polysilicon remains in this portion during the process of etching the polysilicon film to form the gate electrode. This phenomenon occurs, which causes a defect such as causing unwanted characteristics.

Second, since the top portion of the profile of the silicon substrate 10 profile does not have a round shape and has an angular shape in the state where the process is completed, the gate of this portion is later grown when the gate insulating layer 26 is grown. The insulating film thickness is made thinner than other portions. As described above, when the thickness of the gate insulating film of a specific portion (part indicated by the arrow in the drawing) becomes relatively thin, a phenomenon in which a strong electric field is concentrated on this portion is generated, resulting in a defect that deteriorates the gate insulating film. This is urgently required.

Accordingly, an object of the present invention is to change the process to bring the STI higher than the substrate surface of the active region at the interface between the active region and the inactive region when forming the STI of the semiconductor device, thereby generating the semiconductor at the interface between the active region and the inactive region. The present invention provides a method for manufacturing a semiconductor device, which can prevent deterioration of device characteristics, thereby improving reliability of the semiconductor device.

1 to 6 is a process flowchart showing a device isolation method of a conventional semiconductor device,

7 to 14 are process flowcharts illustrating a device isolation method of a semiconductor device according to the present invention.

In order to achieve the above object, the present invention includes the steps of sequentially forming a pad oxide film, an anti-oxidation film and a photoresist pattern in the active region on the substrate so that the surface of the semiconductor substrate is exposed to a predetermined portion; Flowing the photoresist pattern on sidewalls of the anti-oxidation film and the pad oxide film using a heat treatment process; Forming a trench by etching a surface exposed portion of the substrate by using the photoresist pattern flowed by the heat treatment process as a mask; Forming an insulating film along an interface in the trench; Sequentially forming a first and a second USG on the antioxidant film including the inside of the trench; CMP treating the first and second USGs until the surface of the antioxidant film is exposed; And removing the anti-oxidation layer and the pad oxide layer in the active region.

In the process as described above, since the STI can be brought higher than the surface of the active region at the interface between the active and inactive regions, deterioration of the gate insulating film caused by strong electric field concentration and the remaining of the polysilicon film during the formation of the gate electrode. It is possible to prevent the occurrence of defects, such as causing unwanted characteristics caused by.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

7 to 14 illustrate a process flowchart showing a device isolation method of a semiconductor device according to the present invention to which TI technology is applied. A manufacturing method thereof will be described below with reference to the drawings.

As a first step, as shown in FIG. 7, a pad oxide film 102 and a nitride film 104a are sequentially formed on a semiconductor substrate (eg, a silicon substrate) 100, and then the nitride film 104a is oxidized. A thin thickness oxynitride film (e.g., SiON) 104b is selectively formed only on the surface thereof. As a result, an antioxidant film 104 having a stacked structure of the nitride film 104a and the oxynitride film 104b is formed. As such, the reason why the anti-oxidation film 104 is formed in a stacked structure is that when the anti-oxidation film is formed only by the nitride film 104a, it is difficult to form a desired fine pattern due to the diffuse reflection of the nitride film 104a during the photoetching process. . Subsequently, a photoresist pattern 106 is formed on the antioxidant film 104 so that the surface of the antioxidant film 104 in the inactive region is exposed. 104 and the pad oxide film 102 are etched. In this case, in addition to the laminated structure of the nitride film 104a and the oxynitride film 104b, the polycrystalline silicon and the amorphous silicon can be applied as the antioxidant film 104.

As a second step, as shown in FIG. 8, the photoresist pattern 106 is flowed using a heat treatment process, so that the photoresist pattern 106 is also defined on the sidewalls of the antioxidant film 104 and the pad oxide film 102. To be present.

As a third step, as illustrated in FIG. 9, the surface exposed portion of the substrate 100 is etched by a predetermined thickness using a photosensitive film pattern 106 flowed by a heat treatment process as a mask to form a trench t.

As a fourth step, as shown in FIG. 10, a thin insulating film 108 is formed along the inner surface of the trench t, and plasma-processed in an NH ₃ atmosphere to form a gap fill in the trench t. Make it a good environmental condition. Then, the first USG (110a) of the O ₃ -TEOS material having a thickness of 4000 ~ 7000Å and the PE having a thickness of 1000 ~ 6000Å in front of the resultant including the trench (t) to completely fill the inside of the trench (t) A second USG 110b of TEOS is sequentially formed and heat-treated in a high temperature N ₂ gas atmosphere to cure the first and second USGs 110a and 110b. As such, the first USG 118a of the O ₃ -TEOS material is formed first because the first USG 110a has a better gap fill capability than the second USG 118b of the PE-TEOS material.

At this time, a thermal oxide film, a CVD oxide film, or an oxynitride film is mainly used as the insulating film 108. Therefore, when the insulating film is to be formed using the CVD oxide film, a thin oxide film is formed along the interface inside the trench t by the CVD method, and then plasma-processed using NH ₃ gas or under an N ₂ gas atmosphere. The process may be performed by heat treatment. On the other hand, when an insulating film is formed using an oxynitride film, a thermal oxide film having a predetermined thickness is formed along the interface inside the trench t using a thermal oxidation process, and then N After the annealing treatment for a predetermined time in a _two- gas atmosphere, the process may be performed by supplying N ₂ O gas continuously to oxidize the thermal oxide film.

As a fifth step, as shown in FIG. 11, a first photoresist film (not shown) is formed on the second USG 110b and an etching process is performed such that the first photoresist film remains only in an inactive region using a photoetch process. Then, it is reflowed at a predetermined temperature to be planarized by the first photosensitive film. Subsequently, a second photoresist film (not shown) is formed on the second USG 110b including the reflowed first photoresist film, and the first and second photoresist films and the first and second USGs 110a and 110b are formed. Etch back at the same time. At this time, the etch back is performed only until the first USG 110a having a predetermined thickness remains on the antioxidant film 104 as shown in FIG. 11.

As a sixth step, as shown in FIG. 12, the first USG 110a is subjected to CMP treatment until the surface of the antioxidant film 104 is exposed, so that the insulating film 108 and the first USG ( An STI 112 formed of 110a is formed, and an oxide film 104 and a pad oxide film 102 having a predetermined thickness are left in the active region on the substrate 100.

As a seventh step, as shown in FIG. 13, the antioxidant film 104 and the pad oxide film 102 are sequentially removed to expose the surface of the substrate 100 in the active region.

As an eighth step, as shown in FIG. 14, a buffer oxide film (not shown) is formed on an exposed surface of the substrate 100, a well forming ion implantation process and a threshold voltage adjustment ion implantation process are performed, and then the buffer is formed. Remove the oxide film. Subsequently, the gate insulating film 114 is formed again in the portion where the buffer oxide film is removed, and the polysilicon film 116 is formed on the gate insulating film 114 including the STI 112, thereby completing the device isolation process.

As described above, when the device isolation process is performed, the etching process of the substrate 100 is performed by using the photosensitive film pattern 106 flowed by the heat treatment process as a mask, as shown in the second step. The silicon forming the (100) hits the lower portion of the anti-oxidation film 104 so that the etching does not occur, and a concave valley is formed between the edges of the STI 112 and the substrate 100 which are finally made. The defective product does not occur. As a result, it is possible to prevent the deterioration of characteristics of the semiconductor device generated at the interface between the active region where the active element is formed and the inactive region where the STI 112 is formed.

On the other hand, as a modification of the present invention, the STI 112 forming process may be performed without applying the etch back process of the first and second photoresist layers and the first and second USGs 110a and 110b. Immediately after the deposition process of the first and second USGs 110a and 110b is completed, heat treatment is performed immediately under a high temperature N ₂ atmosphere, in which the first and second surfaces are exposed until the surface of the antioxidant film 104 is exposed. The process may be proceeded by CMP treatment of the second USGs 110a and 110b. In this case, the above-mentioned effects are equally applied.

As described above, according to the present invention, it is possible to bring both edge portions of the STI higher than the substrate surface of the active region through the process change, and thus, 1) the thickness of the gate insulating layer is different at the interface between the active region and the inactive region. Compared to this, the thinning of the gate insulating film is prevented due to the strong electric field concentration, and 2) the active region and the inactive region even after the polysilicon film etching process for forming the gate electrode is performed. The phenomenon that the polysilicon remains at the interface of the does not occur, thereby preventing unwanted characteristics caused by the remaining polysilicon.

Claims (11)

Sequentially forming a pad oxide film, an anti-oxidation film, and a photoresist pattern in an active region on the substrate so that a surface of the semiconductor substrate is partially exposed; Flowing the photoresist pattern on sidewalls of the anti-oxidation film and the pad oxide film using a heat treatment process; Forming a trench by etching a surface exposed portion of the substrate by using the photoresist pattern flowed by the heat treatment process as a mask; Forming an insulating film along an interface in the trench; Sequentially forming a first and a second USG on the antioxidant film including the inside of the trench; CMP treating the first and second USGs until the surface of the antioxidant film is exposed; And Removing the anti-oxidation film and the pad oxide film in the active region. The method of claim 1, wherein the anti-oxidation film is formed in a stacked structure of a nitride film and an oxynitride film. The method of claim 1, wherein the insulating layer is formed of any one selected from a thermal oxide film, a CVD oxide film, and an oxynitride film. 4. The method of claim 3, wherein when the insulating film is formed of a CVD oxide film, the insulating film is formed by forming a oxide film along an interface inside the trench using a CVD method and plasma treating the oxide film using NH ₃ gas. Forming through a semiconductor device manufacturing method characterized by. 4. The method of claim 3, wherein when the insulating film is formed of a CVD oxide film, the insulating film is formed through a process of forming an oxide film along an interface inside the trench by using a CVD method and a heat treatment under an N ₂ gas atmosphere. A semiconductor device manufacturing method characterized by. 4. The method of claim 3, wherein when the insulating film is formed of an oxynitride film, the insulating film is thermally oxidized to form a thermal oxide film along an interface inside the trench, and continuously after annealing for a predetermined time in an N ₂ gas atmosphere. Supplying N ₂ O gas to oxidize the thermal oxide film to form an oxynitride film. The method of claim 1, wherein the anti-oxidation film is formed of polycrystalline silicon or amorphous silicon. The method of claim 1, further comprising heat treatment under a high temperature N ₂ atmosphere after the formation of the first and second USGs. The method of claim 1, wherein the first USG is formed of O ₃ -TEOS having a thickness of 4000 to 7000 μs. The method of claim 1, wherein the second USG is formed of PE-TEOS having a thickness of 1000 to 6000 μs. The method of claim 1, further comprising: after forming the first and second USGs, selectively forming a first photoresist film only on an inactive region on the second USG, and reflowing the first photoresist film; Forming a second photoresist film on the reflowed first photoresist film and the second USG; And etching back the first and second photoresist film and the first and second USG until the first USG remains a predetermined thickness on the antioxidant film.