KR100349689B1 - Method for manufacturing ferroelectric memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a ferroelectric memory device using tantalum nitride as a diffusion barrier between a metal wiring and a capacitor. The present invention provides a method of forming a first interlayer dielectric layer on a semiconductor substrate on which an impurity diffusion layer is formed. Forming a capacitor including a lower electrode, a ferroelectric layer, and an upper electrode on the first interlayer insulating film, and forming a second interlayer insulating film on the semiconductor substrate including the upper electrode of the capacitor, to expose the impurity diffusion layer and the upper electrode. Patterning the second interlayer insulating film, forming a first tantalum nitride on the entire surface including the exposed impurity diffusion layer, and patterning the diffusion layer to remain only on the upper electrode of the capacitor; Tantalum, the second tantalum nitride And patterning the layer comprises forming a metal wiring for connecting the upper electrode and the impurity diffusion layer.

Description

Manufacturing method of ferroelectric memory device {METHOD FOR MANUFACTURING FERROELECTRIC MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a memory device, and more particularly, to a method of manufacturing a ferroelectric memory device using a tantalum nitride film as a diffusion barrier.

In general, SrBi ₂ Ta ₂ O ₉ (hereinafter referred to as SBT) and Pb (Zr, Ti) O ₃ (hereinafter referred to as PZT) thin films are mainly used as storage materials for ferroelectric memory devices (FeRAM). Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices. A nonvolatile memory device using a ferroelectric thin film adjusts the direction of polarization in the direction of an applied electric field and stores the digital signals "1" and "0" by the direction of residual polarization remaining when the electric field is removed. Hysteresis characteristics are used.

And low density (Low density) in the FeRAM device to the ferroelectric material _{PZT, SBT, Sr x Bi y} (Ta i Nb j) without using a plug ₂ O ₉ (hereinafter SBTN) having a perovskite (perovskite) structure, such as In the case of using a ferroelectric, a top electrode is typically formed of a metal such as Pt, Ir, Ru, or Pt alloy.

1 illustrates a conventional ferroelectric memory device, in which an interlayer insulating film 5 is formed on a semiconductor substrate 1 on which a gate insulating film 2, a gate electrode 3, and an impurity diffusion layer 4 are formed. SBT (SrBi ₂ Ta ₂ O ₉ ) is used as the ferroelectric film 7 on the insulating film 5, and platinum (Pt) is used as the upper and lower electrodes 6 and 8.

Platinum (Pt) used as the upper electrode (8) has a number of advantages, but the reaction occurs severely even at low temperatures with aluminum (Al) used as the material of the wiring 11 in the subsequent metal wiring process. To solve this problem, titanium nitride (TiN) is mainly used as the diffusion barrier layer 10.

However, titanium nitride (TiN) is not known to be a perfect diffusion barrier. In this case, titanium (Ti) of the diffusion barrier layer is diffused into the SBT in the subsequent metallization process to degrade the electrical characteristics. Therefore, such a device manufacturing process is a process that is less reliable, causing deterioration of the characteristics and yield of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in particular, a method of manufacturing a ferroelectric memory device suitable for improving the electrical characteristics of a metal wiring and an upper electrode of a capacitor using a tantalum / tantalum nitride film / tantalum laminated film as a diffusion barrier. The purpose is to provide.

1 shows a ferroelectric memory device of the prior art;

2 to 5 illustrate a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

21 semiconductor substrate 22 gate electrode

23a, 23b: impurity diffusion layer 24: first interlayer insulating film

25: high temperature oxide film 26: titanium oxide film

27: lower electrode 28: ferroelectric film

29: upper electrode 30a: TEOS

30b: BPSG 31: second interlayer insulating film

33: first tantalum nitride 34: tantalum

35 second tantalum nitride 36 first metal wiring

37: third interlayer insulating film 38: titanium

39: titanium nitride 40: aluminum

41: anti-reflection titanium nitride 42: second metal wiring

43: protective film

A method of manufacturing a ferroelectric memory device of the present invention for achieving the above object comprises the step of forming a first interlayer insulating film on a semiconductor substrate formed with an impurity diffusion layer, a lower electrode, a ferroelectric film, an upper electrode on the first interlayer insulating film Forming a capacitor, forming a second interlayer insulating film on the semiconductor substrate including the upper electrode of the capacitor, patterning the second interlayer insulating film to expose the impurity diffusion layer and the upper electrode, and the exposed impurities Forming a first tantalum nitride on the front surface including a diffusion layer and patterning so as to remain only in the upper electrode of the capacitor to form a diffusion barrier film of the first tantalum nitride, and tantalum, second tantalum on the front surface including the diffusion barrier Laminate and pattern nitride to form the phase Including the step of forming a metal wiring for connecting the electrode and the impurity diffusion layer is characterized by true.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

FIG. 2 is a diagram illustrating a ferroelectric capacitor formed up to a capacitor contact etching process, in which a cell region Y and a peripheral region X are defined, and a semiconductor substrate 21 having gate electrodes 22 and impurity diffusion layers 23a and 23b formed therein. A BPSG (Boron Phos-phorous Silicate Glass) film is deposited as a first interlayer insulating film 24 thereon, and the BPSG film is reflowed and planarized to apply a high temperature oxide (HTO) 25. . In order to remove moisture adsorbed on the high temperature oxide film 25, a curing process is performed for 10 minutes to 1 hour in a temperature range of 100 to 400 ° C.

Subsequently, titanium (Ti) is deposited on the high temperature oxide layer 25 to a thickness of 100 to 500 Å as an adhesion layer. Then, a titanium oxide film (TiO _X ) 26 is formed by heat-treating in an oxygen (O ₂ ) atmosphere for 10 minutes to 1 hour at a temperature of 500 to 800 ° C. using a furnace. Subsequently, a platinum (Pt) film is deposited on the titanium oxide film TiO _X 26 to a thickness of 1000 to 3000 Å.

Subsequently, conventional methods such as spin coating, Liquid Source Misted Chemical Deposition (LSMCD), Chemical Vapor Deposition (CVD), and Physical Vapor Deposition (Pt) on a platinum (Pt) film; PVD) is used to deposit the SBT ferroelectric film. Before depositing the ferroelectric film, heat treatment is performed for 10 minutes to 2 hours in the range of 100 to 500 ° C. for the purpose of improving adhesion between the ferroelectric film and the platinum (Pt) film, which is a lower electrode material.

Then, before depositing the upper electrode material, a curing process is performed at a temperature of 100 to 400 ° C. for about 10 minutes to 1 hour to remove moisture adsorbed on the ferroelectric film. Subsequently, a platinum (Pt) film, which is an upper electrode material, is deposited on the ferroelectric film to a thickness of 1000 to 3000 GPa. . At this time, electrode deposition conditions require a process temperature of 200 to 700 ° C, a pressure of 10 to 100 mTorr, and a power of 0.1 to 1 KW.

Subsequently, the platinum film / SBT / platinum film is patterned using a conventional photolithography and an etching process using a titanium nitride (TiN) hard mask and a photoresist film to form a lower electrode 27 / ferroelectric film 28 / upper electrode 29. A ferroelectric capacitor is formed.

Subsequently, after the ferroelectric capacitor is formed, a second interlayer insulating layer 31 is formed by depositing a TEOS (Tetra-Ethyl-Ortho-Silicate) 30a and a BPSG film 30b. Wherein the TEOS (30a) is characterized in that the deposition at 600 ~ 800 ℃, 1 atm, after depositing the BPSG film 30b, and heat treatment at 700 ~ 900 ℃ to improve the planarization and densification characteristics.

After the deposition process of the second interlayer insulating film 31, the capacitor contact hole 32 is opened using a conventional photolithography and etching process using a photosensitive film.

As shown in FIG. 3, a first tantalum nitride (TaN) 33 is deposited as a diffusion barrier on the BPSG film 30b including the capacitor contact hole 32 and the photolithography process is performed to obtain a capacitor. It is to be electrically connected to the upper electrode (29). The diffusion barrier is to prevent diffusion into the upper electrode (Pt) 29 and the capacitor, the first tantalum nitride (TaN) 33 is a conventional PVD, for example, RF sputtering (Radio Frequency-sputtering) It is deposited to a thickness of 500-2000 mm using DC reactive sputtering or chemical vapor deposition (CVD).

In the case of depositing the first tantalum nitride 33 using conventional reactive sputtering, a power of 0.5 to 3 KW is applied in a device maintaining a pressure of 1 to 100 mTorr and a temperature of 0 to 600 ° C. to 10 to 1000 sccm. Carry out in a nitrogen atmosphere at flow rate. In addition, when using a conventional CVD process, the step of tantalum nitride can be improved.

After the deposition of the first tantalum nitride 33, heat treatment is performed in an apparatus maintaining a temperature of 200 to 900 ° C. in a gas atmosphere of nitrogen (N ₂ ), argon (Ar), or oxygen (O ₂ ).

In this way, by applying the first tantalum nitride (TaN) 33 as a capacitor diffusion barrier, it is possible to prevent the deterioration of electrical characteristics due to titanium (Ti) generated in a subsequent process.

FIG. 4 is a cross-sectional view after a contact etching process for electrically connecting a capacitor and a transistor, and then completing a local interconnection between the capacitor and the transistor using a tantalum nitride (TaN) / tantalum (Ta) laminate.

As shown in FIG. 4, after the first tantalum nitride (TaN) 33, which is a diffusion barrier between the capacitor and the metal wiring, is patterned, the contact of the impurity diffusion layer 23b of the cell region Y of the semiconductor substrate 21 is patterned. Only the region is etched using a conventional photolithography and etching process to form a contact hole (not shown) in which a predetermined surface of the impurity diffusion layer 23b is exposed.

Subsequently, a tantalum (Ta) 34 is deposited to a thickness of 200 to 1000 GPa on the entire surface including the contact hole, and a second tantalum nitride (TaN) 35 is deposited to a thickness of 500 to 5000 GPa on the tantalum 34. Since the aluminum is not used, the thickness is too thin, the wiring resistance is high, and if the thickness is too thick, the step is increased to prevent the complexity of the subsequent photograph and etching process.

Subsequently, the laminated film of the second tantalum nitride 35 / tantalum 34 is subjected to subsequent heat treatment in an oxygen, nitrogen, or argon gas atmosphere.

This metal wiring process is performed only in the cell region Y to form the first metal wiring 36, which is a laminated film of tantalum 34 and second tantalum nitride 35, which connect between the capacitor and the transistor.

5 is a cross-sectional view after finishing the second metal wiring process after the deposition of the third interlayer insulating film.

That is, after the process of the first metal wiring 36 is finished, the third interlayer insulating film 37 is applied. A laminated film of BPSG, PSG, or SiON / SOG / silicon oxide film is used.

Subsequently, after the third interlayer insulating film 37 is applied, the contact hole (not shown) of the impurity diffusion layer 23a in the peripheral area X is opened using a conventional photolithography and etching process. Subsequently, in order to reduce the contact resistance of the impurity diffusion layer 23a, a cleaning process using a soft etch or a buffered oxide etchant (BOE) solution is performed. Then, titanium (Ti) 38 is deposited at about 50 to 1000 Å. Subsequently, the titanium nitride (TiN) 39 is deposited at about 300 to 1000 Å, and then heat-treated in a nitrogen atmosphere using a furnace to reduce contact resistance and to improve the prevention film properties of the titanium nitride 39. The heat treatment temperature and time at this time are about 300 to 500 ° C and about 10 minutes to 2 hours. This heat treatment process can be replaced by rapid thermal treatment (RTA).

Subsequently, after the titanium nitride 39 is deposited, aluminum 40 is deposited at about 1000 to 5000 mW, and titanium nitride (ARC-TiN) 41 having antireflection property is deposited at about 100 to 1000 mW.

Next, titanium (38) / titanium nitride (39) / aluminum (40) / anti-reflective titanium nitride are used to reduce the contact contact resistance between the impurity diffusion layer 23b and the wiring in the surrounding area using conventional photolithography and etching processes. The second metal wiring 42 having the laminated film structure of 41 is formed. The second metal wire 42 may be used as a wire for connecting peripheral circuits in the peripheral area X and used as bit line wiring and other wires in the cell area Y.

Subsequently, a passivation layer 43 is formed on the entire surface including the second metal wire 42.

In another application, tantalum aluminum nitride (TaAlN) or tantalum silicon nitride (TaSiN) may be used instead of tantalum nitride (TaN).

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, in the method of manufacturing the ferroelectric memory device of the present invention, since aluminum (Al) is not used in the first metal wiring process, the Pt / Al reaction by the subsequent thermal process can be prevented. In addition, by using the TaN / Ta / TaN structure as the capacitor diffusion barrier and the first metal wiring, it is possible to prevent the deterioration of electrical characteristics due to titanium (Ti) generated in a subsequent process.

In addition, since Al is not used in the entire device manufacturing process, the capacitor step can be dramatically reduced, thereby facilitating subsequent photographic and etching processes to improve device yield.

Claims (16)

Forming a first interlayer insulating film on the semiconductor substrate on which the impurity diffusion layer is formed; Forming a capacitor including a lower electrode, a ferroelectric layer, and an upper electrode on the first interlayer insulating film; Forming a second interlayer insulating film on the semiconductor substrate including the upper electrode of the capacitor; Patterning the second interlayer insulating film to expose the impurity diffusion layer and the upper electrode; Forming a first tantalum nitride on the entire surface including the exposed impurity diffusion layer and patterning the first tantalum nitride to remain only at the upper electrode of the capacitor to form a diffusion barrier layer formed of the first tantalum nitride; And Forming and patterning tantalum and second tantalum nitride on the entire surface including the diffusion barrier to form a metal wiring connecting the upper electrode and the impurity diffusion layer. Method of manufacturing a ferroelectric memory device, characterized in that made. The method of claim 1, The first tantalum nitride is subjected to 300 to 3000 kW by treating 0.5 to 3 kW of power and 10 to 1000 sccm of nitrogen gas under a pressure of 1 to 100 mTorr and a temperature of 30 to 600 C using reactive sputtering. A method of manufacturing a ferroelectric memory device, characterized in that deposited to a thickness. The method of claim 1, And depositing the first tantalum nitride at a temperature of 200 ° C. to 900 ° C. in a nitrogen, oxygen, or blister gas atmosphere. The method of claim 1, A method for manufacturing a ferroelectric memory device, wherein the second tantalum nitride is deposited to have a thickness of 500 to 5000 GPa. The method of claim 1, And depositing the tantalum / second tantalum nitride and heat-treating it in a nitrogen, oxygen, or argon gas atmosphere. The method of claim 1, The diffusion barrier layer made of the first tantalum nitride is a method of manufacturing a ferroelectric memory device, characterized in that the silicon contained in the first tantalum nitride. Forming a capacitor including a lower electrode, a ferroelectric film, and an upper electrode on a semiconductor substrate in which a cell region and a peripheral region are defined and an impurity diffusion layer is formed; After forming a first interlayer insulating film on the semiconductor substrate including the upper electrode, and forming a contact hole to expose a predetermined surface of the impurity diffusion layer and the upper electrode of the cell region by performing a photo and etching the first interlayer insulating film. ; Forming and patterning a first tantalum nitride in a contact hole formed on the upper electrode surface to form a diffusion barrier layer formed of the first tantalum nitride; Forming a tantalum and a second tantalum nitride on the entire surface including the first tantalum nitride; Patterning the tantalum and the second tantalum nitride to form a first metal wire connecting the upper electrode and the impurity diffusion layer of the cell region; Forming a second interlayer insulating film over the first metal wiring and patterning the second interlayer insulating film to expose the impurity diffusion layer in the peripheral region; And Forming a second metal interconnect electrically connected to the impurity diffusion layer in the peripheral region Method of manufacturing a ferroelectric memory device, characterized in that made. The method of claim 7, wherein The first tantalum nitride is subjected to 300 to 3000 kW by treating 0.5 to 3 kW of power and 10 to 1000 sccm of nitrogen gas under a pressure of 1 to 100 mTorr and a temperature of 30 to 600 C using reactive sputtering. A method of manufacturing a ferroelectric memory device, characterized in that deposited to a thickness. The method of claim 7, wherein And depositing the first tantalum nitride at a temperature of 200 ° C. to 900 ° C. in a nitrogen, oxygen, or blister gas atmosphere. The method of claim 7, wherein A method for manufacturing a ferroelectric memory device, wherein the second tantalum nitride is deposited to have a thickness of 500 to 5000 GPa. The method of claim 7, wherein And depositing the tantalum / second tantalum nitride and heat-treating it in a nitrogen, oxygen, or argon gas atmosphere. The method of claim 7, wherein And the first metal wiring is formed only in the cell region of the semiconductor substrate. The method of claim 7, wherein And the second metal wiring is formed in the cell region and the peripheral region of the semiconductor substrate. The method of claim 7, wherein The second metal wiring may be formed by stacking titanium, titanium nitride, aluminum, and titanium nitride having antireflection characteristics. The method of claim 14, And depositing the titanium and titanium nitride, followed by heat treatment using a furnace or rapid heat treatment in an oxygen, nitrogen, or argon gas atmosphere. The method of claim 7, wherein The diffusion barrier layer formed of the first tantalum nitride is a method of manufacturing a ferroelectric memory device, characterized in that the silicon contained in the first tantalum nitride.