KR100336750B1 - 양방향 지연을 이용한 디엘엘 회로 - Google Patents
양방향 지연을 이용한 디엘엘 회로 Download PDFInfo
- Publication number
- KR100336750B1 KR100336750B1 KR1019990030900A KR19990030900A KR100336750B1 KR 100336750 B1 KR100336750 B1 KR 100336750B1 KR 1019990030900 A KR1019990030900 A KR 1019990030900A KR 19990030900 A KR19990030900 A KR 19990030900A KR 100336750 B1 KR100336750 B1 KR 100336750B1
- Authority
- KR
- South Korea
- Prior art keywords
- delay
- unit
- clock signal
- external clock
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 10
- 230000001934 delay Effects 0.000 claims abstract description 11
- 230000000295 complement effect Effects 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 8
- 230000003111 delayed effect Effects 0.000 description 7
- 230000000644 propagated effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000002250 progressing effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Dram (AREA)
Abstract
Description
Claims (11)
- 외부 클럭신호를 지연하는 제1지연기와;상기 제1지연기의 출력을 입력받아 숏펄스 형태의 제1입력신호를 발생하는 제1펄스발생기와;반전된 외부 클럭신호를 지연하는 제2지연기와;상기 제2지연기의 출력을 입력받아 숏펄스 형태의 제2입력신호를 발생하는 제2펄스발생기와;상기 외부 클럭신호의 레벨에 따라 지연방향을 제어하기 위한 제1,제2제어신호를 발생하는 방향 제어부와;상기 방향 제어부에서 출력된 제1,제2제어신호에 따라 상기 제1입력신호 또는 제2입력신호를 순방향 및 역방향으로 지연시키는 복수의 단위 지연기들의 지연체인으로 구성된 것을 특징으로 하는 양방향 지연을 이용한 디엘엘 회로.
- 삭제
- 제1항에 있어서, 상기 제1,제2지연기는 서로 동일한 지연율로 구성된 것을 특징으로 하는 양방향 지연을 이용한 디엘엘 회로.
- 제1항에 있어서, 상기 방향 제어부는 외부 클럭신호를 순차 반전시켜 제1,제2제어신호를 출력하는 제1,제2인버터로 구성된 것을 특징으로 하는 양방향 지연을 이용한 디엘엘 회로.
- 제1항에 있어서, 상기 지연체인은 제1입력신호 또는 제2입력신호를 순방향 및 역방향으로 지연시키기 위하여 2개의 입력과 2개의 출력을 갖는 복수의 단위 지연기들로 구성되며, 각 단위 지연기는 제1,제2제어신호에 따라 서로 상보적으로 동작되는 제1,제2인버터로 구성된 것을 특징으로 하는 양방향 지연을 이용한 디엘엘 회로.
- 제5항에 있어서, 상기 복수의 단위 지연기들의 제1인버터들은 외부 클럭신호가 하이레벨일 때 인에이블되고, 제2인버터들은 외부 클럭신호가 로우레벨일 때 인에이블되게 구성된 것을 특징으로 하는 양방향 지연을 이용한 디엘엘 회로.
- 삭제
- 삭제
- 제5항에 있어서, 상기 제1,제2인버터는 각각 전원전압과 접지사이에 직렬 접속된 2개의 PMOS트랜지스와 2개의 NMOS트랜지스로 구성된 것을 특징으로 하는 양방향 지연을 이용한 디엘엘 회로.
- 제5항에 있어서, 상기 첫 번째 단위 지연기에서 제1인버터의 출력단자는 제2인버터의 입력단자에 접속되고, 마지막 단위지연기에서 제2인버터의 출력단자는 제1인버터의 입력단자에 접속된 것을 특징으로 하는 양방향 지연을 이용한 디엘엘 회로.
- 삭제
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990030900A KR100336750B1 (ko) | 1999-07-28 | 1999-07-28 | 양방향 지연을 이용한 디엘엘 회로 |
US09/476,380 US6239641B1 (en) | 1999-07-28 | 2000-01-03 | Delay locked loop using bidirectional delay |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990030900A KR100336750B1 (ko) | 1999-07-28 | 1999-07-28 | 양방향 지연을 이용한 디엘엘 회로 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010011503A KR20010011503A (ko) | 2001-02-15 |
KR100336750B1 true KR100336750B1 (ko) | 2002-05-13 |
Family
ID=19605448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019990030900A Expired - Fee Related KR100336750B1 (ko) | 1999-07-28 | 1999-07-28 | 양방향 지연을 이용한 디엘엘 회로 |
Country Status (2)
Country | Link |
---|---|
US (1) | US6239641B1 (ko) |
KR (1) | KR100336750B1 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6583653B1 (en) * | 2000-03-31 | 2003-06-24 | Intel Corporation | Method and apparatus for generating a clock signal |
KR100415544B1 (ko) * | 2001-06-25 | 2004-01-24 | 주식회사 하이닉스반도체 | 양방향 지연을 이용한 디엘엘 회로 |
US6930524B2 (en) * | 2001-10-09 | 2005-08-16 | Micron Technology, Inc. | Dual-phase delay-locked loop circuit and method |
US6759911B2 (en) | 2001-11-19 | 2004-07-06 | Mcron Technology, Inc. | Delay-locked loop circuit and method using a ring oscillator and counter-based delay |
US6621316B1 (en) | 2002-06-20 | 2003-09-16 | Micron Technology, Inc. | Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line |
JP3776847B2 (ja) * | 2002-07-24 | 2006-05-17 | エルピーダメモリ株式会社 | クロック同期回路及び半導体装置 |
US6727740B2 (en) | 2002-08-29 | 2004-04-27 | Micron Technology, Inc. | Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals |
KR100484250B1 (ko) * | 2002-10-30 | 2005-04-22 | 주식회사 하이닉스반도체 | 초기 딜레이를 제어하는 디지털 dll 회로 |
US6937076B2 (en) * | 2003-06-11 | 2005-08-30 | Micron Technology, Inc. | Clock synchronizing apparatus and method using frequency dependent variable delay |
US7130226B2 (en) * | 2005-02-09 | 2006-10-31 | Micron Technology, Inc. | Clock generating circuit with multiple modes of operation |
KR100854496B1 (ko) | 2006-07-03 | 2008-08-26 | 삼성전자주식회사 | 지연 동기 루프 및 이를 구비한 반도체 메모리 장치 |
JP4551431B2 (ja) * | 2007-09-18 | 2010-09-29 | 富士通株式会社 | 可変遅延回路,遅延時間制御方法および単位回路 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3309782B2 (ja) * | 1997-06-10 | 2002-07-29 | 日本電気株式会社 | 半導体集積回路 |
-
1999
- 1999-07-28 KR KR1019990030900A patent/KR100336750B1/ko not_active Expired - Fee Related
-
2000
- 2000-01-03 US US09/476,380 patent/US6239641B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR20010011503A (ko) | 2001-02-15 |
US6239641B1 (en) | 2001-05-29 |
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