KR100330580B1 - Quad flat package ic mounted pcb and soldering method thereof - Google Patents
Quad flat package ic mounted pcb and soldering method thereof Download PDFInfo
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- KR100330580B1 KR100330580B1 KR1019990036349A KR19990036349A KR100330580B1 KR 100330580 B1 KR100330580 B1 KR 100330580B1 KR 1019990036349 A KR1019990036349 A KR 1019990036349A KR 19990036349 A KR19990036349 A KR 19990036349A KR 100330580 B1 KR100330580 B1 KR 100330580B1
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- Prior art keywords
- land
- solder
- flat package
- induction
- way flat
- Prior art date
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- 238000005476 soldering Methods 0.000 title description 13
- 238000000034 method Methods 0.000 title description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 76
- 238000000576 coating method Methods 0.000 claims abstract description 26
- 239000011248 coating agent Substances 0.000 claims abstract description 19
- 230000006698 induction Effects 0.000 claims description 34
- 230000004907 flux Effects 0.000 description 4
- LAXBNTIAOJWAOP-UHFFFAOYSA-N 2-chlorobiphenyl Chemical compound ClC1=CC=CC=C1C1=CC=CC=C1 LAXBNTIAOJWAOP-UHFFFAOYSA-N 0.000 description 3
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 101710149812 Pyruvate carboxylase 1 Proteins 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- XOMKZKJEJBZBJJ-UHFFFAOYSA-N 1,2-dichloro-3-phenylbenzene Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1Cl XOMKZKJEJBZBJJ-UHFFFAOYSA-N 0.000 description 1
- WVHNUGRFECMVLQ-UHFFFAOYSA-N 1,3-dichloro-2-(2,4-dichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC=C1C1=C(Cl)C=CC=C1Cl WVHNUGRFECMVLQ-UHFFFAOYSA-N 0.000 description 1
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Abstract
본 발명은, 사각판면을 가진 4방향 플랫 패키지IC의 4방향을 따라 배치되며 4방향 플랫 패키지IC의 거의 대각선방향을 따른 땜납도포방향에 대해 전방 및 후방에 위치하는 각각 한 쌍의 전방랜드군 및 후방랜드군을 갖는 4방향 플랫 패키지IC 실장용 회로기판 및 그 땜납도포방법에 관한 것이다. 본 회로기판은, 상기 한 쌍의 후방랜드군 사이에 상기 땜납도포방향을 따라 길게 형성되어 상기 후방랜드군으로부터의 잉여 땜납을 수령하는 후방유도랜드를 포함하는 것을 특징으로 한다. 이에 의해, 후방유도랜드 영역에서 발생하는 쇼트나 브릿지를 방지할 수 있게 된다.The present invention provides a pair of front land groups each disposed along four directions of a four-way flat package IC having a square plate surface and positioned forward and rearward with respect to the solder coating direction along a substantially diagonal direction of the four-way flat package IC. A circuit board for mounting a 4-way flat package IC having a rear land group and a solder coating method thereof. The circuit board is characterized in that it comprises a rear guide land which is formed between the pair of rear land groups along the solder coating direction and receives surplus solder from the rear land groups. This makes it possible to prevent shorts and bridges occurring in the rear guided land region.
Description
본 발명은, 본 발명은 4방향 플랫 패키지IC 실장용 회로기판 및 그 땜납도포방법에 관한 것으로서, 보다 상세하게는, 땜납도포시 쇼트를 방지하기 위한 4방향 플랫 패키지IC 실장용 회로기판 및 그 땜납도포방법에 관한 것이다.The present invention relates to a circuit board for mounting a 4-way flat package IC and a solder coating method thereof, and more particularly, to a circuit board for mounting a 4-way flat package IC and a solder thereof to prevent shorting during solder coating. It relates to a coating method.
일반적으로 PCB의 부품실장공정은, PCB의 표면에 표면실장부품(SMD)나 삽입부품(IMD)을 납땜으로 고정하는 작업공정으로, PCB에는 표면실장부품(SMD)나 삽입부품(IMD)중 한 종류만이 실장되거나 표면실장부품과 삽입부품이 혼재 실장되며, 최근에는 표면실장부품과 삽입부품이 혼재 실장되는 경우가 많다.In general, the component mounting process of a PCB is a work process of fixing a surface mount component (SMD) or an insert component (IMD) by soldering to a surface of the PCB, and one of the surface mount component (SMD) and the insert component (IMD) is applied to the PCB. Only the type is mounted or surface-mounted parts and inserts are mixed-mounted, and recently, surface-mounted parts and inserts are often mixed-mounted.
이러한 부품실장공정은, PCB에 부품을 배열하는 단계, 플럭스(flux)를 도포하는 단계, 예열하는 단계, 땜납을 도포하는 단계, PCB를 냉각하는 단계로 구분할 수 있다.The component mounting process may be divided into arranging components on a PCB, applying flux, preheating, applying solder, and cooling the PCB.
한편, PCB에는 표면실장부품이 배치되는 위치에는 단자에 대응하는 랜드가 형성되어 있고, 삽입부품이 배치되는 위치에는 단자에 대응하는 홀이 형성되어 있으며, PCB에 부품을 배열시 표면실장부품은 칩본드의 도포에 의해 실장위치에 배치되고, 삽입부품은 홀에 단자를 관통시켜 배치된다.On the other hand, a land corresponding to the terminal is formed at the position where the surface mounting component is disposed on the PCB, and a hole corresponding to the terminal is formed at the position where the insertion component is disposed, and the surface mounting component is a chip when arranging the components on the PCB. It is arrange | positioned at a mounting position by application | coating of a bond, and an insertion part is arrange | positioned through the terminal through a hole.
이렇게 표면실장부품이나 삽입부품이 배치된 PCB에는 플럭스를 도포하며, 플럭스는 이소프로필 알코올과 송진(rosin)을 주성분으로 하는 여러 가지 화학물질들로 이루어져 PCB 상의 접합부를 세정하여 금속의 산화를 방지하고 땜납의 도포시 표면장력을 감소시키게 된다. 플럭스가 도포된 PCB는, 납땜공정시 갑작스런 온도상승으로 PCB가 휘는 것을 방지하기 위해 예열과정을 거친 다음, 땜납을 도포하는 솔더링 단계로 돌입하게 된다.Flux is applied to the PCB on which surface-mount components or inserts are placed. Flux is composed of various chemicals whose main components are isopropyl alcohol and rosin, and prevents oxidation of metal by cleaning the joints on the PCB. The application of solder reduces surface tension. The flux-coated PCB is preheated to prevent bending of the PCB due to sudden temperature rise during the soldering process, and then enters the soldering step of applying solder.
솔더링 단계에서, 표면실장부품의 실장시에는 리플로우(reflow) 솔더링 방법이 사용되고, 삽입부품의 실장시에는 플로우(flow) 솔더링 방법이 사용되며, 표면실장부품과 삽입부품이 혼재 실장된 경우에는 플로우 솔더링 방법이 주로 사용된다. 플로우 솔더링방법은, PCB를 납이 분사되는 납조를 통과시켜 표면실장부품과 삽입부품의 단자에 납땜이 이루어지도록 하는 방법으로 표면실장부품 경우 플로우 솔더링에 의해 땜납이 랜드에 부착된다.In the soldering step, a reflow soldering method is used for mounting the surface mount component, a flow soldering method is used for mounting the insert, and in the case where the surface mount component and the insert are mixed Soldering method is mainly used. In the flow soldering method, the solder is attached to the land by the flow soldering in the case of the surface mounting component in such a way that the PCB is soldered to the terminals of the surface mounting component and the insert component by passing the lead bath through which lead is injected.
이러한 표면실장부품중 QFP(Quad Flat Package) IC는 4방향 플랫 패키지IC라고도 하며, 정사각형이나 직사각형의 패키지를 가지고, 패키지의 네변 모두 리드가 형성되어 있다.Among these surface mount components, QFP (Quad Flat Package) IC is also called a 4-way flat package IC, and has a square or rectangular package, and leads are formed on all four sides of the package.
이러한 4방향 플랫 패키지IC는 PCB의 땜납도포방향을 따라 대각선 방향으로 거의 45。회전된 상태로 배치되며, PCB(51) 상에는, 도 3에 도시된 바와 같은 랜드가 형성되어 있다. 여기서, 화살표는 땜납도포방향을 표시한다.The four-way flat package IC is disposed in a state of being rotated almost 45 DEG in a diagonal direction along the solder coating direction of the PCB. On the PCB 51, lands as shown in Fig. 3 are formed. Here, the arrow indicates the solder coating direction.
4방향 플랫 패키지IC(55)의 랜드는, 땜납도포방향을 따라 전방에 위치하는 두 변에 형성된 각 리드에 해당하는 랜드들의 집합인 한 쌍의 전방랜드군(57)과, 땜납도포방향의 후방에 위치하는 한 쌍의 후방랜드군(59)을 포함한다. 그리고, 한 쌍의 전방랜드군(57) 사이인 선단부에는 땜납을 유도하는 전방유도랜드(58)가 형성되어 있으며, 전방유도랜드(58)는 중앙영역이 땜납도포방향을 따라 구획되어 한 쌍의 랜드부분으로 이루어져 한 쌍의 전방랜드군(57)으로 각각 땜납을 유도하게 된다.The land of the four-way flat package IC 55 is a pair of front land groups 57 which are sets of lands corresponding to each lead formed on two sides located forward along the solder coating direction, and the rear of the solder coating direction. It includes a pair of rear land group 59 located in. In addition, a front induction land 58 for inducing solder is formed at the tip portion between the pair of front land groups 57, and the front induction land 58 has a central area partitioned along the solder coating direction. Consists of a land portion to guide the solder to the pair of front land group 57, respectively.
그리고, 각 전방랜드군(57)과 후방랜드군(59) 사이의 절곡부위에는 전방랜드군(57)을 따라 유동한 땜납을 후방랜드군(59)으로 유도하기 위한 한 쌍의 측방유도랜드(60)가 형성되어 있으며, 이 측방유도랜드(60)는 그 폭이 전방랜드군(57) 및 후방랜드군(59)의 랜드폭과 동일하고, 절곡방향을 따라 완만하게 만곡된 부채꼴 형상으로 형성되어 있다. 또한, 각 후방랜드군(59)의 사이에는 후방랜드군(59)을 따라 유동된 땜납의 잔여분을 수용하는 후방유도랜드(65)가 형성되어 있고, 이 후방유도랜드(65)는 후방랜드군(59)의 말단부에 형성된 랜드들이 잔여분의 땜납으로 인해 쇼트나 브릿지가 발생하는 것을 방지하게 된다.Then, at the bent portion between the front land group 57 and the rear land group 59, a pair of side guide lands for guiding solder flowing along the front land group 57 to the rear land group 59 ( 60 is formed, and the side induction land 60 has a width equal to the land width of the front land group 57 and the rear land group 59, and is formed in a fan shape gently curved along the bending direction. It is. In addition, a rear guide land 65 is formed between each rear land group 59 to accommodate the remaining portion of the solder flowing along the rear land group 59, and the rear guide land 65 is a rear land group. Lands formed at the distal end of 59 prevent the short or bridge from occurring due to the residual solder.
그런데, 이러한 4방향 플랫 패키지IC(55)의 후방유도랜드(65)는, 잔여분의 땜납을 수용하여 후방랜드군(59)의 쇼트를 방지하기 위한 것이나, 이 땜납이 역류하여 오히려 후방랜드군(59) 말단부의 랜드들이 쇼트가 발생한다는 문제점이 있다.By the way, the rear induction land 65 of the four-way flat package IC 55 is for accommodating the remaining solder to prevent the short of the rear land group 59, but this solder flows backwards, and thus the rear land group ( 59) There is a problem that the lands at the distal ends are short-circuited.
한편, 전방유도랜드(58)는 각 전방랜드군(57)으로 땜납을 유도하기 위해 형성되어 있으나, 땜납의 진행시 오히려 전방유도랜드(58)의 면적이 넓어 표면장력에 의해 땜납이 뭉쳐 전방랜드군(57)의 땜납진행방향 입구측에 있는 랜드들이 쇼트가 발생하게 된다.On the other hand, the front induction land 58 is formed to induce solder to each of the front land group 57, but rather the area of the front induction land 58 when the solder proceeds, so that the solder is agglomerated by the surface tension The lands on the inlet side of the group 57 in the soldering direction are short-circuited.
따라서 본 발명의 목적은, 후방유도랜드에 의한 후방랜드군의 쇼트를 방지할 수 있도록 하는 4방향 플랫 패키지IC 실장용 회로기판 및 그 땜납도포방법을 제공하는 것이다.It is therefore an object of the present invention to provide a circuit board for mounting a four-way flat package IC and a solder coating method thereof, which can prevent a short of the rear land group caused by the rear guide land.
도 1은 본 발명의 일 실시예에 따른 회로기판의 평면도,1 is a plan view of a circuit board according to an embodiment of the present invention;
도 2는 도 1의 Ⅱ-Ⅱ선에 따른 측단면도,2 is a side cross-sectional view taken along line II-II of FIG. 1;
도 3은 종래의 회로기판의 평면도이다.3 is a plan view of a conventional circuit board.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 : PCB 5 : 4방향 플랫 패키지IC1: PCB 5: 4-way flat package IC
7 : 전방랜드군 9 : 후방랜드군7: Forward Land Force 9: Rear Land Force
10 : 측방유도랜드 15 : 후방유도랜드10: side induction land 15: rear induction land
16 : 유도부 17 : 연결부16: guide portion 17: connection portion
18 : 도피부18: skin
상기 목적은, 본 발명에 따라, 사각판면을 가진 4방향 플랫 패키지IC의 4방향을 따라 배치되며 4방향 플랫 패키지IC의 거의 대각선방향을 따른 땜납도포방향에 대해 전방 및 후방에 위치하는 각각 한 쌍의 전방랜드군 및 후방랜드군을 갖는 4방향 플랫 패키지IC 실장용 회로기판에 있어서, 상기 한 쌍의 후방랜드군 사이에상기 땜납도포방향을 따라 길게 형성되어 상기 후방랜드군으로부터의 잉여 땜납을 수령하는 후방유도랜드를 포함하는 것을 특징으로 하는 회로기판에 의해 달성된다.The above object is, in accordance with the present invention, a pair disposed along the four directions of the four-way flat package IC having a square plate surface and positioned forward and rearward with respect to the solder coating direction along the substantially diagonal direction of the four-way flat package IC. A circuit board for mounting a four-way flat package IC having a front land group and a rear land group, wherein a length is formed between the pair of rear land groups along the solder coating direction to receive surplus solder from the rear land group. It is achieved by a circuit board comprising a rear guide land.
여기서, 상기 후방유도랜드는 상기 후방랜드군에 인접하게 형성되어 땜납을 유도하는 유도부와, 상기 유도부에 의해 유도된 땜납을 흡입하는 물방울 형상의 도피부와, 상기 유도부와 도피부를 연결하며 상기 유도부 및 상기 도피부보다 좁은 폭을 가지는 연결부를 포함함으로써, 잔여의 땜납을 흡입하여 수용하게 된다.Here, the rear induction land is formed adjacent to the rear land group to guide the solder, the water droplet-shaped escape portion to suck the solder guided by the induction portion, and the induction portion and connecting the induction portion and By including the connecting portion having a narrower width than the escape portion, the remaining solder is sucked in and received.
한편, 상기 목적은, 본 발명의 다른 분야에 따르면, 사각판면을 가진 4방향 플랫 패키지IC의 4방향을 따라 배치되며 4개의 랜드군을 갖는 4방향 플랫 패키지IC의 실장용 회로기판의 땜납도포방법에 있어서, 상기 한 쌍의 후방랜드군 사이에 상기 땜납도포방향을 따라 길게 형성되어 상기 후방랜드군으로부터의 잉여 땜납을 수령하는 후방유도랜드를 마련하는 단계와; 상기 회로기판을 상기 전방랜드군에서 상기 후방랜드군를 연결하는 대각선 방향을 따라 땜납조에 통과시켜 땜납을 도포하는 단계를 포함하는 것을 특징으로 하는 회로기판의 땜납도포방법에 의해서도 달성될 수 있다.On the other hand, the above object, according to another field of the present invention, the solder coating method of the circuit board for mounting the four-way flat package IC having four land groups and arranged along the four directions of the four-way flat package IC having a rectangular plate surface Providing a rear guide land formed between the pair of rear land groups in the solder coating direction to receive excess solder from the rear land groups; It can also be achieved by the solder coating method of the circuit board comprising the step of applying the solder by passing the circuit board through the solder tank along the diagonal direction connecting the rear land group in the front land group.
이하, 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the drawings.
도 1은 4방향 플랫 패키지IC의 실장을 위한 랜드가 형성된 PCB의 평면도이다. 4방향 플랫 패키지IC(5)는 땜납도포방향을 따라 대각선 방향으로 거의 45。회전된 상태로 배치되게 되며, 이에 따라, PCB(1) 상에는 4방향 플랫 패키지IC(5)에 대응하는 랜드가 형성되어 있다. 여기서, 화살표는 땜납도포방향을 표시한다.1 is a plan view of a PCB on which lands for mounting a four-way flat package IC are formed. The four-way flat package IC 5 is disposed to be rotated almost 45 ° in a diagonal direction along the solder coating direction. Thus, lands corresponding to the four-way flat package IC 5 are formed on the PCB 1. It is. Here, the arrow indicates the solder coating direction.
4방향 플랫 패키지IC(5)의 랜드는, 땜납도포방향을 따라 전방에 위치하는 두변에 형성된 각 리드에 해당하는 랜드들의 집합인 한 쌍의 전방랜드군(7)과, 땜납도포방향의 후방에 위치하는 한 쌍의 후방랜드군(9)을 포함한다.The land of the four-way flat package IC 5 is a pair of front land groups 7 which are sets of lands corresponding to the leads formed on two sides located forward along the solder coating direction, and at the rear of the solder coating direction. It includes a pair of rear land group (9) located.
여기서, 각 전방랜드군(7)과 후방랜드군(9) 사이의 절곡부위에는 전방랜드군(7)을 따라 유동한 땜납을 후방랜드군(9)으로 유도하기 위한 한 쌍의 측방유도랜드(10)가 형성되어 있으며, 이 측방유도랜드(10)는 그 폭이 전방랜드군(7) 및 후방랜드군(9)의 랜드폭과 동일하고, 절곡방향을 따라 완만하게 만곡된 부채꼴 형상으로 형성되어 있다.Here, at the bent portion between the front land group 7 and the rear land group 9, a pair of lateral induction lands for guiding solder flowing along the front land group 7 to the rear land group 9 ( 10) is formed, the lateral induction land 10 is the same width as the land width of the front land group (7) and the rear land group (9), formed in a fan shape gently curved along the bending direction. It is.
한편, 각 후방랜드군(9)의 사이에는 후방랜드군(9)을 따라 유동된 땜납의 잔여분을 수용하는 후방유도랜드(15)가 형성되어 있으며, 이 후방유도랜드(15)는 각 후방랜드군(9) 사이에 형성되어 땜납을 유도하는 유도부(16)와, 유도부(16)에 의해 유도된 땜납을 흡입하는 물방울 형상의 도피부(18)와, 유도부(16)와 도피부(18)를 연결하여 유도부(16)로부터의 땜납이 도피부(18)로 흡입되도록 하는 연결부(17)로 형성된다. 여기서, 연결부(17)와 유도부(16)의 가로폭의 비는 1:3정도로 보다 그 폭이 좁게 형성되며, 도피부(18)는 그 말단부가 땜납진행방향으로 갈수록 폭이 급격히 좁아지는 물방울형상으로 형성된다.On the other hand, a rear guide land 15 is formed between the rear land groups 9 to accommodate the residual amount of solder flowing along the rear land group 9, and the rear guide lands 15 are each rear lands. An induction part 16 formed between the groups 9 to induce solder, a water droplet-shaped skin part 18 to suck the solder guided by the induction part 16, and an induction part 16 and the skin part 18; Is formed as a connection portion 17 to allow solder from the induction portion 16 to be sucked into the escape portion 18. Here, the ratio of the width of the connecting portion 17 and the induction portion 16 is about 1: 3 narrower than the width is formed, the escape portion 18 is a droplet shape that the width of the end portion is sharply narrowed toward the solder progress direction Is formed.
이러한 구성에 의하여, 플로우 솔더링방법에 의한 땜납도포시, 땜납이 납땜진행방향으로 진행하여 4방향 플랫 패키지IC(5)의 선단부에 도달하면, 땜납이 양 전방랜드군(7)을 따라 이동하여 각 랜드에 땜납이 도포된다. 그리고, 4방향 플랫 패키지IC(5)의 측방을 따라 흐르던 땜납은 측방유도랜드(10)에 의해 그 흐름방향이 전환되어 후방랜드군(9)으로 안내된다. 이렇게 양 후방랜드군(9)으로 안내되어 유동된 땜납은 후방유도랜드(15)의 유도부(16)에서 합쳐져 연결부(17)를 지나면서 그 흐름이 단절되면서 잔여분의 땜납은 도피부(18)에 수용되며, 연결부(17)에 의해 도피부(18)로부터의 땜납이 유도부(16)로 역류되는 것이 방지된다. 이러한 후방유도랜드(15)를 도 2에 도시된 바와 같이, 측면에서 보면, 유도부(16)와 연결부(17)에는 땜납의 양이 적고, 도피부(18)에 잔여분의 땜납이 모이는 것을 알 수 있다.With this configuration, when solder is applied by the flow soldering method, when the solder proceeds in the soldering progress direction and reaches the tip of the four-way flat package IC 5, the solder moves along both front land groups 7 Solder is applied to the lands. The solder flowing along the side of the four-way flat package IC 5 is switched by the side induction lands 10 to be guided to the rear land group 9. The solder guided and flowed to both rear land groups 9 thus merges in the induction part 16 of the rear induction land 15 and passes through the connection part 17, and the flow thereof is cut off while the remaining solder is transferred to the escape part 18. And the solder 17 from the escape portion 18 is prevented from flowing back into the induction portion 16 by the connecting portion 17. As shown in FIG. 2, when the rear guide land 15 is viewed from the side, it is understood that the amount of solder is small in the induction part 16 and the connection part 17, and the residual solder is collected in the escape part 18. have.
한편, 4방향 플랫 패키지IC(5)의 땜납진행방향의 후방부에 PCB(1)의 패턴으로 인해 후방유도랜드(15)를 형성할 만한 여유 공간이 없을 경우에는, PCB(1)에 형성된 패턴의 솔더 레지스터를 일부 제거하여 후방유도랜드(15)를 형성하면 된다.On the other hand, when there is no free space for forming the rear guide land 15 due to the pattern of the PCB 1 at the rear portion in the solder progress direction of the 4-way flat package IC 5, the pattern formed on the PCB 1 Some solder resistors may be removed to form rear induction lands 15.
이와 같이, 본 발명에서는 각 후방랜드군(9) 사이에는 물방울 형상의 후방유도랜드(15)를 형성함으로써, 후방유도랜드(15)의 도피부(18)에서는 잔여분의 땜납을 수용하고 연결부(17)에서는 땜납의 역류를 방지하여 종래에 후방랜드군(9)의 말단부에서 땜납의 뭉침으로 인해 발생하던 쇼트나 브릿지를 방지할 수 있다.As described above, in the present invention, by forming the water droplet-shaped rear induction land 15 between the rear land groups 9, the escape portion 18 of the rear induction land 15 receives the remaining solder and connects the connection 17. ), Backflow of the solder can be prevented to prevent shorts or bridges that have conventionally been caused by agglomeration of the solder at the distal end of the rear land group 9.
한편, 본 발명에서는 전방유도랜드를 삭제함으로써, 전방랜드군(7)의 땜납진행방향 입구측에 있는 랜드들의 쇼트를 방지할 수 있게 된다.On the other hand, in the present invention, by eliminating the front induction land, it is possible to prevent the short of the lands on the inlet side of the solder progress direction of the front land group 7.
이상에서 설명한 바와 같이, 본 발명에 따르면, 후방유도랜드에 의해 후방랜드군 영역에 발생하던 쇼트나 브릿지를 방지할 수 있게 된다.As described above, according to the present invention, it is possible to prevent shorts and bridges generated in the rear land group region by the rear guide land.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990036349A KR100330580B1 (en) | 1999-08-30 | 1999-08-30 | Quad flat package ic mounted pcb and soldering method thereof |
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| KR1019990036349A KR100330580B1 (en) | 1999-08-30 | 1999-08-30 | Quad flat package ic mounted pcb and soldering method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07106744A (en) * | 1993-09-30 | 1995-04-21 | Sony Corp | Land for solder dip of four-way-lead flat package ic and dip soldering method |
| JPH07115261A (en) * | 1993-10-15 | 1995-05-02 | Toyota Motor Corp | Printed wiring board and its soldering |
| KR950024627A (en) * | 1994-01-17 | 1995-08-21 | 김광호 | Soldering Land Patterns on Printed Circuit Boards |
| JPH09181435A (en) * | 1995-12-27 | 1997-07-11 | Sharp Corp | Printed wiring board |
| JPH10163582A (en) * | 1996-11-27 | 1998-06-19 | Matsushita Electric Ind Co Ltd | Printed board for reflow soldering |
-
1999
- 1999-08-30 KR KR1019990036349A patent/KR100330580B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07106744A (en) * | 1993-09-30 | 1995-04-21 | Sony Corp | Land for solder dip of four-way-lead flat package ic and dip soldering method |
| JPH07115261A (en) * | 1993-10-15 | 1995-05-02 | Toyota Motor Corp | Printed wiring board and its soldering |
| KR950024627A (en) * | 1994-01-17 | 1995-08-21 | 김광호 | Soldering Land Patterns on Printed Circuit Boards |
| JPH09181435A (en) * | 1995-12-27 | 1997-07-11 | Sharp Corp | Printed wiring board |
| JPH10163582A (en) * | 1996-11-27 | 1998-06-19 | Matsushita Electric Ind Co Ltd | Printed board for reflow soldering |
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