KR100322887B1 - 반도체장치의 다층 금속배선 형성방법 - Google Patents
반도체장치의 다층 금속배선 형성방법 Download PDFInfo
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- KR100322887B1 KR100322887B1 KR1019990059874A KR19990059874A KR100322887B1 KR 100322887 B1 KR100322887 B1 KR 100322887B1 KR 1019990059874 A KR1019990059874 A KR 1019990059874A KR 19990059874 A KR19990059874 A KR 19990059874A KR 100322887 B1 KR100322887 B1 KR 100322887B1
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- South Korea
- Prior art keywords
- photoresist
- film
- interlayer insulating
- forming
- wiring
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 57
- 239000011229 interlayer Substances 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000000059 patterning Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000001465 metallisation Methods 0.000 claims abstract 2
- 239000010410 layer Substances 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 10
- 230000003667 anti-reflective effect Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (4)
- 반도체장치의 다층 배선 제조 방법에 있어서,반도체 기판의 구조물에 하부 금속배선을 형성하는 단계;상기 하부 금속 배선이 형성된 기판 전면에 평탄화된 층간 절연막을 형성하는 단계;상기 기판 상부에 제 1감광막 패턴을 형성하는 단계;상기 제 1감광막 패턴이 형성된 결과물 상부에 유기성 반사방지막을 증착하고, 상기 제 1감광막 패턴 표면이 들러날때까지 전면 식각하는 단계;상기 결과물 전면에 제 2감광막을 증착하고 경화한 후에 제 2 및 제 1감광막을 패터닝하는 단계;상기 감광막 패턴과 유기성 반사방지막을 마스크로 삼아 식각 공정을 진행하여 상기 층간 절연막내에 비아 및 상부 배선용 트렌치를 동시에 형성하는 단계; 및상기 비아 및 상부 배선용 트렌치가 형성된 층간 절연막에 금속을 매립하고 이를 연마하여 하부 금속배선과 연결되는 플러그 및 상부 배선을 동시에 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 다층 금속배선 형성방법.
- 제 1항에 있어서, 상기 제 1감광막 패턴의 두께는 (비아 깊이)×(층간 절연막을 식각하는 공정에서 유기성 반사방지막의 식각 속도)÷(층간 절연막을 식각하는 공정에서 층간 절연막의 식각 속도)인 것을 특징으로 하는 반도체장치의 다층 금속배선 형성방법.
- 제 1항에 있어서, 상기 유기성 반사방지막의 전면 식각 공정시 플라즈마 식각 공정을 이용하는 것을 특징으로 하는 반도체장치의 다층 금속배선 형성방법.
- 제 1항에 있어서, 상기 제 2감광막 패턴과 유기성 반사방지막을 마스크로 삼아 식각 공정을 진행할 때 CxFy를 활성화시킨 플라즈마 식각 공정을 이용하는 것을 특징으로 하는 반도체장치의 다층 금속배선 형성방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990059874A KR100322887B1 (ko) | 1999-12-21 | 1999-12-21 | 반도체장치의 다층 금속배선 형성방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990059874A KR100322887B1 (ko) | 1999-12-21 | 1999-12-21 | 반도체장치의 다층 금속배선 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010063036A KR20010063036A (ko) | 2001-07-09 |
KR100322887B1 true KR100322887B1 (ko) | 2002-02-08 |
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KR1019990059874A KR100322887B1 (ko) | 1999-12-21 | 1999-12-21 | 반도체장치의 다층 금속배선 형성방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100322887B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101081851B1 (ko) | 2004-01-09 | 2011-11-09 | 매그나칩 반도체 유한회사 | 반도체 소자의 듀얼 다마신 패턴 형성 방법 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100942698B1 (ko) * | 2007-12-07 | 2010-02-16 | 한국전자통신연구원 | 다층의 금속 배선 제조 방법 |
-
1999
- 1999-12-21 KR KR1019990059874A patent/KR100322887B1/ko active IP Right Grant
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101081851B1 (ko) | 2004-01-09 | 2011-11-09 | 매그나칩 반도체 유한회사 | 반도체 소자의 듀얼 다마신 패턴 형성 방법 |
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Publication number | Publication date |
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KR20010063036A (ko) | 2001-07-09 |
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