KR100317517B1 - 복수의에이전트에의한공유메모리로의동시액세스를제공하는방법및장치 - Google Patents

복수의에이전트에의한공유메모리로의동시액세스를제공하는방법및장치 Download PDF

Info

Publication number
KR100317517B1
KR100317517B1 KR1019980710671A KR19980710671A KR100317517B1 KR 100317517 B1 KR100317517 B1 KR 100317517B1 KR 1019980710671 A KR1019980710671 A KR 1019980710671A KR 19980710671 A KR19980710671 A KR 19980710671A KR 100317517 B1 KR100317517 B1 KR 100317517B1
Authority
KR
South Korea
Prior art keywords
memory
agent
access
shared
memory portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980710671A
Other languages
English (en)
Korean (ko)
Other versions
KR20000022251A (ko
Inventor
머니시 뮤탈
닐레시 브이. 샤
쿨지트 베인스
Original Assignee
피터 엔. 데트킨
인텔 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 피터 엔. 데트킨, 인텔 코오퍼레이션 filed Critical 피터 엔. 데트킨
Publication of KR20000022251A publication Critical patent/KR20000022251A/ko
Application granted granted Critical
Publication of KR100317517B1 publication Critical patent/KR100317517B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Dram (AREA)
KR1019980710671A 1996-06-27 1997-06-13 복수의에이전트에의한공유메모리로의동시액세스를제공하는방법및장치 Expired - Fee Related KR100317517B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/672,099 US5815167A (en) 1996-06-27 1996-06-27 Method and apparatus for providing concurrent access by a plurality of agents to a shared memory
US08/672,099 1996-06-27
US8/672,099 1996-06-27
PCT/US1997/010447 WO1997050042A1 (en) 1996-06-27 1997-06-13 A method and apparatus for providing concurrent access by a plur ality of agents to a shared memory

Publications (2)

Publication Number Publication Date
KR20000022251A KR20000022251A (ko) 2000-04-25
KR100317517B1 true KR100317517B1 (ko) 2002-02-19

Family

ID=24697142

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980710671A Expired - Fee Related KR100317517B1 (ko) 1996-06-27 1997-06-13 복수의에이전트에의한공유메모리로의동시액세스를제공하는방법및장치

Country Status (8)

Country Link
US (1) US5815167A (enExample)
EP (1) EP0972251B1 (enExample)
JP (1) JP3976342B2 (enExample)
KR (1) KR100317517B1 (enExample)
AU (1) AU3397697A (enExample)
DE (1) DE69724463T2 (enExample)
TW (1) TW358180B (enExample)
WO (1) WO1997050042A1 (enExample)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6058459A (en) * 1996-08-26 2000-05-02 Stmicroelectronics, Inc. Video/audio decompression/compression device including an arbiter and method for accessing a shared memory
TW360823B (en) * 1996-09-30 1999-06-11 Hitachi Ltd Data processor and graphic processor
US5941968A (en) * 1997-04-14 1999-08-24 Advanced Micro Devices, Inc. Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
US6249853B1 (en) 1997-06-25 2001-06-19 Micron Electronics, Inc. GART and PTES defined by configuration registers
US6282625B1 (en) 1997-06-25 2001-08-28 Micron Electronics, Inc. GART and PTES defined by configuration registers
US6118462A (en) 1997-07-01 2000-09-12 Memtrax Llc Computer system controller having internal memory and external memory control
US6057862A (en) * 1997-07-01 2000-05-02 Memtrax Llc Computer system having a common display memory and main memory
JPH11120156A (ja) * 1997-10-17 1999-04-30 Nec Corp マルチプロセッサシステムにおけるデータ通信方式
US6965974B1 (en) * 1997-11-14 2005-11-15 Agere Systems Inc. Dynamic partitioning of memory banks among multiple agents
US6091431A (en) * 1997-12-18 2000-07-18 Intel Corporation Method and apparatus for improving processor to graphics device local memory performance
US6252612B1 (en) * 1997-12-30 2001-06-26 Micron Electronics, Inc. Accelerated graphics port for multiple memory controller computer system
US7071946B2 (en) * 1997-12-30 2006-07-04 Micron Technology, Inc. Accelerated graphics port for a multiple memory controller computer system
US6157398A (en) * 1997-12-30 2000-12-05 Micron Technology, Inc. Method of implementing an accelerated graphics port for a multiple memory controller computer system
US6272584B1 (en) * 1998-09-10 2001-08-07 Compaq Computer Corporation System board with consolidated EEPROM module
WO2000052564A2 (en) * 1999-03-05 2000-09-08 Amulet Technologies, Llc Graphical user interface engine for embedded systems
US6601147B1 (en) * 1999-03-31 2003-07-29 International Business Machines Corporation Computer system and method for maintaining an integrated shared buffer memory in a group of interconnected hosts
EP1059586B1 (en) * 1999-06-09 2004-09-08 Texas Instruments Incorporated Shared memory with programmable size
US6469703B1 (en) * 1999-07-02 2002-10-22 Ati International Srl System of accessing data in a graphics system and method thereof
US6526462B1 (en) * 1999-11-19 2003-02-25 Hammam Elabd Programmable multi-tasking memory management system
US6774903B1 (en) * 2000-11-06 2004-08-10 Ati International Srl Palette anti-sparkle enhancement
US7205993B2 (en) * 2001-02-15 2007-04-17 Sony Corporation Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation
US6828977B2 (en) * 2001-02-15 2004-12-07 Sony Corporation Dynamic buffer pages
US6831649B2 (en) * 2001-02-15 2004-12-14 Sony Corporation Two-dimensional buffer pages using state addressing
US6765579B2 (en) * 2001-02-15 2004-07-20 Sony Corporation Pixel pages using combined addressing
US6992674B2 (en) * 2001-02-15 2006-01-31 Sony Corporation Checkerboard buffer using two-dimensional buffer pages and using state addressing
US6831651B2 (en) * 2001-02-15 2004-12-14 Sony Corporation Checkerboard buffer
US6801204B2 (en) * 2001-02-15 2004-10-05 Sony Corporation, A Japanese Corporation Checkerboard buffer using memory blocks
US6795079B2 (en) * 2001-02-15 2004-09-21 Sony Corporation Two-dimensional buffer pages
US6831650B2 (en) * 2001-02-15 2004-12-14 Sony Corporation Checkerboard buffer using sequential memory locations
US6803917B2 (en) * 2001-02-15 2004-10-12 Sony Corporation Checkerboard buffer using memory bank alternation
US6765580B2 (en) * 2001-02-15 2004-07-20 Sony Corporation Pixel pages optimized for GLV
US7038691B2 (en) * 2001-02-15 2006-05-02 Sony Corporation Two-dimensional buffer pages using memory bank alternation
US6850241B2 (en) * 2001-02-15 2005-02-01 Sony Corporation Swapped pixel pages
US7088369B2 (en) * 2001-02-15 2006-08-08 Sony Corporation Checkerboard buffer using two-dimensional buffer pages and using bit-field addressing
US6791557B2 (en) * 2001-02-15 2004-09-14 Sony Corporation Two-dimensional buffer pages using bit-field addressing
US7379069B2 (en) * 2001-02-15 2008-05-27 Sony Corporation Checkerboard buffer using two-dimensional buffer pages
US6768490B2 (en) * 2001-02-15 2004-07-27 Sony Corporation Checkerboard buffer using more than two memory devices
US6622203B2 (en) * 2001-05-29 2003-09-16 Agilent Technologies, Inc. Embedded memory access method and system for application specific integrated circuits
JP2003177958A (ja) * 2001-06-11 2003-06-27 Emblaze Semiconductor Ltd 特殊メモリデバイス
US20030058368A1 (en) * 2001-09-24 2003-03-27 Mark Champion Image warping using pixel pages
US6965980B2 (en) * 2002-02-14 2005-11-15 Sony Corporation Multi-sequence burst accessing for SDRAM
US6959355B2 (en) * 2003-02-24 2005-10-25 Standard Microsystems Corporation Universal serial bus hub with shared high speed handler
US7185126B2 (en) * 2003-02-24 2007-02-27 Standard Microsystems Corporation Universal serial bus hub with shared transaction translator memory
US6874042B2 (en) * 2003-03-11 2005-03-29 Dell Products L.P. System and method for using a switch to route peripheral and graphics data on an interconnect
JP2005165592A (ja) * 2003-12-02 2005-06-23 Matsushita Electric Ind Co Ltd データ転送装置
JP2005222245A (ja) * 2004-02-04 2005-08-18 Renasas Northern Japan Semiconductor Inc プロセッサ
JP4500610B2 (ja) * 2004-07-07 2010-07-14 キヤノン株式会社 映像信号処理装置、メモリ制御方法、及びプログラム
US20060227759A1 (en) * 2004-09-14 2006-10-12 Bohm Mark R Peripheral Sharing USB Hub
US20060059293A1 (en) * 2004-09-14 2006-03-16 Henry Wurzburg Universal serial bus switching hub
US7433990B2 (en) * 2006-01-24 2008-10-07 Standard Microsystems Corporation Transferring system information via universal serial bus (USB)
US7523243B2 (en) * 2006-04-14 2009-04-21 Standard Microsystems Corporation Multi-host USB device controller
US7480753B2 (en) * 2006-04-27 2009-01-20 Standard Microsystems Corporation Switching upstream and downstream logic between ports in a universal serial bus hub
US20080005262A1 (en) * 2006-06-16 2008-01-03 Henry Wurzburg Peripheral Sharing USB Hub for a Wireless Host
KR100888427B1 (ko) * 2006-09-15 2009-03-11 엠텍비젼 주식회사 공유 메모리를 구비한 디지털 처리 장치 및 데이터 출력방법
US7949815B2 (en) * 2006-09-27 2011-05-24 Intel Corporation Virtual heterogeneous channel for message passing
US20090063717A1 (en) * 2007-08-28 2009-03-05 Bohm Mark R Rate Adaptation for Support of Full-Speed USB Transactions Over a High-Speed USB Interface
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
KR101283482B1 (ko) * 2009-12-11 2013-07-12 한국전자통신연구원 Ｐｃｉ 익스프레스 프로토콜 처리 장치
US8397006B2 (en) * 2010-01-28 2013-03-12 Freescale Semiconductor, Inc. Arbitration scheme for accessing a shared resource
US8799532B2 (en) 2011-07-07 2014-08-05 Smsc Holdings S.A.R.L. High speed USB hub with full speed to high speed transaction translator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156904A (en) * 1976-08-25 1979-05-29 Hitachi, Ltd. Computer systems having a common memory shared between a central processor and a CRT display

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459846A (en) * 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory
US4980828A (en) * 1988-11-25 1990-12-25 Picker International, Inc. Medical imaging system including use of DMA control for selective bit mapping of DRAM and VRAM memories
WO1995015528A1 (en) * 1993-11-30 1995-06-08 Vlsi Technology, Inc. A reallocatable memory subsystem enabling transparent transfer of memory function during upgrade
US5450542A (en) * 1993-11-30 1995-09-12 Vlsi Technology, Inc. Bus interface with graphics and system paths for an integrated memory system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156904A (en) * 1976-08-25 1979-05-29 Hitachi, Ltd. Computer systems having a common memory shared between a central processor and a CRT display

Also Published As

Publication number Publication date
TW358180B (en) 1999-05-11
KR20000022251A (ko) 2000-04-25
DE69724463D1 (de) 2003-10-02
DE69724463T2 (de) 2004-07-08
EP0972251B1 (en) 2003-08-27
JP2001523361A (ja) 2001-11-20
EP0972251A1 (en) 2000-01-19
AU3397697A (en) 1998-01-14
US5815167A (en) 1998-09-29
JP3976342B2 (ja) 2007-09-19
EP0972251A4 (en) 2000-01-19
WO1997050042A1 (en) 1997-12-31

Similar Documents

Publication Publication Date Title
KR100317517B1 (ko) 복수의에이전트에의한공유메모리로의동시액세스를제공하는방법및장치
US5911149A (en) Apparatus and method for implementing a programmable shared memory with dual bus architecture
US7873775B2 (en) Multiple processor system and method including multiple memory hub modules
US5454107A (en) Cache memory support in an integrated memory system
US6076139A (en) Multimedia computer architecture with multi-channel concurrent memory access
USRE36191E (en) Configuration data loopback in a bus bridge circuit
US5450542A (en) Bus interface with graphics and system paths for an integrated memory system
US4782462A (en) Raster scan video controller with programmable prioritized sharing of display memory between update and display processes and programmable memory access termination
US5640519A (en) Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme
US6317813B1 (en) Method for arbitrating multiple memory access requests in a unified memory architecture via a non unified memory controller
US20030177333A1 (en) Bus interface selection by page table attributes
KR100869938B1 (ko) 주문형 집적 회로
US5748203A (en) Computer system architecture that incorporates display memory into system memory
US6434688B1 (en) Method and apparatus for providing and maximizing concurrent operations in a shared memory system which includes display memory
CA2239426A1 (en) Shared memory system
JP2900892B2 (ja) 情報処理装置
KR20060039719A (ko) 시스템 버스 성능 개선을 위한 상호접속 장치
KR100210404B1 (ko) 공유 메모리 억세스 제어장치
JPH07262125A (ja) 情報処理装置
KR19990031220A (ko) 브이.엠.이 버스 시스템에서 브이.엠.이 버스 제어장치
JPH0877072A (ja) キャッシュメモリ装置
JPH10171749A (ja) メモリアクセス制御装置
JPH0287258A (ja) メモリアクセス方式

Legal Events

Date Code Title Description
A201 Request for examination
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20091124

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20101202

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20101202

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000