KR100315017B1 - DRAM device capacitors and manufacturing methods thereof - Google Patents
DRAM device capacitors and manufacturing methods thereof Download PDFInfo
- Publication number
- KR100315017B1 KR100315017B1 KR1019980025782A KR19980025782A KR100315017B1 KR 100315017 B1 KR100315017 B1 KR 100315017B1 KR 1019980025782 A KR1019980025782 A KR 1019980025782A KR 19980025782 A KR19980025782 A KR 19980025782A KR 100315017 B1 KR100315017 B1 KR 100315017B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- dielectric film
- capacitor
- temperature
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 디램 디바이스의 캐패시터 및 그 제조방법에 관한 것으로, 트랜지스터가 구비된 반도체 기판상에 트랜지스터의 접합 영역을 노출시키는 콘택홀이 구비된 층간 절연막을 형성하는 단계와, 상기 노출된 접합 영역과 콘택되도록 층간 절연막 상부에 스토리지 전극을 형성하는 단계와, 상기 스토리지 전극 상에 유전체막으로서, LixTa1-xO3막을 형성하는 단계 및 상기 LixTa1-xO3막 상부에 플레이트 전극을 형성하는 단계를 포함한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a DRAM device and a method of manufacturing the same, comprising the steps of: forming an interlayer insulating film having a contact hole exposing a junction region of a transistor on a semiconductor substrate provided with a transistor; Forming a storage electrode over the interlayer insulating film, forming a Li x Ta 1-x O 3 film as a dielectric film on the storage electrode, and forming a plate electrode over the Li x Ta 1-x O 3 film. Forming a step.
Description
본 발명은 디램 디바이스의 캐패시터 및 그 제조방법에 관한 것으로, 보다 구체적으로는, 캐패시터의 유전체막의 유전율을 증대시켜 캐패시터의 저장 용량을 증대시킬 수 있는 디램 디바이스의 캐패시터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a DRAM device and a method of manufacturing the same, and more particularly, to a capacitor of a DRAM device and a method of manufacturing the same capable of increasing the storage capacity of the capacitor by increasing the dielectric constant of the dielectric film of the capacitor.
일반적으로, 디램 디바이스의 캐패시터는 스토리지 전극과, 플레이트 전극및 그 사이의 유전체막으로 구성된다. 이러한 캐패시터의 용량(이하, 캐패시턴스라 칭함)은 스토리지 전극의 면적 및 유전체막의 유전율에 비례하고, 유전체막의 두께에 반비례한다.Generally, a capacitor of a DRAM device is composed of a storage electrode, a plate electrode and a dielectric film therebetween. The capacitance of the capacitor (hereinafter referred to as capacitance) is proportional to the area of the storage electrode and the dielectric constant of the dielectric film, and inversely proportional to the thickness of the dielectric film.
종래에는 캐패시턴스를 증대시키기 위한 방법으로서, 유전율이 25 정도인 Ta2O5막을 유전체막으로 사용하는 방법이 제안되었다.Conventionally, as a method for increasing capacitance, a method of using a Ta 2 O 5 film having a dielectric constant of about 25 as a dielectric film has been proposed.
즉, 도 1에 도시된 바와 같이, 도핑된 폴리실리콘으로 된 스토리지 전극(1) 상부에 LPCVD(low pressure chemical vapor deposition) 방식으로 유전체막인 TaO5막(2)을 형성한다. 이어 TaO5막(2) 상부에 TiN막(3)을 증착하고, TiN막(3) 상에 도핑된 폴리실리콘으로 된 플레이트 전극(3)을 형성하여, 캐패시터를 형성한다.That is, as illustrated in FIG. 1, a TaO 5 film 2, which is a dielectric film, is formed on the storage electrode 1 made of doped polysilicon by low pressure chemical vapor deposition (LPCVD). Subsequently, a TiN film 3 is deposited on the TaO 5 film 2 and a plate electrode 3 made of polysilicon doped on the TiN film 3 is formed to form a capacitor.
그러나, 상기 종래의 Ta2O5막을 유전체막으로 하는 캐패시터에 있어서는 다음과 같은 문제점이 있다.However, there is the following problem in the capacitor having the conventional Ta 2 O 5 film as a dielectric film.
먼저, 상기 Ta2O5막은 불안정한 화학양론비(stoichiometry)를 갖고 있으므로, TaxOy상태로 존재한다. 이로인하여, TaxOy상태의 막은 Ta과 O의 조성비 차이로 인하여, 치환된 Ta 원자 즉, 베이컨시 원자가 발생된다. 이와같이 베이컨시 원자가 발생되면, 베이컨시 원자의 결합력을 증대시키면서, 안정한 화학양론비를 갖도록 별도의 안정화 공정을 실시하여야 한다.First, since the Ta 2 O 5 film has an unstable stoichiometry, it is present in a Ta x O y state. As a result, in the Ta x O y state, due to the difference in composition ratios of Ta and O, substituted Ta atoms, that is, vacancy atoms, are generated. In this way, when vacancy atoms are generated, an additional stabilization process must be performed to increase the binding force of vacancy atoms and to have a stable stoichiometric ratio.
또한, Ta2O5막의 원료원인 Ta(OC2H5)5의 유기물과 O2또는 NO2가스의 반응으로 인하여, Ta2O5막내에 불순물인 탄소 원자(C)와 탄소 화합물(CH4) 및 수분들이 존재하게 된다.In addition, due to the reaction of O 2 or NO 2 gas with an organic material of Ta (OC 2 H 5 ) 5, which is a raw material of the Ta 2 O 5 film, a carbon atom (C) and a carbon compound (CH 4 ) as impurities in the Ta 2 O 5 film ) And moisture.
이와같이, Ta2O5막내에 Ta 원자, 불순물로 존재하는 탄소 이온과 라디칼이 존재함에 따라, 막내의 누설 전류가 증대되고, 유전 특성이 저하되어, 캐패시터의 유전체막으로 사용하기 어렵다.As described above, due to the presence of carbon atoms and radicals present as Ta atoms and impurities in the Ta 2 O 5 film, leakage current in the film is increased, dielectric properties are degraded, and it is difficult to use the dielectric film of the capacitor.
따라서, 본 발명의 목적은 유전율이 높으면서도 막내에 누설전류가 발생되지 않고, 캐패시턴스를 증대시킬 수 있음은 물론 별도의 안정화 공정없이도 안정한 상태를 가지는 유전체막을 이용한 디램 디바이스의 캐패시터 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a DRAM device using a dielectric film having a high dielectric constant and no leakage current in the film, increasing capacitance, and having a stable state without a separate stabilization process. .
도 1은 종래의 디램 디바이스의 캐패시터 전극을 개략적으로 나타낸 단면도.1 is a cross-sectional view schematically showing a capacitor electrode of a conventional DRAM device.
도 2a 내지 도 2c는 본 발명에 따른 디램 디바이스의 캐패시터 제조방법을 설명하기 위한 공정 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a DRAM device according to the present invention.
도 3은 본 발명에 따른 유전체막의 결정 구조를 나타낸 도면.3 is a view showing a crystal structure of a dielectric film according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
10 : 반도체 기판 10a : 접합 영역10 semiconductor substrate 10a junction region
11 : 층간 절연막 12 : 스토리지 전극11 interlayer insulation film 12 storage electrode
13 : 질산화막 14 : LixTa1-xO3막으로 된 유전체막13: nitric oxide film 14: dielectric film of Li x Ta 1-x O 3 film
15: TiN막 16 : 플레이트 전극15: TiN film 16: plate electrode
상기한 본 발명의 목적을 달성하기 위한 본 발명의 따른 디램 디바이스의 캐패시터 제조방법은, 트랜지스터가 구비된 반도체 기판상에 트랜지스터의 접합 영역을 노출시키는 콘택홀이 구비된 층간 절연막을 형성하는 단계와, 상기 노출된 접합 영역과 콘택되도록 층간 절연막 상부에 폴리실리콘층으로 이루어진 스토리지노드전극을 형성하는 단계와, 상기 스토리지노드전극을 플라즈마 또는 RTN(rapid thermal nitridation) 처리에 의한 1차 아닐링공정을 진행하는 단계와, 상기 폴리실리콘층 상에 LixTa1-xO3막(x는 0.25 내지 0.75)으로된 유전체막을 형성하는 단계와 상기 유전체막을 2차 아닐링처리하여 상기 유전체막을 결정화시키고 막내의 탄소를 포함한 불순물을 제거시키는 단계 및, 상기 LixTa1-xO3막(x는 0.25 내지 0.75)으로된 유전체막상부에 TiN층과 도핑된 폴리실리콘층으로된 플레이트 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a DRAM device, the method including: forming an interlayer insulating film having a contact hole exposing a junction region of a transistor on a semiconductor substrate provided with a transistor; Forming a storage node electrode formed of a polysilicon layer on the interlayer insulating layer to be in contact with the exposed junction region, and performing a first annealing process on the storage node electrode by plasma or rapid thermal nitridation (RTN) treatment And forming a dielectric film of a Li x Ta 1-x O 3 film (x is 0.25 to 0.75) on the polysilicon layer and subjecting the dielectric film to secondary annealing to crystallize the dielectric film and carbon in the film. a dielectric film on a part of the step of removing impurities, and the Li x Ta 1-x O 3 film (x is 0.25 to 0.75) also including the TiN layer The poly is characterized in that comprises a step of forming a plate electrode of a silicon layer.
본 발명에 의하면, 캐패시터의 유전체막으로 유전율이 매우 높은 LiTaO3막을 이용하므로써, 디램 디바이스의 캐패시턴스를 크게 향상시킬 수 있다. 아울러, LiTaO3막은 페롭스카이트 결정 구조를 가지므로, 종래의 다른 유전체막과 비교하여 볼 때 매우 안정적이다.According to the present invention, by using a LiTaO 3 film having a very high dielectric constant as the dielectric film of the capacitor, the capacitance of the DRAM device can be greatly improved. In addition, since the LiTaO 3 film has a perovskite crystal structure, the LiTaO 3 film is very stable compared with other conventional dielectric films.
따라서, 유전체막내에서 누설 전류가 발생되지 않으며, 절연 파괴 전압도 상당히 증대되어, 유전체막의 신뢰성이 개선된다.Therefore, no leakage current is generated in the dielectric film, and the dielectric breakdown voltage is also significantly increased, so that the reliability of the dielectric film is improved.
(실시예)(Example)
이하 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 자세히 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도면 도 2a 내지 도 2c는 본 발명에 다른 디램 디바이스의 캐패시터 제조방법을 설명하기 위한 공정 단면도이고, 도 3은 본 발명에 따른 유전체막의 결정 구조를 나타낸 도면이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a DRAM device according to the present invention, and FIG. 3 is a view showing a crystal structure of a dielectric film according to the present invention.
본 발명에 따른 디램 디바이스의 캐패시터 제조방법은, 도 2a에 도시된 바와 같이, 먼저 트랜지스터(도시되지 않음)가 구비된 반도체기판(10)상부에 층간절연막(11)을 증착한다음, 트랜지스터의 접합영역(10a)이 노출되도록 콘택홀을 형성한다.In the method of manufacturing a capacitor of a DRAM device according to the present invention, as shown in FIG. 2A, an interlayer insulating film 11 is first deposited on a semiconductor substrate 10 having a transistor (not shown), and then a junction of transistors is formed. A contact hole is formed to expose the region 10a.
그다음, 노출된 접합영역(10a)과 콘택되도록 불순물이 도핑된 제 1 폴리실리콘층(미도시)을 형성하고, 상기 제1폴리실리콘층(미도시)상에 희생 산화막(미도시)을 증착한다.Next, a first polysilicon layer (not shown) doped with impurities to contact the exposed junction region 10a is formed, and a sacrificial oxide film (not shown) is deposited on the first polysilicon layer (not shown). .
이어서, 상기 희생 산화막(미도시)과 제 1 폴리실리콘층(미도시)을 예정된 캐패시터 크기 정도로 패터닝한다음, 불순물이 도핑된 제 2 폴리실리콘층(미도시)을 증착한다.Subsequently, the sacrificial oxide film (not shown) and the first polysilicon layer (not shown) are patterned to a predetermined capacitor size, and then a second polysilicon layer (not shown) doped with impurities is deposited.
그다음, 상기 제 2 폴리실리콘층을 희생산화막의 표면이 노출되도록 이방성 식각하여, 희생 산화막 및 제 1 폴리실리콘층 측벽에 스페이서(미도시)를 형성한다.Next, the second polysilicon layer is anisotropically etched to expose the surface of the sacrificial oxide layer, thereby forming spacers (not shown) on sidewalls of the sacrificial oxide layer and the first polysilicon layer.
이어서, 상기 희생 산화막을 제거하여, 상기 스페이서와 제1폴리실리콘층으로 이루어진 실린더(cylinder) 형상의 스토리지 전극(12)을 형성한다. 그후, 상기 스토리지 전극(12)의 표면적을 더욱 확장시키기 위하여, 상기 스토리지전극(12)의 표면상에 HSG(hemi spherical grain:12a)을 증착하여 상기 스토리지 전극(12)의 표면은 요철(12a)을 형성한다.Subsequently, the sacrificial oxide film is removed to form a cylindrical storage electrode 12 including the spacer and the first polysilicon layer. Thereafter, in order to further expand the surface area of the storage electrode 12, a hemi spherical grain 12 H (HSG) is deposited on the surface of the storage electrode 12 so that the surface of the storage electrode 12 is uneven 12a. To form.
그다음, 상기 요철(12a)을 갖는 스토리지 전극(12) 표면에 불순물을 제거하고, 요철 형성으로 비정질 상태가 된 스토리지전극(12)을 결정화하며, 스토리지 전극(12) 상부에 자연 산화막의 형성을 방지하기 위하여, 인시튜(in-situ)로 1차 어닐링 공정을 실시하여준다.Then, impurities are removed from the surface of the storage electrode 12 having the unevenness 12a, crystallization of the storage electrode 12 which is in an amorphous state by the unevenness formation, and prevention of formation of a natural oxide film on the storage electrode 12. To do this, a first annealing process is performed in-situ.
이때, 1차 어닐링 공정은 200 내지 400℃의 온도에서 플라즈마를 이용하여 NH3또는 N2분위기에서 진행되거나, 또는 750 내지 850℃의 온도에서 1 내지 5분동안 RTN(rapid thermal nitridation) 처리될 수 있다. 상기 1차 어닐링 공정으로,스토리지 전극(12)의 표면에는 질산화막(13)이 형성된다.In this case, the first annealing process may be performed in an NH 3 or N 2 atmosphere using a plasma at a temperature of 200 to 400 ℃, or may be subjected to rapid thermal nitridation (RTN) for 1 to 5 minutes at a temperature of 750 to 850 ℃ have. In the first annealing process, the nitride oxide film 13 is formed on the surface of the storage electrode 12.
이어서, 도 2b에 도시된 바와 같이, 질산화막(13)상부에 본 실시예에 따른 유전체막(14)을 형성한다. 유전체막(14)은 LPCVD 챔버내에서 300 내지 500℃의 온도로 기상반응(gas phase reaction)을 억제시키면서 형성되는 LixTa1-xO3(x=0.25∼ 0.75)막이다. 상기 LixTa1-xO3막의 Ta에 대한 Li의 몰조성비(Li/Ta)는 0.3 내지 3 정도가 되도록 한다.Subsequently, as shown in FIG. 2B, the dielectric film 14 according to the present embodiment is formed on the nitridation film 13. The dielectric film 14 is a Li x Ta 1-x O 3 (x = 0.25 to 0.75) film formed while suppressing a gas phase reaction at a temperature of 300 to 500 ° C. in the LPCVD chamber. The molar composition ratio (Li / Ta) of Li to Ta of the Li x Ta 1-x O 3 film is about 0.3 to about 3.
이때, LixTa1-xO3막(14)을 구성하는 각 성분은 다음과 같은 방식으로 얻어진다.At this time, each component constituting the Li x Ta 1-x O 3 film 14 is obtained in the following manner.
먼저, Ta 성분의 화학 증기는 MFC(mass flow controller)와 같은 유량 조절기를 통하여 증발기 또는 증발관으로 공급되는 일정량의 Ta(OC2H5)5용액을 150 내지 200℃의 온도로 증발시켜서 얻는다.First, the chemical vapor of Ta component is obtained by evaporating a predetermined amount of Ta (OC 2 H 5 ) 5 solution supplied to an evaporator or an evaporator via a flow controller such as a mass flow controller (MFC) to a temperature of 150 to 200 ° C.
또한, Li 성분의 화학 증기는 C2H3LiO2, LiOH, Li20와 같은 Li 화합물을 에탄올 또는 부탄올류의 알콜이나 증류수에 녹인 포화용액 또는 과포화 용액을 유량 조절기를 통하여 증발기로 공급한다음, 일정량을 100 내지 400℃의 온도에서 증발시켜서 얻는다.In addition, the chemical vapor of Li component is supplied to the evaporator a saturated solution or a supersaturated solution in which Li compounds such as C 2 H 3 LiO 2 , LiOH, Li 2 0 are dissolved in ethanol or butanol alcohol or distilled water through a flow controller. It obtains by evaporating a fixed amount at the temperature of 100-400 degreeC.
이와 같은 방법을 통하여 얻어진 화학 증기들을 Li에 대한 Ta의 몰비(Ta/Li)를 0.1∼10로 하여, 반응가스인 과잉 02가스와 함께 LPCVD 챔버내에 주입하면, 표면 화학반응(surface chemical reaction)되어, 질산화막(13)상부에 양질의LiTaO3막(14)이 얻어진다.When chemical vapors obtained through this method are injected into an LPCVD chamber with an excess of 0 2 gas, which is a reactant gas, with a molar ratio (Ta / Li) of Ta to Li of 0.1 to 10, a surface chemical reaction As a result, a good quality LiTaO 3 film 14 is obtained on the nitrification film 13.
그다음, 상기 LiTaO3막(14)의 유전율을 증가시키기 위하여, 결과물을 2차 어닐링한다. 이때, 상기 2차 어닐링 공정은 800 내지 900℃의 온도에서, 전기로 내를 N2O 또는 O2분위기로 하여 10분 내지 60분 정도 실시한다. 상기 2차 어닐링 공정으로 LiTaO3로 된 유전체막(14)은 결정화되며, 유전율(ε)이 45 정도로 증가된다. 또한, 상기 2차 어닐링 공정에 의하여 LiTaO3로 된 유전체막(14)내의 탄소와 같은 불순물이 제거된다.Then, to increase the dielectric constant of the LiTaO 3 film 14, the resultant is second annealed. At this time, the secondary annealing process is carried out at a temperature of 800 to 900 ℃, the inside of the electric furnace in a N 2 O or O 2 atmosphere for about 10 to 60 minutes. In the secondary annealing process, the dielectric film 14 made of LiTaO 3 is crystallized, and the dielectric constant? Is increased to about 45 degrees. In addition, by the secondary annealing process, impurities such as carbon in the dielectric film 14 made of LiTaO 3 are removed.
여기서, 도 3은 본 발명에 따른 유전체막(14)의 결정 구조를 나타낸 것으로서, 본 발명의 LiTaO3로 된 유전체막(14)은 Ta2O5에 Li을 첨가한 것으로서, 도 3에 도시된 바와 같이, Li1+Ta5+O3유형 즉 A1+B5+O3의 페롭스카이트(perovskite) 결정 구조를 갖는다. 이 페롭스카이트 결정 구조는 공지된 바와 같이 매우 안정적인 결합 구조이므로, 베이컨시 원자들이 발생되지 않는다.3 shows a crystal structure of the dielectric film 14 according to the present invention. The dielectric film 14 made of LiTaO 3 according to the present invention is formed by adding Li to Ta 2 O 5 . As shown, it has a perovskite crystal structure of the Li 1+ Ta 5+ O 3 type, ie A 1+ B 5+ O 3 . This perovskite crystal structure is a very stable bonding structure, as is known, so that no vacancy atoms are generated.
이에따라, 베이컨시 원자들의 결합력을 증대시키기 위한 산화 공정 또는 막질을 안정하게 하기 위한 추가 공정이 요구되지 않는다.Accordingly, no oxidation process is required to increase the binding force of the vacancy atoms or an additional process to stabilize the film quality.
이어서, 도 2c에 도시된 바와 같이, 상기 유전체막(14)상부에 TiN막(15)과 도핑된 폴리실리콘막으로 플레이트전극(16)을 형성하여 캐패시터(18)를 완성한다.Subsequently, as shown in FIG. 2C, the plate electrode 16 is formed of the TiN film 15 and the doped polysilicon film on the dielectric film 14 to complete the capacitor 18.
이와같이 형성된 LiTaO3로 된 유전체막(14)은 유전율이 25인 Ta205막 및 유전율이 7인 NO막과 비교하여볼 때 월등히 큰 유전율(ε=45)을 가지므로, 큰 캐패시턴스를 얻을 수 있다.The dielectric film 14 made of LiTaO 3 thus formed has an extremely large dielectric constant (ε = 45) as compared with a Ta205 film having a dielectric constant of 25 and a NO film having a dielectric constant of 7, whereby a large capacitance can be obtained.
또한, 상기 유전체막(14)에 의하여 캐패시턴스가 확보됨으로써, 표면 면적을 증대시키기 위하여 스토리지전극을 복잡하게 형성하지 않아도 되므로써 공정이 간소화된다.In addition, since the capacitance is ensured by the dielectric film 14, the process is simplified because the storage electrode does not have to be complicated to increase the surface area.
그리고, LiTaO3로 된 유전체막(14)은 매우 안정된 구조를 가지고 있으며, 2차 어닐링 공정으로 불순물을 제거하였으므로, 유전체막(14)내에서 누설 전류가 발생되지 않으며, 절연 파괴 전압(breakdown voltage)이 매우 높다.In addition, since the dielectric film 14 made of LiTaO 3 has a very stable structure and impurities are removed by the secondary annealing process, no leakage current is generated in the dielectric film 14, and a breakdown voltage is generated. This is very high.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 캐패시터의 유전체막으로 유전율이 매우 높은 LiTaO3막을 이용하므로써, 디램 디바이스의 캐패시턴스를 크게 향상시킬 수 있다. 아울러, LiTaO3막은 페롭스카이트 결정 구조를 가지므로, 종래의 다른 유전체막과 비교하여 볼 때 매우 안정적이다.As described in detail above, according to the present invention, by using a LiTaO 3 film having a very high dielectric constant as the dielectric film of the capacitor, the capacitance of the DRAM device can be greatly improved. In addition, since the LiTaO 3 film has a perovskite crystal structure, the LiTaO 3 film is very stable compared with other conventional dielectric films.
따라서, 유전체막내에서 누설 전류가 발생되지 않으며, 절연 파괴 전압도 상당히 증대되어, 유전체막의 신뢰성이 개선된다.Therefore, no leakage current is generated in the dielectric film, and the dielectric breakdown voltage is also significantly increased, so that the reliability of the dielectric film is improved.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025782A KR100315017B1 (en) | 1998-06-30 | 1998-06-30 | DRAM device capacitors and manufacturing methods thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025782A KR100315017B1 (en) | 1998-06-30 | 1998-06-30 | DRAM device capacitors and manufacturing methods thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000004350A KR20000004350A (en) | 2000-01-25 |
| KR100315017B1 true KR100315017B1 (en) | 2002-04-24 |
Family
ID=19542170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980025782A KR100315017B1 (en) | 1998-06-30 | 1998-06-30 | DRAM device capacitors and manufacturing methods thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100315017B1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100431740B1 (en) * | 2001-09-14 | 2004-05-17 | 주식회사 하이닉스반도체 | Semiconductor with High-k dielectric layer and Method for fabricating the same |
| KR100876842B1 (en) * | 2006-10-02 | 2009-01-07 | 주식회사 하이닉스반도체 | Method for manufacturing of semiconductor device |
| US7651894B2 (en) | 2006-10-02 | 2010-01-26 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163847A (en) * | 1992-11-17 | 1994-06-10 | Ricoh Co Ltd | Memory device and its manufacture |
-
1998
- 1998-06-30 KR KR1019980025782A patent/KR100315017B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163847A (en) * | 1992-11-17 | 1994-06-10 | Ricoh Co Ltd | Memory device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000004350A (en) | 2000-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100444603B1 (en) | Method of manufacturing a Ta2O5-Al2O3 dielectric film and semiconductor device utilizing thereof | |
| JP4035626B2 (en) | Capacitor manufacturing method for semiconductor device | |
| US6787414B2 (en) | Capacitor for semiconductor memory device and method of manufacturing the same | |
| US6740553B1 (en) | Capacitor for semiconductor memory device and method of manufacturing the same | |
| US6410400B1 (en) | Method of manufacturing Ta2O5capacitor using Ta2O5thin film as dielectric layer | |
| US7371670B2 (en) | Method for forming a (TaO)1-x(TiO)xN dielectric layer in a semiconductor device | |
| KR100359860B1 (en) | Capacitor Formation Method of Semiconductor Device | |
| KR100504435B1 (en) | Method of forming capacitor in semiconducotr device | |
| KR100371143B1 (en) | Method of forming high efficiency capacitor in semiconductor device | |
| KR100315017B1 (en) | DRAM device capacitors and manufacturing methods thereof | |
| JP2001057414A (en) | Capacitor for semiconductor memory element and its manufacture | |
| JP2001036046A (en) | Capacitor of semiconductor memory device and its manufacture | |
| US6329237B1 (en) | Method of manufacturing a capacitor in a semiconductor device using a high dielectric tantalum oxide or barium strontium titanate material that is treated in an ozone plasma | |
| JP4531935B2 (en) | Capacitor forming method for semiconductor memory device | |
| KR100342873B1 (en) | Method for forming capacitor of semiconductor device | |
| US6602722B2 (en) | Process for fabricating capacitor having dielectric layer with pervskite structure and apparatus for fabricating the same | |
| JP2001053255A (en) | Manufacture of capacitor of semiconductor memory element | |
| KR100882090B1 (en) | Method for fabricating capacitor of semiconductor device | |
| KR100388203B1 (en) | Method for manufactruing capacitor in semiconductor device | |
| KR20010108989A (en) | Method for manufacturing capacitor in semiconductor memory divice | |
| KR100386450B1 (en) | Method for forming of capacitor in semiconductor | |
| KR100480912B1 (en) | method for fabricating capacitor | |
| KR100355602B1 (en) | Method for manufacturing capacitor in semiconductor device | |
| KR100358065B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100380269B1 (en) | Method for manufacturing capacitor in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20091028 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |