KR100358065B1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR100358065B1 KR100358065B1 KR1019990024219A KR19990024219A KR100358065B1 KR 100358065 B1 KR100358065 B1 KR 100358065B1 KR 1019990024219 A KR1019990024219 A KR 1019990024219A KR 19990024219 A KR19990024219 A KR 19990024219A KR 100358065 B1 KR100358065 B1 KR 100358065B1
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- dielectric film
- capacitor
- semiconductor device
- gas
- taon dielectric
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- 239000003990 capacitor Substances 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 62
- 229910003071 TaON Inorganic materials 0.000 claims abstract description 50
- 239000007789 gas Substances 0.000 claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 239000012495 reaction gas Substances 0.000 claims abstract description 5
- 238000005121 nitriding Methods 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 238000011065 in-situ storage Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000011066 ex-situ storage Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 238000010574 gas phase reaction Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000009279 wet oxidation reaction Methods 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims 1
- 238000006557 surface reaction Methods 0.000 claims 1
- 238000001704 evaporation Methods 0.000 abstract description 5
- 230000008020 evaporation Effects 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 52
- 230000008569 process Effects 0.000 description 20
- 239000010410 layer Substances 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000007847 structural defect Effects 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 150000001723 carbon free-radicals Chemical class 0.000 description 1
- -1 carbon ions Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 종래 캐패시터의 유전체막의 경우 유전특성이 열악하고 유전체막 내에 포함된 불순물 성분으로 인하여 캐패시터의 누설전류 수준이 증가하는 문제점을 해결하기 위하여, NH3가스 분위기에서 Ta(OC2H5)5의 증발가스와 반응가스인 O2가스를 이용하여 TaON 유전체막을 형성하므로써, 유전율이 높고 누설전류 수준이 낮으며 막질이 우수한 TaON 유전체막을 갖는 반도체 소자의 캐패시터 제조 방법이 개시된다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device, in order to solve the problem that the dielectric film of the conventional capacitor is poor dielectric properties and the leakage current level of the capacitor increases due to the impurity component contained in the dielectric film, NH 3 gas Formation of TaON dielectric film using Ta (OC 2 H 5 ) 5 evaporation gas and reaction gas O 2 gas to manufacture capacitor of semiconductor device with TaON dielectric film with high dielectric constant, low leakage current level and excellent film quality The method is disclosed.
Description
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 유전상수 값이 크면서 막질이 우수한 TaON 유전체막을 갖는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device having a TaON dielectric film having a high dielectric constant value and excellent film quality.
최근 미세화된 반도체 공정기술의 발달로 메모리 제품의 고집적화가 가속화됨에 따라 단위 셀의 면적이 크게 감소하고 있으며, 동작전압의 저전압화가 이루어지고 있다. 그러나 셀 면적의 감소에도 불구하고 기억소자의 동작에 필요한 충전용량은 소프트 에러의 발생과 리프레쉬 시간의 단축을 방지하기 위해서 25fF/cell 이상을 갖도록 하여야 한다. 따라서 현재 NO(Nitride-Oxide) 구조의 질화막을 유전체막으로 사용하고 있는 DRAM용 캐패시터 소자의 경우 표면적이 큰 반구형 구조의 전극 표면을 갖는 3차원 형태의 전하저장전극을 사용하고 있다, 그런데, NO 구조의 캐패시터는 256N 이상의 DRAM 제품에 필요한 충전용량을 확보하는데 그 한계를 보이고 있으며, 이에 따라 캐패시터의 높이도 점점 증가하고 있다. 그런데, 캐패시터의 높이가 증가하게 되면 셀지역과 주변회로 지역간에 생기는 단차로 인하여 후속 노광 공정시 초점심도여유(DOF)가 확보되지 않아 배선공정 이후 집적공정에 악영향을 미치게 된다. 또한, NO 캐패시터의 유전율(ε)은 7정도로 낮은 단점이 있다.Recently, as the integration of memory products is accelerated due to the development of miniaturized semiconductor processing technology, the area of a unit cell is greatly reduced, and the operating voltage is reduced. However, despite the reduction of the cell area, the charge capacity required for the operation of the memory device should be 25 fF / cell or more in order to prevent the occurrence of soft errors and shortening of the refresh time. Therefore, in the case of a DRAM capacitor element using a nitride film having a structure of NO (Nitride-Oxide) as a dielectric film, a three-dimensional charge storage electrode having a hemispherical electrode surface having a large surface area is used. Capacitors are showing limitations in securing the necessary charge capacity for DRAM products with more than 256N. As a result, the height of capacitors is increasing. However, when the height of the capacitor increases, the depth of focus (DOF) is not secured during the subsequent exposure process due to the step difference between the cell region and the peripheral circuit region, which adversely affects the integration process after the wiring process. In addition, the dielectric constant (ε) of the NO capacitor has a disadvantage of as low as about 7.
최근에는 이러한 NO 캐패시터의 한계를 극복하기 위해 Ta2O5유전체막을 이용한 캐패시터의 개발이 본격적으로 이루어지고 있다. 그러나 Ta2O5유전체막은 유전율이 25 정도로 높은 장점이 있는 반면, 불안정한 화학량론비(stoichiometry)를 갖고 있기 때문에 탄탈륨(Ta)과 산소(O)의 조성비 차이에 기인한 치환형 Ta원자 (vacancy atom)가 Ta2O5막 내에 존재하게 된다.Recently, in order to overcome the limitations of the NO capacitor, development of a capacitor using a Ta 2 O 5 dielectric film has been made in earnest. However, the Ta 2 O 5 dielectric film has an advantage of having a high dielectric constant of about 25, but has an unstable stoichiometry, and thus a substitutional Ta atom due to the difference in the composition ratio of tantalum (Ta) and oxygen (O). Is present in the Ta 2 O 5 film.
그리고 Ta2O5박막 형성시 Ta2O5의 전구체인 Ta(OC2H5)5의 유기물과 O2또는N2O 가스의 반응으로 인해서 불순물인 탄소원자와 탄소화합물(예를 들어 C, CH4, C2H4등) 및 수분(H2O)이 함께 존재하게 된다. 결국 Ta2O5박막 내에 불순물로 존재하는 탄소 원자, 탄소 이온 및 탄소 기(radical)로 인해서 캐패시터의 누설전류가 증가하게 되고 유전특성이 열화되는 문제점이 있다.And carbon atoms and carbon compounds that are impurities due to the reaction of O 2 or N 2 O gas with Ta (OC 2 H 5 ) 5 organic material, which is a precursor of Ta 2 O 5 , when the Ta 2 O 5 thin film is formed. CH 4 , C 2 H 4, etc.) and moisture (H 2 O) are present together. As a result, the leakage current of the capacitor is increased due to the carbon atoms, carbon ions, and carbon radicals present as impurities in the Ta 2 O 5 thin film, and the dielectric properties are deteriorated.
이상 설명한 바와 같이, Ta2O5은 물질 자체의 불안정한 화학적 조성 때문에 그 박막 내에는 산소 공공(oxygen vacancy) 상태의 치환형 Ta원자가 항상 국부적으로 존재할 수 밖에 없다. 특히 이같은 Ta2O5박막의 산소공공의 수는 성분들의 함량과 결합 정도에 따라 다소의 차이는 있을 수 있지만 완전하게 제거할 수 있는 방법이 아직까지 제시되지 않고 있다. 결과적으로 Ta2O5막 고유의 불안정한 화학량론비를 안정화시켜 누설전류를 방지하려는 목적으로 박막 내에 잔존해 있는 치환형 Ta원자를 산화시키려는 별도의 산화공정이 필요하게 된다. 특히 Ta2O5막은 상/하부 전극으로 사용하고 있는 폴리실리콘(산소계 전극) 또는 TiN(금속계 전극)과의 산화반응성이 크기 때문에 박막 내에 존재하는 산소가 계면으로 이동하여 전유전 산화층을 형성함과 동시에 계면의 균질성이 크게 저하되는 문제점이 있다.As described above, Ta 2 O 5 always has a local substitution of a substituted Ta atom in an oxygen vacancy state due to the unstable chemical composition of the material itself. In particular, the number of oxygen vacancies in the Ta 2 O 5 thin film may vary slightly depending on the content of the components and the degree of bonding, but a method for completely removing the Ta 2 O 5 thin film has not been proposed yet. As a result, a separate oxidation process is required to oxidize the substituted Ta atoms remaining in the thin film for the purpose of stabilizing the unstable stoichiometric ratio inherent in the Ta 2 O 5 film to prevent leakage current. In particular, the Ta 2 O 5 film has a high oxidation reactivity with polysilicon (oxygen based electrode) or TiN (metal based electrode) used as the upper and lower electrodes, and thus oxygen in the thin film moves to the interface to form a dielectric dielectric layer. At the same time, there is a problem that the homogeneity of the interface is greatly reduced.
따라서, 본 발명은 NH3가스 분위기에서 Ta(OC2H5)5의 증발가스와 반응가스인 O2가스를 이용하여 질산화 반응을 유도하므로써 Ta-O-N이 강한 결합력으로 공유결합되어 있는 TaON 유전체막을 형성하므로써, 유전율이 높고 누설전류 수준이 낮으며 막질이 우수한 TaON 유전체막을 갖는 반도체 소자의 캐패시터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a TaON dielectric film in which Ta-ON is covalently bonded with a strong bonding force by inducing nitrification reaction using an evaporation gas of Ta (OC 2 H 5 ) 5 and an O 2 gas which is a reaction gas in NH 3 gas atmosphere. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device having a TaON dielectric film having a high dielectric constant, a low leakage current level and excellent film quality.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 캐패시터를 형성하기 위한 하부구조가 형성된 반도체 기판이 제공되는 단계와, 상기 반도체 기판 상에 하부전극을 형성하는 단계와, 상기 하부전극을 포함한 전체구조 상부에 NH3가스 분위기에서 Ta(OC2H5)5의 가스와 반응가스인 O2가스를 이용하여 TaON 유전체막을 형성하는 단계와, 상부전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: providing a semiconductor substrate having a lower structure for forming a capacitor; forming a lower electrode on the semiconductor substrate; And forming a TaON dielectric film on the entire structure including the electrode by using Ta (OC 2 H 5 ) 5 gas and a reactive gas O 2 gas in an NH 3 gas atmosphere, and forming an upper electrode. It is characterized by.
도 1a 내지 1d는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 도시한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining the method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 2a 및 2b는 원통형 구조를 갖는 캐패시터의 전하저장전극을 설명하기 위해 도시한 소자의 단면도.2A and 2B are cross-sectional views of a device for explaining the charge storage electrode of a capacitor having a cylindrical structure.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11, 21 : 반도체 기판 12, 22 : 층간 절연막11 and 21: semiconductor substrate 12 and 22: interlayer insulating film
13, 23 : 하부전극 14 : TaON 유전체막13, 23: lower electrode 14: TaON dielectric film
15, 31 : 상부전극 32 : 완충층15, 31: upper electrode 32: buffer layer
24 : 반구형 폴리실리콘층24: hemispherical polysilicon layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 내지 1d는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 1a에 도시된 바와 같이, 하부구조가 형성된 반도체 기판(11) 상에 층간 절연막(12) 및 전하저장전극인 하부전극(13)을 형성한다. 하부전극(13)은 LPCVD 챔버 내에서 형성하는데, 도 1a에 도시한 것과 같이 스택 구조로 형성하거나 도 2a 및 2b에 도시된 바와 같이 원통형 구조로 형성한다.As shown in FIG. 1A, an interlayer insulating layer 12 and a lower electrode 13, which is a charge storage electrode, are formed on a semiconductor substrate 11 on which a lower structure is formed. The lower electrode 13 is formed in the LPCVD chamber, which is formed in a stack structure as shown in FIG. 1A or in a cylindrical structure as shown in FIGS. 2A and 2B.
도 2a 및 2b는 원통형 구조의 전하저장전극을 설명하기 위해 도시한 소자의 단면도이다.2A and 2B are cross-sectional views of a device illustrated to explain a charge storage electrode having a cylindrical structure.
도 2a는 반도체 기판(21)의 층간 절연막(22) 상부에 원통형 구조의하부전극(23)을 형성한 상태를 나타내고, 도 2b는 캐패시터의 충전용량을 증대시키기 위해 전하저장전극용 폴리실리콘층 표면에 반구형 폴리실리콘층(24)을 형성한 상태를 나타낸다.FIG. 2A illustrates a state in which a lower electrode 23 having a cylindrical structure is formed on the interlayer insulating layer 22 of the semiconductor substrate 21, and FIG. 2B illustrates a surface of the polysilicon layer for the charge storage electrode in order to increase the charge capacity of the capacitor. The state in which the hemispherical polysilicon layer 24 is formed is shown.
이상과 같은 방법으로 하부전극(13 또는 23)을 형성하고 나면, 하부전극(13, 23)과 후속 공정으로 형성될 TaON 유전체막과의 계면에 저유전 산화막(SiO2)이 형성되는 것을 방지하기 위해 시간 지연없이 인-시투(In-situ)로 하부전극(13)을 표면처리한다.After the lower electrode 13 or 23 is formed in the above manner, the low dielectric oxide film (SiO 2 ) is prevented from being formed at the interface between the lower electrode 13 and 23 and the TaON dielectric film to be formed in a subsequent process. The lower electrode 13 is surface treated in-situ without time delay.
하부전극(13)의 표면처리 방법으로는 하부전극(13) 형성 후 시간 지연없이 인-시투로 200 내지 600℃의 온도조건 및 NH3분위기에서 30초 내지 10분 동안 플라즈마 처리하여 하부전극(13) 표면을 질화시키는 방법, RTP를 이용하여 650 내지 950℃의 온도조건 및 NH3분위기에서 어닐링하여 질화시키는 방법, 퍼니스를 이용하여 500 내지 1000℃의 온도조건 및 NH3분위기에서 질화시키는 방법 등이 있다.In the surface treatment method of the lower electrode 13, the lower electrode 13 may be plasma-treated for 30 seconds to 10 minutes in a NH 3 atmosphere and a temperature condition of 200 to 600 ° C. in-situ without time delay after the lower electrode 13 is formed. ) a method of nitriding the surface, a method of nitriding method for nitriding annealing at a temperature condition and a NH 3 atmosphere at 650 to 950 ℃ using the RTP, the temperature conditions and the NH 3 atmosphere at 500 to 1000 ℃ using a furnace such as have.
이상과 같이 하부전극(13) 표면을 질화시키기 전에, HF 증기 또는 HF 용액과 같은 HF 화합물을 사용하여 하부전극(13) 표면에 성장된 자연산화막을 제거하는 방법, HF 화합물을이용한 세정 공정 전 또는 후에 NH4OH 용액 또는 H2SO4용액 등의 화합물을 사용하여 계면처리를 수행하는 방법, 하부전극(13) 표면의 자연산화막을 제거하고 세정공정을 진행한 다음 5 내지 25Å의 두께로 실리콘 질화막을 형성하는 방법, RTP를 이용하여 300 내지 950℃의 온도조건 및 NH3또는 N2/H2분위에서 질화시키거나 NO2또는 O2분위기에서 열처리하는 방법 등이 있다.As described above, before the surface of the lower electrode 13 is nitrided, a method of removing the native oxide film grown on the surface of the lower electrode 13 using HF compound such as HF vapor or HF solution, before the cleaning process using the HF compound, or After the interfacial treatment using a compound such as NH 4 OH solution or H 2 SO 4 solution, remove the natural oxide film on the surface of the lower electrode 13, and proceeds the cleaning process and then silicon nitride film to a thickness of 5 to 25Å a method, the method for temperature conditions of 300 to 950 ℃ using a RTP and a NH 3 or N 2 / H 2 atmosphere, or heat treatment in the nitriding to NO 2 in the O 2 atmosphere or the like to form a.
이와 같이 하부전극(13)을 표면처리하게 되면, 산소에 대한 확산 장벽(diffusion barrier)이 형성되어 후속 공정시 TaON 유전체막 하부쪽으로 저유전 산화막이 생성되는 것을 방지할 수 있고 계면을 균질화시킬 수 있다. 또한, 댕글링 본드(dangling bond)로 인한 구조적 결함(defect)이나 구조적 불균일성(homogeneity)을 개선하여 누설전류 특성을 개선할 수 있다.As such, when the lower electrode 13 is surface treated, a diffusion barrier for oxygen may be formed to prevent a low dielectric oxide film from being formed below the TaON dielectric layer in a subsequent process and to homogenize the interface. . In addition, the leakage current characteristics may be improved by improving structural defects or structural homogeneity due to dangling bonds.
도 1b에 도시된 바와 같이, 전체구조 상부에 TaON 유전체막(14)을 형성한다. TaON 유전체막(14)은 NH3가스 분위기에서 Ta(OC2H5)5의 증발가스와 반응가스인 O2가스를 흘려주어 질산화 반응을 유도하므로써 형성할 수 있다. TaON 유전체막(14) 형성에 앞서 먼저, 300 내지 600℃의 LPCVD 챔버에서 기상반응(gas phase reaction)을 억제시키면서 Ta 성분의 화학증기를 사용하여 150Å 이하의 얇은 비정질 TaON막을 형성한다. 이때, Ta 성분의 화학증기는 탄탈륨 에틸레이트(Tantalum-ethylate; Ta(OC2H5)5)와 같은 Ta 화합물을 MFC(Mass Flow Controller)와 같은 유량조절기를 통해 정량된 양을 증발기 또는 증발관으로 공급한 다음 일정양을 150 내지 200℃에서 증발시켜어 얻는다. 이와 같은 방법을 통해 얻어진 Ta 화학증기를 반응가스인 과잉 O2가스와 NH3가스를 10 내지 1000sccm 범위 내의 유량으로 각각 정량하여 공급한 다음 300 내지 600℃의 LPCVD 챔버 내에서 표면반응시키면 원하는 두께를 갖는 비정질 TaON막을 얻을 수 있다. 이와 같은 방법으로 형성된 TaON 유전체막(14)은 결합력이 강한 Ta-O-N 구조로 공유결합되어 있기 때문에 구조적으로 매우 안정하여, 높은 절연파괴 전압과 소자 동작에 필요한 충분한 충전용량을 얻을 수 있다. 또한,NO 유전체막(ε=4 내지 5) 보다 유전율이 높기 때문에(ε=20 내지 25) 큰 충전용량을 얻을 수 있다. 또한, Ta2O5캐패시터 형성 공정에서 Ta2O5유전체막 내에 잔존하는 치환형 Ta 원자에 의한 불안정한 화학양론비를 안정화시키기 위한 별도의 산화 공정을 생략할 수 있다. 그리고 TaON 유전체막은 Ta2O5유전체막(ε=23 내지 27)보다 유전율은 다소 작지만 Ta2O5캐패시터에서 Ta2O5증착 및 후속 열처리 과정에서 상부 및 하부전극과의 계면에서 일어나는 산화반응을 효과적으로 억제할 수 있기 때문에 등가산화막의 두께를 35Å 이하로 낮게 조절할 수 있어 Ta2O5캐패시터보다 더 큰 충전용량을 얻을 수 있다.As shown in Fig. 1B, a TaON dielectric film 14 is formed over the entire structure. The TaON dielectric film 14 can be formed by flowing an evaporation gas of Ta (OC 2 H 5 ) 5 and an O 2 gas which is a reaction gas in an NH 3 gas atmosphere to induce nitrification. Prior to formation of the TaON dielectric film 14, a thin amorphous TaON film of 150 kPa or less is formed using chemical vapor of Ta component while suppressing gas phase reaction in an LPCVD chamber at 300 to 600 ° C. At this time, the chemical vapor of the Ta component is the amount of Ta compound such as tantalum ethylate (Tantalum-ethylate; Ta (OC 2 H 5 ) 5 ) is quantified through a flow controller such as a MFC (Mass Flow Controller). It is obtained by feeding to a predetermined amount and then evaporating at 150-200 ° C. Ta chemical vapor obtained through the above method was quantitatively supplied to each of the reactant excess O 2 gas and NH 3 gas at a flow rate within the range of 10 to 1000 sccm, and then surface-reacted in an LPCVD chamber at 300 to 600 ° C. to obtain a desired thickness. An amorphous TaON film having can be obtained. Since the TaON dielectric film 14 formed in this manner is covalently bonded in a Ta-ON structure having a strong bonding force, the TaON dielectric film 14 is structurally very stable, thereby obtaining a high dielectric breakdown voltage and sufficient charge capacity required for device operation. In addition, since the dielectric constant is higher than that of the NO dielectric film (ε = 4 to 5) (ε = 20 to 25), a large charge capacity can be obtained. In addition, in the Ta 2 O 5 capacitor formation process, an additional oxidation process may be omitted to stabilize the unstable stoichiometry due to the substituted Ta atoms remaining in the Ta 2 O 5 dielectric film. And a TaON dielectric film Ta 2 O 5 dielectric layer (ε = 23 to 27) than the dielectric constant is rather small, but the oxidation reaction in the Ta 2 O 5 deposition and subsequent heat treatment at Ta 2 O 5 capacitor takes place at the interface between the upper and lower electrodes Since the effective oxide film can be effectively suppressed, the thickness of the equivalent oxide film can be adjusted to less than 35 kW, thereby obtaining a larger charging capacity than the Ta 2 O 5 capacitor.
이와 같이 비정질 TaON 유전체막을 형성한 후 비정질 TaON막의 유전율을 증가시키고 결합구조를 치밀화시켜 결합력이 강화되도록 하기 위하여 결정화시킨다. TaON막을 결정화시키는 방법은 비정질 TaON막을 RTP를 이용하여 650 내지 950℃의 온도에서 30초 내지 10분정도 어닐링하는 방법, 퍼니스를 이용하여 650 내지 950℃의 온도조건 및 N2O(또는 O2또는 N2) 분위기에서 1분 내지 30분 동안 어닐링하는 방법 등이 있다.As such, after forming the amorphous TaON dielectric film, crystallization is performed to increase the dielectric constant of the amorphous TaON film and to densify the bonding structure to enhance the bonding force. Crystallization of the TaON film is performed by annealing the amorphous TaON film for 30 seconds to 10 minutes at a temperature of 650 to 950 ° C using RTP, a temperature condition of 650 to 950 ° C using a furnace and N 2 O (or O 2 or N 2 ) annealing for 1 to 30 minutes in the atmosphere and the like.
이상과 같은 방법으로 TaON 유전체막(14)을 형성하고 나면, TaON 유전체막(14)과 후속 공정으로 형성될 상부전극 계면의 마이크로 크랙(micro crack) 및 핀 홀(pin hole)과 같은 구조 결함을 보강하고 균질도를 향상시키며, 상부전극의 산화 및 전하전도(charge conduction)을 향상시키기 위하여 TaON 유전체막(14) 표면을 질화처리한다. 질화처리 방법에는 TaON 유전체막(14) 형성 후 인-시투 또는 익스-시투로 플라즈마를 이용하여 200 내지 600℃의 온도조건 및 NH3또는 N2/H2또는 N2O 분위기에서 어닐링하여 5 내지 20Å 두께의 질화막을 형성하는 방법, N2O 또는 O2분위기에서 건식 산화 공정 또는 라이트(light) 산화공정을 실시하여 질(산)화하는 방법, 퍼니스 또는 RTP를 이용하여 650 내지 950℃의 온도조건 및 NH3또는 N2/H2또는 N2O 분위기에서 어닐링하여 5 내지 20Å의 질화막을 형성하는 방법 등이 있다.After the TaON dielectric film 14 is formed in the above manner, structural defects such as micro cracks and pin holes at the interface between the TaON dielectric film 14 and the upper electrode to be formed in a subsequent process are removed. The surface of the TaON dielectric film 14 is nitrided to reinforce and improve homogeneity and to improve oxidation and charge conduction of the upper electrode. In the nitriding treatment method, after forming the TaON dielectric film 14, an in-situ or ex-situ plasma is used to anneal in an atmosphere of NH 3 or N 2 / H 2 or N 2 O and a temperature of 200 to 600 ° C. A method of forming a nitride film having a thickness of 20 kÅ, a method of nitriding by performing a dry oxidation process or a light oxidation process in an N 2 O or O 2 atmosphere, or a temperature of 650 to 950 ° C. using a furnace or RTP. Conditions and a method of annealing in an NH 3 or N 2 / H 2 or N 2 O atmosphere to form a nitride film of 5 to 20 kPa.
한편, 비정질 TaON 유전체막(14)의 결정화 및 계면의 질화처리를 동시에 유도하는 방법도 가능한데, 그 방법으로는 TaON 유전체막(14) 형성 후 인-시투 또는 익스-시투로 플라즈마를 이용하여 300 내지 950℃의 온도조건 및 NH3또는 N2또는 N2/H2분위기에서 어닐링하는 방법, 인-시투 또는 익스-시투로 RTP 또는 퍼니스를 이용하여 600 내지 950℃의 온도조건 및 NH3(또는 N2또는 N2/H2또는 N2O)분위기에서 열처리하는 방법, 인-시투 또는 익스-시투로 RTP 또는 퍼니스를 사용하여 N2O 또는 O2분위기에서 열처리를 실시하거나 O2/H2분위기에서 O2/H2의 유량비를 3 이하로 정량화하여 라이트 습식 산화시키는 방법 등이 있다.On the other hand, it is also possible to simultaneously induce the crystallization of the amorphous TaON dielectric film 14 and the nitriding treatment of the interface, such as 300 to 300 by using in-situ or ex-situ plasma after the TaON dielectric film 14 is formed. Annealing in a temperature condition of 950 ° C. and NH 3 or N 2 or N 2 / H 2 atmosphere, temperature conditions of 600 to 950 ° C. and NH 3 (or N) using RTP or furnace in-situ or ex-situ. Heat treatment in an atmosphere of 2 or N 2 / H 2 or N 2 O), in-situ or ex-situ using an RTP or furnace for heat treatment in an N 2 O or O 2 atmosphere, or in an O 2 / H 2 atmosphere And the wet wet oxidation by quantifying the flow rate ratio of O 2 / H 2 to 3 or less.
이상에서 설명한 바와 같은 방법으로 TaON 유전체막(14)을 형성한 다음에는 상부전극을 형성한다.After forming the TaON dielectric film 14 by the method described above, the upper electrode is formed.
도 1c는 도프트 폴리실리콘을 이용하여 상부전극(15)을 형성한 상태를 나타내고, 도 1d는 금속계 물질을 이용하여 상부전극(31)을 50 내지 600Å의 두께로 형성한 후 완충층(32)을 형성한 상태를 나타낸다. 도 1d의 상부전극(31)으로 사용되는 금속계 물질로는 TiN, TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2, Pt 등이 있다.FIG. 1C illustrates a state in which the upper electrode 15 is formed by using doped polysilicon, and FIG. 1D illustrates a buffer layer 32 after forming the upper electrode 31 using a metal material to a thickness of 50 to 600 microns. The formed state is shown. Metal-based materials used as the upper electrode 31 of FIG. 1D include TiN, TaN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2 , and Pt.
캐패시터의 하부전극(13, 23) 및 상부전극(16, 31)은 LPCVD 법을 포함한 PECVD법, RF 마그네틱 스퍼터링법 중 어느 하나를 이용하여 형성한다.The lower electrodes 13 and 23 and the upper electrodes 16 and 31 of the capacitor are formed using any one of a PECVD method including an LPCVD method and an RF magnetic sputtering method.
상술한 바와 같이 본 발명은 NH3가스 분위기에서 Ta(OC2H5)5의 증발가스와 반응가스인 O2가스를 이용하여 질산화 반응을 유도하므로써 Ta-O-N이 강한 결합력으로 공유결합되어 있는 TaON 유전체막을 형성하므로써, 종래의 NO 캐패시터보다 유전율이 높고 Ta2O5캐패시터보다 결합구조가 안정되어 상부 및 하부전극과의 산화반응성이 적은 캐패시터를 얻을 수 있다. 이에 따라 등가 산화막의 두께를 효과적으로 제어할 수 있어 높은 충전용량을 확보할 수 있다. 특히, TaON 유전체막은 구조적으로 안정된 Ta-O-N 결합구조를 갖고 있기 때문에 외부로부터 인가되는 전기적 충격에 강하며, 따라서 절연파괴 전압이 높고 누설전류 수준이 낮은 특성을 갖는다.As described above, according to the present invention, TaON is covalently bonded with a strong bonding force by inducing nitrification reaction using an evaporation gas of Ta (OC 2 H 5 ) 5 and O 2 gas, which is a reaction gas, in an NH 3 gas atmosphere. By forming the dielectric film, a capacitor having a higher dielectric constant than a conventional NO capacitor and a more stable bonding structure than a Ta 2 O 5 capacitor can be obtained with a lower oxidation reaction with the upper and lower electrodes. Accordingly, the thickness of the equivalent oxide film can be effectively controlled, thereby ensuring a high filling capacity. In particular, since the TaON dielectric film has a structurally stable Ta-ON coupling structure, the TaON dielectric film is resistant to electric shocks applied from the outside, and thus has a high dielectric breakdown voltage and a low leakage current level.
또한, TaON 유전체막을 사용하는 경우에는 Ta2O5 캐패시터 형성 공정에서 실시하는 산화 공정을 생략하고도 상부 및 하부전극 계면에서의 산화반응을 억제할 수 있기 때문에 공정 과정이 단축되고 등가 산화막의 두께를 35Å 미만으로 제어할수 있고 충전용량이 증가하게 된다. 결과적으로 전하저장전극의 면적을 장가시키기 위해 이중 또는 삼중구조의 캐패시터 모듈이 필요하지 않게 되어, 캐패시터 모듈 형성공정이 간단한 스택(stack) 구조의 캐패시터라 하더라도 충분한 충전용량을 얻을 수 있기 때문에 단위 공정수가 적고 단위 공정시간이 짧아 생산원가를 절감할 수 있다.In addition, in the case of using a TaON dielectric film, the oxidation process at the upper and lower electrode interfaces can be suppressed without the oxidation process performed in the Ta2O5 capacitor formation process, thereby shortening the process process and reducing the thickness of the equivalent oxide film to less than 35 GPa. Controllable and charging capacity is increased. As a result, no double or triple capacitor module is required to increase the area of the charge storage electrode, and even if the capacitor module forming process is a simple stack capacitor, sufficient charge capacity can be obtained. Small production time and short process time can reduce production cost.
Claims (20)
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| KR1019990024219A KR100358065B1 (en) | 1999-06-25 | 1999-06-25 | Method of manufacturing a capacitor in a semiconductor device |
| GB0015318A GB2355113B (en) | 1999-06-25 | 2000-06-22 | Method of manufacturing capacitor for semiconductor memory device |
| JP2000189842A JP2001036045A (en) | 1999-06-25 | 2000-06-23 | Capacitor of semiconductor memory device and manufacture thereof |
| TW089112253A TWI226673B (en) | 1999-06-25 | 2000-06-23 | Capacitor semiconductor memory device and method of manufacturing the same |
| CNB001268163A CN1163965C (en) | 1999-06-25 | 2000-06-25 | Capacitor for semiconductor storage device and its producing method |
| DE10031056A DE10031056B4 (en) | 1999-06-25 | 2000-06-26 | A method of manufacturing a capacitor for a semiconductor memory device |
| US09/606,097 US6740553B1 (en) | 1999-06-25 | 2000-06-26 | Capacitor for semiconductor memory device and method of manufacturing the same |
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| JPH06244364A (en) * | 1993-02-17 | 1994-09-02 | Nec Corp | Manufacture of semiconductor device |
| KR950034588A (en) * | 1994-03-17 | 1995-12-28 | 오가 노리오 | Tantalum high dielectric material and formation method of high dielectric film and semiconductor device |
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| JPH06244364A (en) * | 1993-02-17 | 1994-09-02 | Nec Corp | Manufacture of semiconductor device |
| KR950034588A (en) * | 1994-03-17 | 1995-12-28 | 오가 노리오 | Tantalum high dielectric material and formation method of high dielectric film and semiconductor device |
| US5677015A (en) * | 1994-03-17 | 1997-10-14 | Sony Corporation | High dielectric constant material containing tantalum, process for forming high dielectric constant film containing tantalum, and semiconductor device using the same |
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