KR100311197B1 - method for preparing self-aligned gate transistor using a low temperature Pd/Ge ohmic electrode - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a self-aligned gate transistor semiconductor device using a low temperature Pd / Ge ohmic electrode. The present invention relates to a method for manufacturing a transistor semiconductor device having a substrate including a GaAs or InP layer. According to the method of the present invention, after fabricating the electrode, Pd and Ge are sequentially deposited and heat-treated to fabricate an ohmic electrode. Thus, the self-aligned gate electrode may be manufactured in a finer pattern.

Description

Method for preparing self-aligned gate transistor using a low temperature Pd / Ge ohmic electrode}

The present invention relates to a method of manufacturing a self-aligned gate transistor device using a low-temperature palladium / germanium (Pd / Ge) ohmic electrode. Specifically, the alignment of the gate electrode is improved by fabricating the gate electrode before the ohmic electrode fabrication process, and the gate A method of manufacturing a transistor device having a self-aligned gate electrode having a finer electrode pattern formed thereon.

As the frequency band for the wireless communication service becomes increasingly high frequency, the communication device manufacturing process becomes more complicated and difficult. In particular, source, gate, and drain electrode formation technology in a PHEMT device, which is used as an amplifier for communication in a high frequency band, is a core process that determines the electrical and frequency characteristics of the device.

PHEMT is a device that can maximize electron mobility by heterogeneous AlGaAs with a large band gap and InGaAs with a small band gap to form quantum wells that trap electrons in the InGaAs layer. At this time, the amount of current is determined by controlling the electrons flowing through the source-drain electrode making the ohmic contact by applying a voltage to the gate electrode making the Schottky contact with the semiconductor. Therefore, the contact resistance of the ohmic electrode is not only a direct current (DC) characteristic such as the drain current, the transconductance and the knee voltage of the device, but also the signal gain and power added efficiency of the device. It has a decisive influence on the frequency characteristics of the lamp. Therefore, in order to improve the electrical and frequency characteristics of the device, the source-drain ohmic electrode interval is gradually narrowed, and the length of the gate electrode formed between the ohmic electrodes is gradually sub-micron. Therefore, the technique of fabricating and aligning fine gate electrodes between narrow source-drain electrodes is very important for determining the reproducibility and characteristics of the device.

Conventional PHETM devices are fabricated by depositing source, drain, and ohmic metals after mesa etching for device isolation and heat treatment to form ohmic contacts and then forming gate electrodes (see FIGS. 1 and 2). 1 is a method for manufacturing a PHEMT device according to the conventional method. First, the device is etched to a buffer layer using a wet etching method to separate the device (1a), and Au / Ge / Ni / Au is used to form an ohmic contact in an electron beam deposition apparatus (e-). After deposition with a beam evaporator (2b), rapid thermal treatment is performed to form ohmic contacts (1c). Subsequently, a gate pattern is formed by shape inversion lithography to perform gate recess etching, and then Ti / Pt / Au is deposited using an electron beam deposition apparatus (1d).

At this time, in the case of the AuGe-based metal film used as the ohmic electrode, it is formed in a wet process by performing a high temperature heat treatment of 400 ° C. or higher, so that the AuGe metal diffuses not only in the depth direction but also in the lateral direction to narrow the width between the source electrode and the drain electrode. . In addition, a photoresist pattern for forming a gate electrode is formed between the source electrode and the drain electrode, and the gap between the ohmic electrodes becomes narrower after the heat treatment, and thus there are many difficulties in aligning the fine gate pattern. In addition, photoresist patterns by lithography are more finely formed on smooth substrates. However, in the conventional process, after forming the source and drain ohmic electrodes, a fine gate pattern must be formed on the substrate having the step difference, so that the fine pattern of the gate is difficult to form and the reproducibility of the process is inferior.

Accordingly, the present inventors have continued their intensive research and found that the above problems can be solved by performing the gate electrode process before the ohmic electrode process by reversing the order of the conventional ohmic electrode forming process and the gate electrode forming process. It was completed.

An object of the present invention relates to a method of manufacturing a self-aligned gate transistor device in which the degree of alignment of the gate electrode is improved, and the gate electrode pattern can be formed more finely.

1 is a process flowchart for manufacturing a conventional pseudomorphic high electron mobility transistor (PHEMT) device,

2 is a schematic diagram showing the structure of a GaAs / AlGaAs / InGaAs PHEMT substrate and a conventional Au / Ge / Ni / Au ohmic metal layer formed thereon;

3 is a flow chart of a PHEMT device manufacturing process according to the present invention,

4 is a schematic diagram showing a GaAs / AlGaAs / InGaAs PHEMT substrate and the Pd / Ge ohmic electrode layer structure of the present invention formed thereon;

5 is a graph showing a change in ohmic contact resistance according to a heat treatment temperature in the low temperature ohmic electrode (■: Pd / Ge) of the present invention and the ohmic electrode (▲: Au / Ge / Ni / Au) of the conventional method,

6 is a graph showing changes in the interfacial structure of the ohmic electrode of the present invention before and after heat treatment analyzed by X-ray diffraction method (■: before heat treatment (Pd), □: after heat treatment (Pd / Ge)).

7A and 7B show the interface structure change of the ohmic electrode of the present invention before and after heat treatment observed with a cross-sectional transmission electron microscope, respectively (FIG. 7A: before heat treatment and FIG. 7B: after heat treatment),

8A and 8B are schematic diagrams showing the interface structure change of the ohmic electrode of the present invention before and after heat treatment, respectively (FIG. 8A: before heat treatment and FIG. 8B: after heat treatment),

9 is a schematic diagram showing the change of the band diagram at the metal / semiconductor interface of the ohmic electrode of the present invention before (9a) and (9b) after the heat treatment,

10A and 10B are graphs illustrating changes in drain current and transconductance according to the drain voltage of the ohmic electrode of the present invention, respectively.

11A and 11B are graphs illustrating changes in drain current and transconductance according to the drain voltage of an ohmic electrode used in the related art, respectively.

12 is a graph showing the frequency characteristics of the self-aligned gate PHEMT element (●) of the present invention and the PHEMT element (▲) of the prior art.

In order to achieve the above object, in the present invention, in the method of manufacturing a transistor semiconductor device having a substrate including a GaAs or InP layer, after fabricating a gate electrode, Pd and Ge are sequentially deposited and heat treated to produce an ohmic electrode. It provides a method for manufacturing a semiconductor device.

Hereinafter, the present invention will be described in more detail.

The transistor device to which the present invention is applicable is a non-normal high electron mobility transistor having a substrate composed of GaAs / Al _x Ga _lx As / In _y Ga _1-y As (where x and y are numbers of 0.1 to 0.5) Pseudomorphic high electron Mobility transistor: PHEMT), n-type AlGaAs / Al _x Ga _lx as / GaAs (wherein, x is the normal form high electron mobility having a substrate consisting of a number from 0.1 to 0.5) Fig transistor (Normal high electron Mobility transistor: NHEMT), metal semiconductor field effect transistors having substrates composed of high concentration n-type GaAs / n-type GaAs / semi-insulating GaAs, and the like, and those having substrates including GaAs layers. Moreover, it is applicable also when using the board | substrate containing an InP layer.

In the present invention, since the gate electrode is manufactured before the ohmic electrode, the difficulty of aligning the gate electrode between the ohmic electrodes can be overcome. Therefore, since there is no step difference due to the ohmic electrode, a photoresist pattern for forming the gate electrode may be more finely formed.

In the case of using the process of the present invention in which the ohmic electrode is fabricated after the gate electrode is fabricated, the heat treatment for forming the ohmic contact should be performed at a low temperature process that does not degrade the Schottky characteristics of the gate electrode. Schottky properties of gates are reported not to deteriorate below 325 ° C. (see JL Lee, JK mun, and BT Lee, J. Appl. Phys. , 82, 5011 (1997)). Since the AuGe-based ohmic electrode mainly used in the existing PHEMT device process has a heat treatment temperature of 400 ° C. or higher, it is impossible to manufacture the gate electrode before the ohmic electrode. Therefore, in manufacturing a self-aligned PHEMT device according to the present invention, an ohmic electrode making ohmic contact at 300 ° C. or lower should be used.

Unlike the AuGe-based ohmic electrode that uses a wet process, the Pd / Ge ohmic electrode is formed by solid phase regrowth, so the uniformity and reproducibility of ohmic contact resistance are excellent, and the temperature at which the ohmic contact is formed is high. Since it is lower than 300 ° C, the Schottky characteristic of the gate electrode does not deteriorate even if the ohmic heat treatment is performed after the gate electrode and the ohmic electrode are manufactured, and thus the present invention is applied to fabricating a self-aligned gate PHEMT device according to the present invention. (ED Marshall, B. Zhang, LC Wang, PF Jiao, WZ Chen, T. Sawada, KL Kavanagh and TF Kuech, J. Appl. Phys. , 62, 942 (1987)).

3 is a process flowchart for manufacturing a PHEMT device according to the present invention. The mesa etching process 3a for device isolation in FIG. 3 is the same as the conventional process shown in FIG. 1A. The ohmic electrode and gate electrode forming process is reversed from the conventional process sequence (1b, 1c and 1d in FIG. 1). That is, after forming a gate pattern by shape inversion lithography and etching the gate recess, Ti / Pt / Au is deposited using an e-beam evaporator (3b). In this case, the gate recess etching may be performed using a citric acid-based solution capable of selectively etching only the n ⁺ -GaAs layer. The citric acid solution that can be used in the present invention is preferably a mixed solution of 50% aqueous citric acid solution and hydrogen peroxide.

Subsequently, Pd / Ge is deposited 3c by an electron beam deposition apparatus for ohmic contact, followed by heat treatment 3d to form ohmic contact. Here, the Pd layer is in the range of 100 to 3000 Pa, the Ge layer is preferably in the range of 200 to 6000 Pa, and the heat treatment is preferably performed at 200 to 325 ° C for 10 seconds to 20 minutes.

According to the present invention, in contrast to the conventional process, since the gate electrode is manufactured before the ohmic electrode is formed, the degree of alignment between the electrodes can be improved, and since the gate shape inversion pattern is formed on the smooth substrate without the ohmic electrode, a finer gate pattern can be obtained. have.

The present invention will be described in more detail with reference to the following examples. However, the scope of the present invention is not limited only to the following Examples.

Comparative example

A PHEMT device was fabricated according to the conventional method shown in FIG.

An AlGaAs / GaAs superlattice was used as a buffer layer on an SI GaAs substrate having a thickness of 635 μm, and an InGaAs layer was used as a channel layer. An n ⁺ -GaAs layer was used to reduce ohmic contact resistance. In addition, an n-type AlGaAs supply layer was used to form a gate electrode after the gate recess selective etching process for selectively removing the n ⁺ -GaAs layer of the surface layer.

First, using a wet etching method to etch the buffer layer to separate the device and the device, and deposited Au / Ge / Ni / Au by an electron beam deposition apparatus to form an ohmic contact, and then rapid heat treatment at 460 ℃ for 20 seconds To form an ohmic contact. The ohmic metal layer structure was Au (1000 Pa) / Ni (200 Pa) / Ge (400 Pa) / Au (500 Pa).

Subsequently, when the device is heat-treated, Au reacts with Ge deposited together and rapidly diffuses and penetrates into the substrate in a liquid state. Since the Au layer reacts with the PHEMT substrate to form an AuGa phase, it is possible to generate Ga cavities at the interface of the electrode layer and at the same time, to release electrons while Ge is substituted with Ga cavities. Ohmic contacts at the interface are formed.

Subsequently, a gate pattern was formed by shape inversion lithography, followed by gate recess etching, and the gate electrode Ti / Pt / Au was deposited by an electron beam deposition apparatus.

The ohmic electrode structure and the AlGaAs / lnGaAs PHEMT substrate structure of the conventional method thus produced are shown in FIG. 2.

Example

A PHEMT device was fabricated according to the method of the present invention shown in FIG.

An AlGaAs / GaAs superlattice was used as a buffer layer on an SI GaAs substrate having a thickness of 635 μm, and an InGaAs layer was used as a channel layer. An n ⁺ -GaAs layer was used to reduce ohmic contact resistance. In addition, an n-type AlGaAs supply layer was used to form a gate electrode after the gate recess selective etching process for selectively removing the n ⁺ -GaAs layer of the surface layer.

First, the device is etched to the buffer layer using a wet etching method, and the device and the device are separated, and a gate pattern is formed by forming a gate pattern by shape inversion lithography, and then Ti / Pt / Au is transferred to an electron beam evaporator (e-beam evaporator). ), (FIG. 3B). Gate recess etching was carried out using a 1.5: 1 mixed solution of hydrogen peroxide and a 50% aqueous citric acid solution which can selectively etch only the n ⁺ -GaAs layer.

Subsequently, Pd / Ge was deposited by an electron beam evaporation apparatus (FIG. 3C) for ohmic contact, and then thermally treated at 300 ° C. for 1 minute (FIG. 3D) to form ohmic contact. The ohmic metal layer structure was Pd (500 mW) / Ge (1000 mW).

During deposition, Pd reacts with GaAs to form Pd _x GaAs ternary compounds, and during heat treatment, Ge reacts with Pd to form PdGe. At this time, the excess Ge remaining after reacting with Pd reacts with ternary compounds generated on the substrate to form recrystallized GaAs, and Ge is doped into the produced recrystallized GaAs to form a high concentration of an electron layer on the surface of the substrate, thereby forming a metal / semiconductor. Forming ohmic contact at the interface Since the heat treatment temperature for ohmic contact is made at a low temperature below 300 ° C, ohmic contact is formed by solid phase regrowth through an interfacial reaction between the ohmic metal layer and the substrate. Therefore, reproducibility of ohmic characteristics can be obtained because diffusion in the depth direction and the lateral direction is suppressed.

5 illustrates a change in contact resistance according to the temperature of the Pd / Ge ohmic electrode (■) of the present invention and the conventional Au / Ge / Ni / Au ohmic electrode (▲). The Pd / Ge ohmic electrode started to exhibit ohmic behavior at 250 ° C., and the contact resistance decreased according to the heat treatment temperature. Thus, a contact resistance of 1.2 × 10 ⁻⁷ μm 2 at 300 ° C. was obtained, and the value was maintained at 325 ° C. The Au / Ge / Ni / Au ohmic electrode started to exhibit ohmic behavior from 380 ℃, showed a minimum contact resistance of 3.2 x 10 ^-6 Ω㎠ at 500 ℃, and maintained a constant level up to 540 ℃. From this, it can be seen that the contact resistance of the Pd / Ge ohmic electrode of the present invention formed by heat treatment at 300 ° C., which is about 120 ° C. lower than that of the conventional Au / Ge / Ni / Au ohmic electrode, is low as about 1/30.

6 shows the structural change at the interface before and after the heat treatment of the Pd / Ge ohmic electrode of the present invention (■: before heat treatment (Pd), □: after heat treatment (Pd / Ge)). The interfacial structure was analyzed by X-ray diffraction. Only the Pd peak (■) was detected in the deposited thin film state before the heat treatment, and the Ge peak was not observed. This is because when Ge is deposited by the electron beam, it is deposited in an amorphous state. After heat treatment at 300 ° C. for 1 minute, Pd and Ge completely reacted to observe a Pd / Ge phase (□).

7A and 7B show the interfacial structures before and after the heat treatment of the Pd / Ge ohmic electrodes prepared in the examples of the present invention, which were analyzed by a cross-sectional transmission electron microscope, respectively. Before the heat treatment, it was confirmed that the deposited Pd reacted with the GaAs substrate to form a 150 _x thick Pd _x GaAs ternary compound at the interface between the Pd and GaAs substrates. After heat treatment at 300 ° C. for 1 minute, Pd was phase-transformed into Ge and the reaction PdGe phase to confirm that an epi-Ge layer was formed between PdGe and the substrate. 8A and 8B show schematic views of FIGS. 7A and 7B. Ternary compound, which is produced on the substrate is a phase separation as recrystallization GaAs, at the same time to move to the remaining surplus Ge PdGe after forming recrystallization of the sum GaAs layer, PdGe / GaAs interface is epi-Ge layer with a high concentration of the n ⁺ -GaAs layer Is formed, and ohmic contact is formed at the metal-semiconductor interface.

9 is a change in band diagram at the metal-semiconductor interface before (9a) and (9b) before and after heat treatment of the Pd / Ge ohmic electrode of the present invention. Prior to the heat treatment, the Pd / Ge ohmic metal rearranges the carriers due to the junction with the GaAs semiconductor. As a result, a potential difference occurs at the interface to form a barrier and a depleted layer of depleted charge (9a). After the heat treatment, Ge is doped into the recrystallized GaAs so that a high concentration of n ⁺ -GaAs layer is formed on the substrate, and thus the width of the depletion layer is rapidly reduced to form an ohmic contact by tunneling electrons (9b). The relationship between the tunneling current and the thickness of the depletion layer is shown in Equation 1 below.

Where I is the tunneling current, W is the thickness of the depletion layer, m _n is the effective electron concentration, and Φ _BM is the barrier height. Therefore, if the barrier height is constant, as the thickness of the depletion layer decreases, the current due to tunneling increases to form ohmic contact.

10A and 10B are graphs illustrating changes in drain current and transconductance according to the drain voltage of the ohmic electrode of the present invention, respectively. FIGS. 11A and 11B are respectively corresponding to the drain voltage of the ohmic electrode manufactured in a comparative example according to the prior art. A graph showing changes in drain current and transconductance. The self-aligned gate PHEMT of the present invention has more accurate alignment between the source-gate and drain electrodes than the conventional PHEMT, and can more easily form the gate electrode. That is, the maximum transconductance of the PHEMT device of the present invention was 381 mmS / mm, the drain conductance was O.lmS, and the knee voltage was 0.2V. On the other hand, in the prior art shown in Figs. 11A and 11B, the maximum transconductance is 347 mmS / mm, the drain conductance is 10 mS, and the knee voltage is 0.25V, which is poor in comparison with the device of the present invention.

12 shows the frequency of a self-aligned gate PHEMT device (●) utilizing the Pd / Ge ohmic electrode of the present invention and a PHEMT device (▲) using the conventional Au / Ge / Ni / Au ohmic electrode. It is a characteristic comparison. The maximum cut-off frequency f _T (major depth when the gain is 0) is 18 GHZ for the self-aligned gate PHEMT of the present invention and 6.5 GHZ for the conventional PHEMT. Self-aligned PHEMT devices showed better characteristics. This supports that the contact resistance characteristic of the Pd / Ge ohmic electrode is superior to the Au / Ge-based ohmic electrode of Au / Ge / Ni / Au.

According to the method of the present invention, by forming the gate electrode before forming the ohmic electrode, a PHEMT semiconductor device having a gate electrode self-aligned in a finer pattern can be manufactured, and the PHEMT device of the present invention has improved contact resistance and frequency characteristics for communication. It can be usefully used for the device.

Claims (4)

CLAIMS 1. A method of manufacturing a transistor semiconductor device having a substrate comprising a GaAs or InP layer, comprising: performing a mesa etching process for device isolation; Forming a gate pattern and performing gate recess etching, and then depositing Ti, Pt, and Au in order to form a gate electrode; And sequentially depositing Pd and Ge, followed by heat treatment to fabricate a cathode-drain ohmic electrode. The method of claim 1, And said transistor semiconductor element is an irregular high electron mobility transistor, a normal high electron mobility transistor, or a metal semiconductor field effect transistor. The method of claim 1, Wherein the heat treatment is performed at 200 to 325 ° C. for 10 seconds to 20 minutes. The method of claim 1, Wherein the deposited Pd layer has a thickness of 100-3000 mm 3 and the Ge layer has a thickness of 200-6000 mm 3.