RU2745589C1 - Semiconductor device manufacturing method - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention relates to the field of semiconductor device manufacturing technology, in particular to the devices with reduced contact resistance manufacturing technology. On GaAs plates after formation of active regions of the semiconductor device, Pd/Ni/Ge contacts are formed by successive application in a vacuum at pressure of 10^-5 Pa of a germanium (Ge) layer with thickness of 20 nm at a deposition rate of 3 nm / s, nickel (Ni) layer with thickness of 15 nm at deposition rate of 1 nm/s, palladium layer (Pd) with thickness of 50 nm at deposition rate of 0.5 nm/s at substrate temperature of 100 °C with subsequent heat treatment at temperature 450 °C in forming gas for 2 minutes. Then Au is applied, by standard technology, with thickness of 100 nm and annealing is performed at temperature 400 °C for 30 s in hydrogen atmosphere.

EFFECT: technical result consists in reduction of contact resistance, provision of manufacturability, improvement of parameters of devices, improvement of quality and increase of percentage yield.

1 cl, 1 tbl

Description

The invention relates to the field of technology for the production of semiconductor devices, in particular to the technology of manufacturing devices with low contact resistance.

A known method of manufacturing a semiconductor device [US Patent 5323053, MKI H01L 29/48] with improved characteristics of contacts to the drain / source areas. In the n ⁺ drain / source regions in the p-type silicon substrate with the (100) orientation, V-grooves are etched, on the (111) - walls of which epitaxial layers of yttrium silicide are grown. These layers with low Schottky barrier heights provide low contact resistances. In such devices, due to the low manufacturability of the yttrium silicide formation process, the characteristics of the devices deteriorate and the leakage currents increase.

A known method of manufacturing a semiconductor device [US Patent No. 5345108, MKI H01L 23/48] with multilayer conductors, where layers of Al-Si-Cu alternate with layers of TiN. At the interfaces between the layers, the interaction of Ti and Al occurs and intermetallic compounds are formed, which envelop the metal grains in a very thin layer and separate the structural layers of the conductors, which sharply increases their resistance to the formation of tubercles and the formation of breaks due to electromigration.

The disadvantages of this method are:

- high contact resistance;

- low manufacturability;

- increased density of defects.

The problem solved by the invention: reducing the contact resistance, ensuring manufacturability, improving the parameters of devices, improving the quality and increasing the percentage of the yield of suitable

The problem is solved by forming a Pd / Ni / Ge contact by sequential deposition in a vacuum at a pressure of 10 ^-5 Pa of a germanium (Ge) layer 20 nm thick with a deposition rate of 3 nm / s, a nickel (Ni) layer 15 nm thick with a deposition rate of 1 nm / s , a palladium (Pd) layer 50 nm thick with a deposition rate of 0.5 nm / s at a substrate temperature of 100 ° C, followed by heat treatment at 450 ° C in forming gas for 2 min.

The technology of the method is as follows: after creating active regions of a semiconductor device, Pd / Ni / Ge contacts were formed on GaAs wafers by sequential deposition in vacuum at a pressure of 10 ^-5 Pa of a germanium (Ge) layer 20 nm thick with a deposition rate of 3 nm / s, a nickel layer (Ni) with a thickness of 15 nm with a deposition rate of 1 nm / s, a palladium (Pd) layer with a thickness of 50 nm with a deposition rate of 0.5 nm / s at a substrate temperature of 100 ° C, followed by heat treatment at a temperature of 450 ° C in a forming gas in within 2 min. Then Au was deposited according to the standard technology, with a thickness of 100 nm, and annealing was carried out at a temperature of 400 ° C for 30 s in a hydrogen atmosphere.

According to the proposed method, semiconductor devices were manufactured and investigated.

The processing results are presented in the table.

Experimental studies have shown that the yield of suitable structures for batches of plates formed in the optimal mode increased by 18.9%.

EFFECT: reduced contact resistance, ensuring manufacturability, improving the parameters of structures, improving quality and increasing the percentage of yield.

The stability of the parameters over the entire operating temperature range was normal and met the requirements.

The proposed method of manufacturing a semiconductor device by forming a Pd / Ni / Ge contact by sequential deposition in vacuum at a pressure of 10 ^-5 Pa of a germanium (Ge) layer 20 nm thick with a deposition rate of 3 nm / s, a nickel (Ni) layer 15 nm thick with a deposition rate 1 nm / s, a palladium (Pd) layer 50 nm thick with a deposition rate of 0.5 nm / s at a substrate temperature of 100 ° C, followed by heat treatment at a temperature of 450 ° C in a forming gas for 2 minutes, devices and will improve their reliability.

Claims (1)

A method for manufacturing a semiconductor device, including a substrate, processes for creating active regions, a field oxide, contacts to active regions, characterized in that the contacts are formed by sequential deposition in a vacuum at a pressure of 10 ^-5 Pa of a germanium (Ge) layer 20 nm thick with a deposition rate of 3 nm / s, a nickel (Ni) layer 15 nm thick with a deposition rate of 1 nm / s, a palladium (Pd) layer 50 nm thick with a deposition rate of 0.5 nm / s at a substrate temperature of 100 ° C, followed by heat treatment at a temperature of 450 ° C in forming gas for 2 minutes.