RU2757176C1 - Method for manufacturing a semiconductor device with multilayer conductors - Google Patents
Method for manufacturing a semiconductor device with multilayer conductors Download PDFInfo
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- RU2757176C1 RU2757176C1 RU2021108857A RU2021108857A RU2757176C1 RU 2757176 C1 RU2757176 C1 RU 2757176C1 RU 2021108857 A RU2021108857 A RU 2021108857A RU 2021108857 A RU2021108857 A RU 2021108857A RU 2757176 C1 RU2757176 C1 RU 2757176C1
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- deposition
- thickness
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- film
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000004020 conductor Substances 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 title claims description 5
- 230000008021 deposition Effects 0.000 claims abstract description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052737 gold Inorganic materials 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Изобретение относится к области технологии производства полупроводниковых приборов, в частности к технологии изготовления многослойных проводников с пониженным значением контактного сопротивления.The invention relates to the field of technology for the production of semiconductor devices, in particular to the technology of manufacturing multilayer conductors with a reduced value of contact resistance.
Известен способ изготовления контакта [Пат. 5317187 США, МКИ H01L 49/00] между проводящими элементами, расположенными на различных уровнях. В диэлектрическом слое создают сквозное окно. Затем проводят последовательное нанесение слоев Ti/TiN/Ti. Далее осуществляют термообработку структуры, в результате чего на границе раздела металл/полупроводник образуется силицид титана. Для снижения сопротивления контакта поверх Ti наносят слой Al. В таких приборах из-за не технологичности формирования в диэлектрическом слое сквозного окна образуется большое количество дефектов, которые ухудшают электрические параметры приборов.A known method of making a contact [US Pat. 5317187 USA, MKI H01L 49/00] between conductive elements located at different levels. A through window is created in the dielectric layer. Then, sequential Ti / TiN / Ti layers are deposited. Next, the structure is heat treated, as a result of which titanium silicide is formed at the metal / semiconductor interface. To reduce the contact resistance, an Al layer is applied on top of the Ti. In such devices, due to the non-manufacturability of formation in the dielectric layer of the through window, a large number of defects are formed, which worsen the electrical parameters of the devices.
Известен способ изготовления полупроводникового прибора с многослойными проводниками [Пат. 5345108 США, МКИ H01L 23/48], где слои AlSiCu чередуются со слоями TiN. На границах раздела слоев происходит взаимодействие Ti с Al и образуются интерметаллические соединения, которые очень тонким слоем обволакивают металлические зерна и разделяют структурные слои проводников.A known method of manufacturing a semiconductor device with multilayer conductors [US Pat. 5345108 USA, MKI H01L 23/48], where AlSiCu layers alternate with TiN layers. At the interfaces between the layers, Ti interacts with Al and intermetallic compounds are formed, which envelop the metal grains in a very thin layer and separate the structural layers of the conductors.
Недостатками этого способа являются:The disadvantages of this method are:
- высокие значения контактного сопротивления;- high values of contact resistance;
- высокая дефектность;- high defectiveness;
- низкая технологичность.- low manufacturability.
Задача, решаемая изобретением: снижение контактного сопротивления, обеспечение технологичности, улучшение параметров приборов, повышение качества и увеличение процента выхода годных.The problem solved by the invention: reducing the contact resistance, ensuring manufacturability, improving the parameters of devices, improving the quality and increasing the percentage of yield.
Задача решается формированием контактов Au/Pd/Ni/Ge путем последовательного осаждения пленки Ge толщиной 20 нм при давлении 1*10-5 Па, скоростью осаждения 3 нм/с, пленки никеля Ni толщиной 15 нм в вакууме 1*10-5 Па, со скоростью роста 1 нм/с, последующим осаждением слоя Pd толщиной 50 нм при давлении 1*10-5 Па, скоростью осаждения 0,5 нм/с, и Au толщиной 100 нм, термообработкой при температуре 450°С в течение 2,5 мин, в атмосфере форминг газе.The problem is solved by forming Au / Pd / Ni / Ge contacts by sequential deposition of a Ge film with a thickness of 20 nm at a pressure of 1 * 10 -5 Pa, a deposition rate of 3 nm / s, a nickel Ni film with a thickness of 15 nm in a vacuum of 1 * 10 -5 Pa, with a growth rate of 1 nm / s, followed by deposition of a 50 nm thick Pd layer at a pressure of 1 * 10 -5 Pa, a deposition rate of 0.5 nm / s, and Au with a thickness of 100 nm, heat treatment at 450 ° C for 2.5 min, in a forming gas atmosphere.
По предлагаемому способу были изготовлены и исследованы полупроводниковые приборы. Результаты обработки представлены в таблице.According to the proposed method, semiconductor devices were manufactured and investigated. The processing results are presented in the table.
Экспериментальные исследования показали, что выход годных структур на партии пластин, сформированных в оптимальном режиме, увеличился на 23,1%.Experimental studies have shown that the yield of suitable structures for batches of plates formed in the optimal mode increased by 23.1%.
Технический результат: снижение контактного сопротивления, обеспечение технологичности, улучшение параметров приборов, повышение качества и увеличения процента выхода годных.EFFECT: lowering contact resistance, ensuring manufacturability, improving the parameters of devices, improving quality and increasing the percentage of yield.
Стабильность параметров во всем эксплуатационном интервале температур была нормальной и соответствовала требованиям.The stability of the parameters over the entire operating temperature range was normal and met the requirements.
Предложенный способ изготовления полупроводникового прибора с многослойными проводниками формированием контактов Au/Pd/Ni/Ge путем последовательного осаждения пленки Ge толщиной 20 нм при давлении 1*10-5 Па, скоростью осаждения 3 нм/с, пленки никеля Ni толщиной 15 нм в вакууме 1*10-5 Па, со скоростью роста 1 нм/с, последующим осаждением слоя Pd толщиной 50 нм при давлении 1*10-5 Па, скоростью осаждения 0,5 нм/с, и Au толщиной 100 нм, термообработкой при температуре 450°С в течение 2,5 мин, в атмосфере форминг газа, позволяет повысит процент выхода годных приборов и улучшит их надежность.The proposed method for manufacturing a semiconductor device with multilayer conductors by forming Au / Pd / Ni / Ge contacts by sequential deposition of a Ge film with a thickness of 20 nm at a pressure of 1 * 10 -5 Pa, a deposition rate of 3 nm / s, a nickel Ni film with a thickness of 15 nm in vacuum 1 * 10 -5 Pa, with a growth rate of 1 nm / s, followed by deposition of a Pd layer 50 nm thick at a pressure of 1 * 10 -5 Pa, a deposition rate of 0.5 nm / s, and Au with a thickness of 100 nm, heat treatment at 450 ° With for 2.5 minutes, in a gas forming atmosphere, it will increase the yield of suitable devices and improve their reliability.
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RU2021108857A RU2757176C1 (en) | 2021-03-31 | 2021-03-31 | Method for manufacturing a semiconductor device with multilayer conductors |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2791442C1 (en) * | 2022-11-11 | 2023-03-07 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method for manufacturing of a semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5192994A (en) * | 1989-08-30 | 1993-03-09 | Mitsubishi Kasei Polytec Co. | Au-ge-ni ohmic contact for ga-al-as compound semiconductor |
US5317187A (en) * | 1992-05-05 | 1994-05-31 | Zilog, Inc. | Ti/TiN/Ti contact metallization |
US5345108A (en) * | 1991-02-26 | 1994-09-06 | Nec Corporation | Semiconductor device having multi-layer electrode wiring |
US5367195A (en) * | 1993-01-08 | 1994-11-22 | International Business Machines Corporation | Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal |
RU2407104C1 (en) * | 2009-08-03 | 2010-12-20 | Закрытое акционерное общество "Научно-производственная фирма Микран" | METHOD OF MAKING MULTILAYER OHMIC CONTACT TO n-GaAs |
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2021
- 2021-03-31 RU RU2021108857A patent/RU2757176C1/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5192994A (en) * | 1989-08-30 | 1993-03-09 | Mitsubishi Kasei Polytec Co. | Au-ge-ni ohmic contact for ga-al-as compound semiconductor |
US5345108A (en) * | 1991-02-26 | 1994-09-06 | Nec Corporation | Semiconductor device having multi-layer electrode wiring |
US5317187A (en) * | 1992-05-05 | 1994-05-31 | Zilog, Inc. | Ti/TiN/Ti contact metallization |
US5367195A (en) * | 1993-01-08 | 1994-11-22 | International Business Machines Corporation | Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal |
RU2407104C1 (en) * | 2009-08-03 | 2010-12-20 | Закрытое акционерное общество "Научно-производственная фирма Микран" | METHOD OF MAKING MULTILAYER OHMIC CONTACT TO n-GaAs |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2791442C1 (en) * | 2022-11-11 | 2023-03-07 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method for manufacturing of a semiconductor device |
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