RU2674413C1 - Method for making semiconductor device - Google Patents

Abstract

FIELD: instrumentation; technological processes.SUBSTANCE: invention relates to the field of manufacturing technology of semiconductor devices, in particular, to the technology of manufacturing a gate dielectric with a low defect density. Technology of the method consists in the following: tantalum film with a thickness of 28 nm is formed on a p-type silicon wafer with orientation (100) with a deposition rate of 30 nm/min, on a substrate heated to 70 °C, in vacuum at a pressure of 10–10mmHg. Carry out the oxidation in oxygen at a temperature of 530 °C for 15 min and form the oxide of tantalum TaO60 nm thick, followed by thermal annealing at 700 °C in an inert atmosphere for 5 min. Improvement of the semiconductor structure parameters is due to the fact that tantalum oxide TaOcontains electronic traps. Improved structure, reduced number of traps for charge carriers near the interface is provided. Active areas of the semiconductor device are formed in a standard way.EFFECT: invention provides a decrease in the density of defects, an increase in processability, an improvement in the parameters of devices, an increase in quality, and an increase in the percentage of yield.1 cl, 1 tbl

Description

The invention relates to the field of production technology of semiconductor devices, in particular to a technology for manufacturing a gate dielectric with a reduced defect density.

A known method of manufacturing a semiconductor device [US Pat. 4985739 USA, MKI HO1L 29/80] by forming the upper and lower isolating gates from each other. Field effect transistors use a structure in which one system of drain-source regions surrounds another system of drain-source regions. The lower shutter - hidden, the upper - is connected to the contact area through a diffusion barrier to prevent the penetration of metal into the structure. The channel region in the shielding region is formed by ion implantation. In such semiconductor structures, due to the occurrence of mechanical stresses, the parameters of the devices deteriorate.

A known method of manufacturing a semiconductor device [US Pat. 5100820 USA, MKI HOIL 21/336] in which the surface of the p-silicon substrate containing the insulating regions of the oxide protective layer is sequentially coated with layers of gate silicon oxide, an n + type gate of polycrystalline silicon and upper silicon oxide. The future shutter area is masked by a layer of silicon nitride. The structure undergoes thermal oxidation in moist oxygen at elevated pressure and subsequently forms a shutter layer. The structure is sequentially implanted with arsenic ions using protective silicon oxide and silicon nitride layers as a mask to form n + source-drain areas, and then p + ions to form n-source drain areas with a smooth doping profile. The surface is passivated by a layer of borophosphorosilicate glass, in which contact windows for aluminum are opened.

The disadvantages of the method are:

- increased density of defects in semiconductor structures;

- formation of mechanical stresses;

- low manufacturability.

The problem solved by the invention: reducing the density of defects, ensuring manufacturability, improving the parameters of devices, improving quality and increasing the percentage of yield.

The problem is solved by creating a gate dielectric by forming a 28 nm thick tantalum film with a deposition rate of 30 nm / min on a substrate heated to 70 ° C in vacuum at a pressure of 10 ^-6 -10 ^-7 mm Hg. on a p-type silicon wafer with a (100) orientation followed by oxidation in oxygen at a temperature of 530 ° C for 15 min. and the formation of tantalum oxide Ta ₂ O ₅ with a thickness of 60 nm, followed by thermal annealing at a temperature of 700 ° C in an inert medium for 5 min.

The technology of the method consists in the following: on a p-type silicon wafer with a (100) orientation, a tantalum film of 28 nm thickness is formed with a deposition rate of 30 nm / min, heated to a substrate at 70 ° C, in a vacuum at a pressure of 10 ^-6 -10 ^{- 7} mmHg Art. Then carry out the oxidation in oxygen at a temperature of 530 ° C for 15 minutes and form tantalum oxide Ta ₂ C ₅ with a thickness of 60 nm, followed by thermal annealing at a temperature of 700 ° C in an inert medium for 5 minutes. The improvement in the parameters of the semiconductor structure is due to the fact that tantalum oxide Ta ₂ O ₅ contains electronic traps. All this improves the structure, reduces the number of traps for charge carriers near the interface. Active areas of the semiconductor device were formed in a standard way.

According to the proposed method, semiconductor devices were manufactured and investigated. The processing results are presented in Table 1.

Experimental studies have shown that the yield of suitable semiconductor devices on a batch of wafers formed in the optimal mode increased by 15.5%.

Effect: reducing the density of defects, ensuring manufacturability, improving the parameters of structures, improving quality and increasing the percentage of yield.

The stability of the parameters over the entire operating temperature range was normal and consistent with the requirements.

The proposed method of manufacturing a semiconductor device can increase the percentage of suitable devices and improve their reliability.

Claims (1)

A method of manufacturing a semiconductor device, including processes for the formation of drain, source, gate and gate dielectric regions, characterized in that the gate dielectric is formed by creating a tantalum film 28 nm thick with a deposition rate of 30 nm / min on a substrate heated to 70 ° C in vacuum at a pressure of 10 ^-6 -10 ^-7 mm Hg on a silicon wafer, followed by oxidation in oxygen at a temperature of 530 ° C for 15 min and the formation of tantalum oxide Ta ₂ O ₅ with a thickness of 60 nm, followed by thermal annealing at a temperature of 700 ° C in an inert medium for 5 min.