KR100310380B1 - 집적회로 - Google Patents
집적회로 Download PDFInfo
- Publication number
- KR100310380B1 KR100310380B1 KR1019960014363A KR19960014363A KR100310380B1 KR 100310380 B1 KR100310380 B1 KR 100310380B1 KR 1019960014363 A KR1019960014363 A KR 1019960014363A KR 19960014363 A KR19960014363 A KR 19960014363A KR 100310380 B1 KR100310380 B1 KR 100310380B1
- Authority
- KR
- South Korea
- Prior art keywords
- signal generator
- input
- buffer circuit
- configuration signal
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
- H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP95106850.1 | 1995-05-05 | ||
| EP19950106850 EP0743756B1 (de) | 1995-05-05 | 1995-05-05 | Konfigurierbare integrierte Schaltung |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960043526A KR960043526A (ko) | 1996-12-23 |
| KR100310380B1 true KR100310380B1 (ko) | 2001-12-17 |
Family
ID=8219229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960014363A Expired - Lifetime KR100310380B1 (ko) | 1995-05-05 | 1996-05-03 | 집적회로 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5726601A (enExample) |
| EP (1) | EP0743756B1 (enExample) |
| JP (1) | JPH08307241A (enExample) |
| KR (1) | KR100310380B1 (enExample) |
| AT (1) | ATE156950T1 (enExample) |
| DE (1) | DE59500516D1 (enExample) |
| TW (1) | TW297936B (enExample) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5051622A (en) * | 1989-11-08 | 1991-09-24 | Chips And Technologies, Inc. | Power-on strap inputs |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4556806A (en) * | 1982-05-10 | 1985-12-03 | Texas Instruments Incorporated | Gate alterable output buffer |
| JPH01289138A (ja) * | 1988-05-16 | 1989-11-21 | Toshiba Corp | マスタースライス型半導体集積回路 |
| JPH07109843B2 (ja) * | 1989-12-28 | 1995-11-22 | 三洋電機株式会社 | 半導体集積回路 |
| JP2563679B2 (ja) * | 1991-01-24 | 1996-12-11 | シャープ株式会社 | 双方向入出力信号分離回路 |
| JPH05136200A (ja) * | 1991-11-14 | 1993-06-01 | Mitsubishi Electric Corp | 半導体集積装置 |
| EP0570158B1 (en) * | 1992-05-08 | 2000-01-19 | National Semiconductor Corporation | Frequency multiplication circuit and method for generating a stable clock signal |
| EP0651513B1 (en) * | 1993-10-29 | 1997-08-06 | STMicroelectronics S.r.l. | Integrated circuit with bidirectional pin |
| JP2684976B2 (ja) * | 1993-11-24 | 1997-12-03 | 日本電気株式会社 | 半導体装置 |
-
1995
- 1995-05-05 AT AT95106850T patent/ATE156950T1/de not_active IP Right Cessation
- 1995-05-05 EP EP19950106850 patent/EP0743756B1/de not_active Expired - Lifetime
- 1995-05-05 DE DE59500516T patent/DE59500516D1/de not_active Expired - Lifetime
-
1996
- 1996-04-11 TW TW85104293A patent/TW297936B/zh not_active IP Right Cessation
- 1996-05-01 JP JP13257696A patent/JPH08307241A/ja not_active Withdrawn
- 1996-05-03 KR KR1019960014363A patent/KR100310380B1/ko not_active Expired - Lifetime
- 1996-05-03 US US08/647,464 patent/US5726601A/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5051622A (en) * | 1989-11-08 | 1991-09-24 | Chips And Technologies, Inc. | Power-on strap inputs |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0743756A1 (de) | 1996-11-20 |
| DE59500516D1 (de) | 1997-09-18 |
| ATE156950T1 (de) | 1997-08-15 |
| HK1000950A1 (zh) | 1998-05-08 |
| TW297936B (enExample) | 1997-02-11 |
| US5726601A (en) | 1998-03-10 |
| JPH08307241A (ja) | 1996-11-22 |
| KR960043526A (ko) | 1996-12-23 |
| EP0743756B1 (de) | 1997-08-13 |
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| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
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St.27 status event code: A-3-3-R10-R17-oth-X000 |
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