KR100309818B1 - Method of manufacturing a capacitor in a FeRAM - Google Patents
Method of manufacturing a capacitor in a FeRAM Download PDFInfo
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- KR100309818B1 KR100309818B1 KR1019980061409A KR19980061409A KR100309818B1 KR 100309818 B1 KR100309818 B1 KR 100309818B1 KR 1019980061409 A KR1019980061409 A KR 1019980061409A KR 19980061409 A KR19980061409 A KR 19980061409A KR 100309818 B1 KR100309818 B1 KR 100309818B1
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- capacitor
- heat treatment
- ferroelectric
- film
- forming
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- 239000003990 capacitor Substances 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims abstract description 69
- 238000010438 heat treatment Methods 0.000 claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 50
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910001260 Pt alloy Inorganic materials 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 229910019899 RuO Inorganic materials 0.000 claims description 2
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 229910010293 ceramic material Inorganic materials 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 229910021521 yttrium barium copper oxide Inorganic materials 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000002425 crystallisation Methods 0.000 claims 1
- 230000008025 crystallization Effects 0.000 claims 1
- 238000011084 recovery Methods 0.000 abstract description 19
- 230000007547 defect Effects 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000000280 densification Methods 0.000 abstract 2
- 239000012212 insulator Substances 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910000575 Ir alloy Inorganic materials 0.000 description 1
- 229910000929 Ru alloy Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 페로일렉트릭 램(FeRAM) 소자의 축전기 제조 방법에 관한 것으로, 축전기 콘택 식각 후 2차 회복 열처리(recovery anneal)시 650 내지 800℃의 고온에서 금속의 높은 이동도(mobility)에 의해 형성되는 금속 상부 전극에 생성되는 홀 결함(hole defect)과 금속 상부 전극의 열팽창에 의해 금속 상부 전극 위에 형성된 축전기 확산 방지막(capacitor level dielectric) 및 축전기 평탄화 절연막(capacitor intermediate level dielectric)에 발생하는 균열(crack)을 방지하여 축전기의 특성 및 수율을 향상시키기 위하여, 본 발명에서는 열공정 방법을 기존에 행하는 2차 회복 열처리를 생략하는 대신 축전기 확산 방지막 및 축전기 평탄화 절연막 형성 후에 열처리를 통하여 선행 공정인 축전기 확산 방지막 및 축전기 평탄화 절연막 형성 공정에서의 강유전체막(ferroelectric film)의 특성 저하를 미리 충분하게 회복시키고, 동시에 상부 전극을 치밀화(densification)시켜 축전기 콘택 식각 시에 식각 충격(etching damage)을 최소화시킬 수 있는 FeRAM 소자의 축전기 제조 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a ferroelectric RAM (FeRAM) device, which is formed by high mobility of a metal at a high temperature of 650 to 800 ° C. during secondary recovery anneal after capacitor contact etching. Hole defects generated in the metal upper electrode and cracks occurring in the capacitor level dielectric and the capacitor intermediate level dielectric formed on the metal upper electrode due to thermal expansion of the metal upper electrode. In order to improve the characteristics and the yield of the capacitor by preventing the present invention, in the present invention, instead of omitting the secondary recovery heat treatment conventionally performed in the thermal process method, the capacitor diffusion barrier film is a preceding process through the heat treatment after the capacitor diffusion barrier film and the capacitor planarization insulating film formed and Characteristics of Ferroelectric Films in Capacitor Flattening Insulator Formation Process And a fully restored in advance, followed by densification (densification) of the upper electrode at the same time is described with respect to a method of manufacturing FeRAM capacitor element to minimize the impact etching (etching damage) at the time of the capacitor contact etch.
Description
본 발명은 페로일렉트릭 램(FeRAM) 소자의 축전기 제조 방법에 관한 것으로, 특히 열공정 방법을 개선하여 축전기 콘택 식각 후 2차 회복 열처리시 금속 상부 전극에 생성되는 홀 결함(hole defect)과 상부 전극 위에 형성된 축전기 확산 방지막 및 축전기 평탄화 절연막에 발생하는 균열(crack)을 방지하여 축전기의 특성 및 수율을 향상시킬 수 있는 FeRAM 소자의 축전기 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a ferroelectric RAM (FeRAM) device, and in particular, to improve the thermal process method, on the upper electrode and hole defects generated in the metal upper electrode during the secondary recovery heat treatment after the capacitor contact etching. The present invention relates to a capacitor manufacturing method of a FeRAM device capable of preventing cracks occurring in the formed capacitor diffusion barrier film and the capacitor planarization insulating film, thereby improving the characteristics and yield of the capacitor.
일반적으로, FeRAM 소자에서 축적기의 강유전체 축전기 재료로 PZT, PLZT, BT, SBT, SBTN 등과 같은 퍼보스키트스(pervoskites) 구조를 갖는 강유전체를 사용하는 경우, 통상적으로 Pt, Ir, Ru, Pt-합금 등의 금속 상부 전극을 사용한다. 이 경우 650 내지 800℃의 고온에서 행하는 회복 열처리시 고온에서 금속의 높은 이동도(mobility)에 의해 금속 상부 전극에 결함이 발생한다. 회복 열처리는 축전기 식각(capacitor etching) 후에 식각 충격(etching damage)에 의해 열화(degradation)된 강유전체 특성을 회복시켜주기 위한 1차 회복 열처리와 축전기 콘택 식각(capacitor contact etching) 후에 식각 충격 및 먼저 진행된 축전기 확산 방지막 (capacitor level dielectric) 및 축전기 평탄화 절연막(intermediate leveldielectric) 형성 공정에서의 수소 충격(hydrogen damage)에 의해 열화된 강유전체막(ferroelectric film)의 특성을 회복시켜주기 위한 2차 회복 열처리로 대별된다. 1차 회복 열처리시에는 주로 금속 상부 전극의 수축(shrinkage)이 발생하는 반면, 2차 회복 열처리시에는 금속 상부 전극에 홀 결함이 생성된다. 또한, 2차 회복 열처리시에는 금속 상부 전극의 열팽창에 의해 금속 상부 전극 위에 형성된 축전기 확산 방지막 및 축전기 평탄화 절연막에 균열(crack)이 발생한다. 2차 회복 열처리시에 발생하는 이러한 홀 결함 및 균열 결함들은 결과적으로 축전기의 특성 및 수율 저하를 야기시킨다.In general, when using a ferroelectric having a pervoskites structure, such as PZT, PLZT, BT, SBT, SBTN, etc., as a ferroelectric capacitor material of the accumulator in a FeRAM device, Pt, Ir, Ru, Pt- Metal upper electrodes such as alloys are used. In this case, a defect occurs in the metal upper electrode due to the high mobility of the metal at a high temperature during the recovery heat treatment performed at a high temperature of 650 to 800 ° C. Recovery heat treatment is the first recovery heat treatment to recover the ferroelectric properties degraded by etching damage after capacitor etching. It is roughly classified as a secondary recovery heat treatment for restoring the characteristics of a ferroelectric film deteriorated by hydrogen damage in a process of forming a capacitor level dielectric and an intermediate level dielectric. Shrinkage of the metal upper electrode mainly occurs during the primary recovery heat treatment, while hole defects are generated in the metal upper electrode during the secondary recovery heat treatment. In the second recovery heat treatment, cracks occur in the capacitor diffusion barrier film and the capacitor planarization insulating film formed on the metal upper electrode due to thermal expansion of the metal upper electrode. These hole defects and crack defects occurring during the secondary recovery heat treatment result in deterioration of the characteristics and yield of the capacitor.
따라서, 본 발명은 열공정 방법을 개선하여 축전기 콘택 식각 후 2차 회복 열처리시 금속 상부 전극에 생성되는 홀 결함(hole defect)과 금속 상부 전극 위에 형성된 축전기 확산 방지막 및 축전기 평탄화 절연막에 발생하는 균열(crack)을 방지하여 축전기의 특성 및 수율을 향상시킬 수 있는 FeRAM 소자의 축전기 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention improves the thermal process method, so that the hole defects generated in the metal upper electrode during the secondary recovery heat treatment after the capacitor contact etching and the cracks generated in the capacitor diffusion barrier film and the capacitor planarization insulating film formed on the metal upper electrode ( It is an object of the present invention to provide a capacitor manufacturing method of the FeRAM device that can improve the characteristics and yield of the capacitor by preventing cracks.
도 1a 내지 도 1e는 본 발명의 페로일렉트릭 램 소자의 축전기 제조 방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a capacitor manufacturing method of the ferroelectric ram device of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 필드 산화막11: semiconductor substrate 12: field oxide film
13: 트랜지스터 13G: 게이트 전극13: transistor 13G: gate electrode
13S: 소오스 접합부 13D: 드레인 접합부13S: source junction 13D: drain junction
14: 제 1 평탄화 절연막 15: 비트 라인14: first planarization insulating film 15: bit line
16: 제 2 평탄화 절연막 17: 보호막16: 2nd planarization insulating film 17: protective film
18: 접착층 20: 축전기18: adhesive layer 20: capacitor
20B: 금속 하부 전극(하부 금속층) 20F: 강유전체막20B: metal lower electrode (lower metal layer) 20F: ferroelectric film
20T: 금속 상부 전극 (상부 금속층) 21: 하드 마스크층20T: metal upper electrode (upper metal layer) 21: hard mask layer
22: 축전기 확산 방지막 23: 축전기 평탄화 절연막22: capacitor diffusion prevention film 23: capacitor planarization insulating film
24: 축전기 콘택홀 25: 소오스 콘택홀24: capacitor contact hole 25: source contact hole
26: 장벽 금속층 27: 금속 배선26: barrier metal layer 27: metal wiring
상술한 목적을 달성하기 위해 본 발명은 반도체 기판에 트랜지스터 및 비트 라인을 형성한 후, 전체구조상에 평탄화 절연막을 형성하고, 상기 평탄화 절연막 상에 보호막, 접착층, 하부 금속층, 강유전체막, 상부 금속층 및 하드 마스크층을순차적으로 형성하는 단계; 상기 하드 마스크층, 상부 금속층, 강유전체막, 하부 금속층 및 접착층을 순차적으로 패터닝하여 금속 하부 전극, 강유전체막 및 금속 상부 전극으로 구성된 축전기를 형성하는 단계; 상기 축전기 형성후, 제 1 열처리 공정을 행하여 식각 공정에 의해 열화된 강유전체막의 특성을 회복시키는 단계와; 상기 축전기를 포함한 전체 구조상에 축전기 확산 방지막 및 축전기 평탄화 절연막을 순차적으로 형성한 후, 제 2 열처리 공정으로 수소 충격에 의해 열화된 강유전체막 특성 회복 및 금속 상부 전극을 치밀화 시키는 단계; 축전기 콘택 공정 및 소오스 콘택 공정으로 축전기 콘택홀 및 소오스 콘택홀을 형성한 후, 장벽 금속층을 형성하고, 소오스 접합부 계면에 타이타늄실리사이드를 형성하기 위한 제 3 열처리 공정을 실시하는 단계; 상기 장벽 금속층 상에 금속층 증착 및 패터닝 공정으로 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention forms a transistor and a bit line on a semiconductor substrate, and then forms a planarization insulating film on the entire structure, and a protective film, an adhesive layer, a lower metal layer, a ferroelectric film, an upper metal layer, and a hard layer on the planarization insulating film. Sequentially forming a mask layer; Sequentially patterning the hard mask layer, the upper metal layer, the ferroelectric layer, the lower metal layer, and the adhesive layer to form a capacitor including a metal lower electrode, a ferroelectric layer, and a metal upper electrode; After forming the capacitor, performing a first heat treatment process to restore the characteristics of the ferroelectric film degraded by the etching process; Sequentially forming a capacitor diffusion barrier film and a capacitor planarization insulating film on the entire structure including the capacitor, and then densifying the ferroelectric film properties deteriorated by hydrogen impact and densifying the metal upper electrode in a second heat treatment process; Forming a capacitor contact hole and a source contact hole by a capacitor contact process and a source contact process, and then forming a barrier metal layer, and performing a third heat treatment process for forming titanium silicide at the source junction interface; And forming a metal wire on the barrier metal layer by a metal layer deposition and patterning process.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명의 페로일렉트릭 램 소자의 축전기 제조 방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of a device for explaining a capacitor manufacturing method of the ferroelectric RAM device of the present invention.
도 1a를 참조하면, 반도체 기판(11)에 필드 산화막(12)을 형성하여 액티브 영역(active region)을 정의(define)하고, 액티브 영역의 반도체 기판에 게이트 전극(13G), 소오스 접합부(13S) 및 드레인 접합부(13D)로 구성된 하부 트랜지스터(13)를 형성한다. 트랜지스터(13)를 포함한 전체 구조상에 제 1 평탄화 절연막(14)을 형성한다. 드레인 접합부(13D) 부분의 제 1 평탄화 절연막(14)을 제거한 후 드레인 접합부(13D)에 연결되는 비트 라인(15)을 형성한다. 비트 라인(15)을 포함한 전체 구조상에 제 2 평탄화 절연막(16)을 형성하고, 제 2 평탄화 절연막(16)상에 보호막(passivation film; 17)을 형성한다. 보호막(17) 상에 접착층(adhesion layer; 18)을 형성한 후, 그 상부에 하부 금속층(20B), 강유전체막(ferroelectric film; 20F) 및 상부 금속층(20T)을 순차적으로 형성한다. 상부 금속층(20T)상에 하드 마스크층(hard mask layer; 21)을 형성한다.Referring to FIG. 1A, a field oxide film 12 is formed in a semiconductor substrate 11 to define an active region, and a gate electrode 13G and a source junction 13S are formed in a semiconductor substrate in an active region. And the lower transistor 13 formed of the drain junction 13D. The first planarization insulating film 14 is formed over the entire structure including the transistor 13. After the first planarization insulating layer 14 of the drain junction 13D is removed, the bit line 15 connected to the drain junction 13D is formed. A second planarization insulating film 16 is formed on the entire structure including the bit line 15, and a passivation film 17 is formed on the second planarization insulating film 16. After the adhesion layer 18 is formed on the passivation layer 17, a lower metal layer 20B, a ferroelectric film 20F, and an upper metal layer 20T are sequentially formed thereon. A hard mask layer 21 is formed on the upper metal layer 20T.
상기에서, 제 1 및 제 2 평탄화 절연막(14 및 16)은 주로 산화물(oxide)로 형성하되, 적어도 BPSG막을 포함한다. 보호막(17)은 고온 산화막(HTO)과 같은 산화물로 형성한다. 접착층(18)은 Ti, Ta, TiOX, TaOX중 어느 하나로 형성한다. 하부 금속층(20B)은 Pt, Ir, Ru, Pt-Alloy, RuO2, IrO2, LSCO, YBCO 등과 같은 금속을 CVD법, 스퍼터링법과 같은 PVD법을 적용하여 형성한다. 강유전체막(20F)은 PZT, PLZT, BT, SBT, SBTN 등과 같은 퍼보스키트스(pervoskites) 구조를 갖는 강유전체를 PVD, CVD, 회전도포(spin-coating)법, LSMCD법 중 어느 하나의 방법으로 형성하는데, 이때 강유전체막(20F)의 결정화를 위해 산소 분위기의 600 내지 800℃의 온도범위에서 약 60분 정도 후열처리한다. 상부 금속층(20T)은 Pt, Ir, Ru, Pt-Alloy 등과 같은 금속을 CVD법, 스퍼터링법과 같은 PVD법을 적용하여 1500 내지 2000Å의 두께로 형성한다. 하드 마스크층(21)은 TiN, TiOX, SiO2중 어느 하나로 형성한다.In the above, the first and second planarization insulating films 14 and 16 are mainly formed of oxide, and include at least a BPSG film. The protective film 17 is formed of an oxide such as a high temperature oxide film (HTO). The adhesive layer 18 is formed of any one of Ti, Ta, TiO X and TaO X. The lower metal layer 20B is formed of a metal such as Pt, Ir, Ru, Pt-Alloy, RuO 2 , IrO 2 , LSCO, YBCO, or the like by applying a PVD method such as a CVD method or a sputtering method. The ferroelectric film 20F is made of any one of the following methods: PVD, CVD, spin-coating, or LSMCD, for ferroelectrics having a pervoskites structure such as PZT, PLZT, BT, SBT, SBTN, etc. In this case, in order to crystallize the ferroelectric film 20F, the heat treatment is performed for about 60 minutes at a temperature range of 600 to 800 ° C. in an oxygen atmosphere. The upper metal layer 20T forms metals such as Pt, Ir, Ru, and Pt-Alloy to a thickness of 1500 to 2000 kPa by applying PVD methods such as CVD and sputtering. The hard mask layer 21 is formed of any one of TiN, TiO X , and SiO 2 .
도 1b를 참조하면, 마스크 공정 및 식각 공정으로 하드 마스크층(21) 및 상부 금속층(20T)을 순차적으로 패터닝하고, 이로 인하여 금속 상부 전극(20T)이 형성된다. 이후, 다시 마스크 공정 및 식각 공정으로 강유전체막(20F), 하부 금속층(20B) 및 접착층(18)을 순차적으로 패터닝하고, 이로 인하여 금속 하부 전극(20B)이 형성된다. 이러한 패터닝 공정의 결과 금속 하부 전극(20B), 강유전체막(20F) 및 금속 상부 전극(20T)으로 구성된 축전기(20)가 형성된다. 축전기(20)를 형성하기 위한 식각 공정시 식각 충격에 의해 열화된 강유전체막(20F)의 특성을 회복시켜주기 위해 650 내지 800℃의 온도에서 약 30분 정도 1차 회복 열처리 공정을 실시해야 한다.Referring to FIG. 1B, the hard mask layer 21 and the upper metal layer 20T are sequentially patterned by a mask process and an etching process, thereby forming the metal upper electrode 20T. Thereafter, the ferroelectric film 20F, the lower metal layer 20B, and the adhesive layer 18 are sequentially patterned again using a mask process and an etching process, thereby forming the metal lower electrode 20B. As a result of this patterning process, a capacitor 20 composed of the metal lower electrode 20B, the ferroelectric film 20F, and the metal upper electrode 20T is formed. During the etching process for forming the capacitor 20, in order to restore the characteristics of the ferroelectric film 20F deteriorated by the etching impact, a primary recovery heat treatment process may be performed for about 30 minutes at a temperature of 650 to 800 ° C.
도 1c를 참조하면, 축전기(20)를 포함한 전체 구조상에 축전기 확산 방지막(22) 및 축전기 평탄화 절연막(23)을 순차적으로 형성한다. 이들 막(22 및 23)을 형성한 후에 수소 충격에 의해 열화된 강유전체막(20F)의 특성을 회복시키고, 동시에 금속 상부 전극(20T)을 치밀화(densification)시키기 위하여 산소 분위기의 650 내지 800℃의 온도에서 약 30 내지 60분 동안 열처리 공정을 실시한다.Referring to FIG. 1C, the capacitor diffusion barrier 22 and the capacitor planarization insulating layer 23 are sequentially formed on the entire structure including the capacitor 20. After the formation of these films 22 and 23, in order to restore the properties of the ferroelectric film 20F deteriorated by hydrogen impact, and at the same time to densify the metal upper electrode 20T, an oxygen atmosphere of 650 to 800 ° C The heat treatment process is carried out for about 30 to 60 minutes at the temperature.
상기에서, 축전기 확산 방지막(22)은 SiO2, TiO2, Al2O3, SiOXN2-X, TiOXN2-X등과 같은 세라믹 재료중 어느 하나로 형성한다. 축전기 확산 방지막(22)을 650 내지 800℃의 온도에서 형성할 경우 상기한 1차 회복 열처리 공정을 생략할 수 있다. 축전기 평탄화 절연막(23)은 SOG, BPSG 등으로 형성한다. 축전기 평탄화 절연막(23)으로 BPSG가 적용될 경우, BPSG는 700 내지 850℃의 고온에서 평탄화 유동(flow) 열처리를 행하게 되는데, 이 경우 수소 충격에 의해 열화된 강유전체막(20F)의 특성을 회복시키고, 동시에 금속 상부 전극(20T)을 치밀화 시키기 위한 열처리 공정을 생략할 수 있다.In the above, the capacitor diffusion barrier 22 is formed of any one of ceramic materials such as SiO 2 , TiO 2 , Al 2 O 3 , SiO X N 2-X , TiO X N 2-X, and the like. When the capacitor diffusion barrier 22 is formed at a temperature of 650 to 800 ° C., the above-described first recovery heat treatment process may be omitted. The capacitor planarization insulating film 23 is made of SOG, BPSG, or the like. When BPSG is applied to the capacitor planarization insulating film 23, the BPSG is subjected to a planarization flow heat treatment at a high temperature of 700 to 850 ° C. In this case, the characteristics of the ferroelectric film 20F deteriorated by hydrogen impact are restored. At the same time, the heat treatment process for densifying the metal upper electrode 20T can be omitted.
도 1d를 참조하면, 축전기 콘택 공정 및 소오스 콘택 공정으로 축전기(20)의 금속 상부 전극(20T)의 일부가 노출되는 축전기 콘택홀(24)과 트랜지스터(13)의 소오스 접합부(13S)의 일부가 노출되는 소오스 콘택홀(25)을 형성한다.Referring to FIG. 1D, a part of the source contact portion 13S of the transistor 13 and the capacitor contact hole 24 in which a part of the metal upper electrode 20T of the capacitor 20 is exposed in the capacitor contact process and the source contact process is shown. The exposed source contact hole 25 is formed.
상기에서, 기존에는 축전기 콘택 공정을 실시한 후에 650 내지 800℃의 고온에서 2차 회복 열처리 공정을 실시하는데, 2차 회복 열처리 공정에 의해 금속 상부 전극(20T)에 홀 결함 생성과 축전기 확산 방지막(22) 및 축전기 평탄화 절연막(23)에 균열이 발생하기 때문에 본 발명의 실시예에서는 2차 회복 열처리 공정을 생략한다.In the above, conventionally, after performing the capacitor contact process, the secondary recovery heat treatment process is performed at a high temperature of 650 to 800 ° C., and the hole defect generation and the capacitor diffusion barrier layer 22 are formed on the metal upper electrode 20T by the secondary recovery heat treatment process. ) And the capacitor planarization insulating film 23, so that the secondary recovery heat treatment step is omitted in the embodiment of the present invention.
도 1e를 참조하면, 축전기 콘택홀(24)과 소오스 콘택홀(25)을 포함한 전체 구조상 장벽 금속층(26)을 형성하고, 콘택 저항 감소를 위해 소오스 접합부(13S) 계면에 타이타늄실리사이드(TiSiX)를 형성하기 위한 열공정을 실시한다. 이와 같이 열공정을 실시하므로 인하여 축전기 콘택 공정 후에 실시하는 2차 회복 열처리 공정을 생략할 수 있다. 이후, 알루미늄이나 텅스텐과 같은 금속층 증착 및 패터닝 공정으로 축전기(20)의 금속 상부 전극(20T)과 트랜지스터(13)의 소오스 접합부(13S)를 전기적으로 연결하는 금속 배선(27)을 형성한다.Referring to FIG. 1E, the entire structural barrier metal layer 26 including the capacitor contact hole 24 and the source contact hole 25 is formed, and titanium silicide (TiSi X ) at the interface of the source junction 13S to reduce contact resistance. Conduct a thermal process to form a. Since the thermal process is performed in this manner, the secondary recovery heat treatment process performed after the capacitor contact process can be omitted. Subsequently, a metal wire 27 is formed to electrically connect the metal upper electrode 20T of the capacitor 20 and the source junction 13S of the transistor 13 by a metal layer deposition and patterning process such as aluminum or tungsten.
상기에서, 장벽 금속층(26)은 TiN/Ti, TiN/Ti/TiN 중 어느 하나로 형성된다.In the above, the barrier metal layer 26 is formed of any one of TiN / Ti and TiN / Ti / TiN.
상술한 바와 같이, 본 발명은 열공정 방법을 개선하므로, 강유전체막의 특성의 열화 없이 2차 회복 열처리시에 발생하는 홀 결함과 금속 상부 전극 위에 형성된 축전기 확산 방지막 및 축전기 평탄화 절연막에 발생하는 균열을 방지하여 축전기의 특성 및 수율을 향상시킬 수 있다.As described above, the present invention improves the thermal process method, thereby preventing hole defects occurring during secondary recovery heat treatment and cracks in the capacitor diffusion barrier film and the capacitor planarization insulating film formed on the metal upper electrode without deterioration of the characteristics of the ferroelectric film. The characteristics and yield of the capacitor can be improved.
Claims (15)
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