KR100309474B1 - Metal line forming method - Google Patents
Metal line forming method Download PDFInfo
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- KR100309474B1 KR100309474B1 KR1019990048798A KR19990048798A KR100309474B1 KR 100309474 B1 KR100309474 B1 KR 100309474B1 KR 1019990048798 A KR1019990048798 A KR 1019990048798A KR 19990048798 A KR19990048798 A KR 19990048798A KR 100309474 B1 KR100309474 B1 KR 100309474B1
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- film
- metal wiring
- nitride film
- metal
- forming
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 64
- 239000002184 metal Substances 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 230000004888 barrier function Effects 0.000 claims abstract description 23
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000001039 wet etching Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 229920000642 polymer Polymers 0.000 abstract description 3
- 238000007796 conventional method Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
Abstract
본 발명은 금속배선 형성방법에 관한 것으로, 종래 금속배선 형성방법은 금속배선의 상부가 식각에 직접 노출되므로 금속배선의 손상이나 폴리머가 발생할 수 있으며 금속배선 사이에 존재하는 기생커패시턴스가 증가하여 시간지연(RC Time Delay)을 유발하므로 전체 반도체장치의 효율을 저하시키는 문제점이 있었다. 따라서 본 발명은 소자가 형성된 반도체기판 상부에 차례로 절연막, 질화막을 증착하고 금속 배선이 형성될 부분을 사진식각공정을 통해 식각하는 공정과; 상기 절연막 및 질화막의 상부전면에 차례로 금속배리어막, 알루미늄막을 형성하는 공정과; 상기 알루미늄막 및 금속배리어막을 상기 질화막이 드러나도록 화학기계적연마를 통해 평탄화 한 다음 다시 에치백하여 질화막 하부까지 식각한 후 그 구조물 상부에 금속배리어막을 물리적 기상증착 방식으로 형성하는 공정과; 상기 질화막을 습식식각하여 제거하는 공정으로 이루어지는 금속배선 형성방법을 통해 상부 금속배선과의 접속을 위한 비아형성시 그 공정이 용이해 지면서도 기생커패시턴스 증가를 방지할 수 있을 뿐 아니라 금속배선의 EM특성을 향상시켜 결과적으로 소자의 효율과 신뢰성을 향상시킬 수 있는 효과가 있다.The present invention relates to a metal wiring forming method, the conventional metal wiring forming method is exposed directly to the etching of the upper metal wiring can damage the metal wiring or the polymer may occur and the parasitic capacitance present between the metal wiring increases the time delay (RC Time Delay) causes a problem of lowering the efficiency of the entire semiconductor device. Therefore, the present invention comprises the steps of depositing an insulating film, a nitride film on the semiconductor substrate on which the device is formed, and etching the portion where the metal wiring is to be formed through a photolithography process; Forming a metal barrier film and an aluminum film in order on the upper surfaces of the insulating film and the nitride film; Planarizing the aluminum film and the metal barrier film by chemical mechanical polishing to expose the nitride film, and then etching back to etch the lower portion of the nitride film, and then forming a metal barrier film on the structure by physical vapor deposition; The metal wiring forming method comprising wet etching and removing the nitride film not only facilitates the process when forming vias for connection with the upper metal wiring, but also prevents the increase of parasitic capacitance and the EM characteristics of the metal wiring. As a result, the efficiency and reliability of the device can be improved.
Description
본 발명은 금속배선 형성방법에 관한 것으로, 특히 상감(Damascene)법을 이용한 금속배선의 상부에 금속배리어막을 형성함으로써 비아(VIA)형성 시 식각조절을 용이하게 함과 아울러 금속배선의 신뢰성을 높이기에 적당하도록 한 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring, and in particular, by forming a metal barrier film on the top of the metal wiring using the damascene method to facilitate etching control when forming a via (VIA) and to increase the reliability of the metal wiring. It relates to a method for forming a metal wiring to be suitable.
종래 금속배선 형성방법을 도 1a 내지 도 1d의 수순단면도를 참고로 하여 설명하면 다음과 같다.Referring to the conventional cross-sectional view of Figure 1a to 1d the method of forming a metal wiring as follows.
소자가 형성된 반도체기판(1) 상부에 절연막(2)을 증착하고 금속 배선이 형성될 부분을 사진식각공정을 통해 식각하는 공정과; 상기 절연막(2)의 상부전면에 차례로 금속배리어막(3), 알루미늄막(4)을 형성하는 공정과; 상기 구조물을 절연막(2)이 드러나도록 평탄화하는 공정과; 상기 구조물 상부전면에 차례로 질화막(5), 금속간절연막(6)을 형성한 후 그 금속간절연막(6)의 특정부위를 식각하고, 질화막(5)을 식각하여 비아홀을 형성하는 공정으로 이루어진다.Depositing an insulating film (2) over the semiconductor substrate (1) on which the device is formed and etching a portion where the metal wiring is to be formed through a photolithography process; Forming a metal barrier film (3) and an aluminum film (4) on the upper surface of the insulating film (2) in sequence; Planarizing the structure so that the insulating film 2 is exposed; The nitride film 5 and the intermetallic insulating film 6 are sequentially formed on the upper surface of the structure, and then a specific portion of the intermetallic insulating film 6 is etched, and the nitride film 5 is etched to form via holes.
먼저, 도 1a에 도시한 바와같이 소자가 형성된 반도체기판(1) 상부에 절연막(2)을 증착하고, 그 상부에 감광막을 도포한 후 금속 배선이 형성될 부분에 맞도록 패터닝하여 이를 마스크로 절연막(2)의 일부를 식각하고, 상기 감광막을 제거한다.First, as shown in FIG. 1A, an insulating film 2 is deposited on the semiconductor substrate 1 on which the device is formed, a photoresist film is applied on the upper portion thereof, and then patterned to match the portion where the metal wiring is to be formed. A part of (2) is etched and the said photosensitive film is removed.
그 다음, 도 1b에 도시한 바와같이 상기 절연막(2)의 상부전면에 차례로 금속배리어막(3), 알루미늄막(4)을 형성한다.Next, as shown in FIG. 1B, the metal barrier film 3 and the aluminum film 4 are sequentially formed on the upper front surface of the insulating film 2.
그 다음, 도 1c에 도시한 바와같이 상기 구조물을 절연막(2)이 드러나도록 평탄화한다.Then, the structure is planarized so that the insulating film 2 is exposed as shown in FIG. 1C.
이때, 상기 형성된 금속 배선은 금속배리어막(3)에 의해 양 측면과 그 하부가 둘러 쌓여져 있으며 이로 인해 절연막(2)과 알루미늄막(4)의 반응을 방지하고, 알루미늄막(4)의 전자이동(Electromigration:EM)을 억제하여 EM특성을 향상시킨다.At this time, the sidewalls and lower portions of the formed metal wirings are surrounded by the metal barrier film 3, thereby preventing the reaction between the insulating film 2 and the aluminum film 4, and the electron movement of the aluminum film 4. It improves EM characteristics by suppressing (Electromigration: EM).
그 다음, 도 1d에 도시한 바와같이 상기 구조물 상부전면에 차례로 질화막(5), 금속간절연막(6)을 형성한 후 금속간절연막(6)의 특정부위를 식각하고, 질화막(5)을 식각하여 비아홀을 형성하는 공정으로 이루어진다.Next, as shown in FIG. 1D, the nitride film 5 and the intermetallic insulating film 6 are sequentially formed on the upper surface of the structure, and then a specific portion of the intermetallic insulating film 6 is etched, and the nitride film 5 is etched. To form a via hole.
이때, 상기 질화막(5) 없이 금속간절연막(6) 만을 형성하고 식각하면, 그 식각 과정에서 하부에 위치한 알루미늄막(4)이 식각에 직접 노출되게 됨에따라 알루미늄막(4)의 손실이 많아지거나 폴리머가 발생하므로 이를 방지하기 위해서 질화막(5)을 형성 한 후 그 상부에 금속간절연막(6)을 형성하고 이를 식각하여 비아홀의 일부를 형성한 다음 질화막(5) 만을 다시 식각하여 완전한 비아홀을 형성한다.At this time, if only the intermetallic insulating film 6 is formed and etched without the nitride film 5, the aluminum film 4 located at the lower portion of the etching process is directly exposed to the etching, so that the loss of the aluminum film 4 increases. Since the polymer is generated, in order to prevent this, the nitride film 5 is formed, and then an intermetallic insulating film 6 is formed on the upper portion thereof, and the via film is etched to form a part of the via hole, and only the nitride film 5 is etched again to form a complete via hole. do.
하지만, 상기한 바와 같은 방법으로 질화막(5)을 금속배선 사이에 형성하면 기생커패시턴스가 증가하여 시정수에 의한 지연이 발생할 수 있다.However, when the nitride film 5 is formed between the metal wires in the above-described manner, parasitic capacitance may increase and delay due to time constant may occur.
상기한 바와같은 종래 금속배선 형성방법은 금속배선의 상부가 식각에 직접 노출되므로 금속배선의 손상이나 폴리머가 발생할 수 있으며 금속배선 사이에 존재하는 기생커패시턴스가 증가하여 시간지연(RC Time Delay)을 유발하므로 전체 반도체장치의 효율을 저하시키는 문제점이 있었다.In the conventional method of forming a metal wiring as described above, since the upper portion of the metal wiring is directly exposed to etching, damage to the metal wiring or polymer may occur, and parasitic capacitance between metal wiring increases, causing a time delay (RC Time Delay). Therefore, there is a problem of lowering the efficiency of the entire semiconductor device.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 금속배선의 양측면과 하부는 물론이고 그 상부에도 금속배리어막을 형성하여 금속배선의 EM특성을 향상시킴은 물론이고, 비아홀 형성이 간편한 금속배선 형성방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to improve the EM characteristics of the metal wiring by forming a metal barrier film on both sides and the bottom of the metal wiring as well as on the top thereof. In addition, the present invention provides a method for forming metal wires, which facilitates via hole formation.
도 1은 종래 금속배선 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for forming metal wiring.
도 2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 절연막21 semiconductor substrate 22 insulating film
23 : 질화막 24 : 제 1금속배리어막23 nitride film 24 first metal barrier film
25 : 알루미늄막 26 : 제 2금속배리어막25 aluminum film 26 second metal barrier film
상기한 바와같은 본 발명의 목적을 달성하기 위한 금속배선 형성방법은 소자가 형성된 반도체기판 상부에 차례로 절연막, 질화막을 증착하고 금속 배선이 형성될 부분을 사진식각공정을 통해 식각하는 공정과; 상기 절연막 및 질화막의 상부전면에 차례로 금속배리어막, 알루미늄막을 형성하는 공정과; 상기 알루미늄막 및 금속배리어막을 상기 질화막이 드러나도록 화학기계적연마를 통해 평탄화 한 다음 다시 에치백하여 질화막 하부까지 식각한 후 그 구조물 상부에 금속배리어막을 물리적 기상증착 방식으로 형성하는 공정과; 상기 질화막을 습식식각하여 제거하는 공정으로 이루어지는 것을 특징으로 한다.A metal wiring forming method for achieving the object of the present invention as described above comprises the steps of depositing an insulating film, a nitride film on the semiconductor substrate on which the device is formed and etching a portion of the metal wiring to be formed through a photolithography process; Forming a metal barrier film and an aluminum film in order on the upper surfaces of the insulating film and the nitride film; Planarizing the aluminum film and the metal barrier film by chemical mechanical polishing to expose the nitride film, and then etching back to etch the lower portion of the nitride film, and then forming a metal barrier film on the structure by physical vapor deposition; It characterized in that it comprises a step of removing the nitride film by wet etching.
상기한 바와같은 본 발명에 의한 금속배선 형성방법을 첨부한 도 2a내지 도 2d의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 2a to 2d with a method of forming a metal wiring according to the present invention as described above in detail as an embodiment as follows.
먼저, 도 2a에 도시한 바와같이 소자가 형성된 반도체기판(21) 상부에 차례로 절연막(22), 질화막(23)을 증착하고, 그 상부에 감광막을 도포한 후 금속 배선이 형성될 부분에 맞도록 패터닝하여 이를 마스크로 질화막(23)과 절연막(22)의 일부를식각하고, 상기 감광막을 제거한다.First, as shown in FIG. 2A, an insulating film 22 and a nitride film 23 are sequentially deposited on the semiconductor substrate 21 on which the device is formed, and then a photosensitive film is coated on the upper portion thereof so as to match the portion where the metal wiring is to be formed. After patterning, a portion of the nitride film 23 and the insulating film 22 is etched using a mask, and the photoresist film is removed.
이때, 질화막(23)은 습식식각이 가능한 종류를 사용하여 500Å이상 증착한다.At this time, the nitride film 23 is deposited by 500 kPa or more using a type capable of wet etching.
그 다음, 도 2b에 도시한 바와같이 상기 절연막(22) 및 질화막(23)의 상부전면에 차례로 금속배리어막(24), 알루미늄막(25)을 형성한다.Next, as shown in FIG. 2B, the metal barrier film 24 and the aluminum film 25 are sequentially formed on the upper surfaces of the insulating film 22 and the nitride film 23.
그 다음, 도 2c에 도시한 바와같이 상기 알루미늄막(25) 및 금속배리어막(24)을 상기 질화막(23)이 드러나도록 화학기계적연마를 통해 평탄화 한 다음 다시 에치백하여 질화막(23)의 하부까지 300~600Å 정도 건식각한 후 그 구조물 상부에 금속배리어막(26)을 물리적 기상증착 방식으로 형성한다.Next, as shown in FIG. 2C, the aluminum film 25 and the metal barrier film 24 are planarized by chemical mechanical polishing so that the nitride film 23 is exposed, and then etched back to lower the nitride film 23. After dry etching about 300 ~ 600Å until the metal barrier film 26 is formed on the structure by physical vapor deposition method.
그 다음, 도 2d에 도시한 바와같이 상기 질화막(23)을 습식식각하여 제거하면 이 질화막(23)의 상부에 형성되어 있는 금속배리어막(26)도 같이 제거되고, 이러한 현상을 리프트 오프(Lift off)라 한다.Then, as shown in FIG. 2D, when the nitride film 23 is wet-etched and removed, the metal barrier film 26 formed on the nitride film 23 is also removed, and this phenomenon is lifted off. off).
상기와 같은 공정을 통해 알루미늄막(25)의 측면 및 하부를 둘러싸고 있는 금속배리어막(24)과 상부를 보호하는 금속배리어막(26)을 형성한다.Through the above process, the metal barrier film 24 surrounding the side and the bottom of the aluminum film 25 and the metal barrier film 26 protecting the upper portion are formed.
상기 형성한 금속배선의 상부에 비아홀을 형성 할 경우 상기 구조물 상부에 금속간절연막을 형성하고 이를 식각하더라도 알루미늄막(25)은 직접 식각에 노출되지 않으므로 식각조정 마진이 커지게되어 공정이 용이해지고, 금속배선의 전면을 금속간절연막(24,26)으로 둘러싸고 있으므로 EM특성이 좋아진다.When the via hole is formed on the formed metal wiring, even though the intermetallic insulating film is formed on the structure and etched, the aluminum film 25 is not directly exposed to the etching, so the etching adjustment margin is increased, thereby facilitating the process. EM properties are improved because the entire surface of the metal wiring is surrounded by the intermetallic insulating films 24 and 26.
상기한 바와같은 본 발명에 의한 금속배선 형성방법은 전류가 흐르는 금속막의 측면 및 하부를 금속배리어막을 형성하여 보호하는, 상부가 드러난 금속배선에 대해 리프트 오프특성을 이용하여 그 상부에도 금속배리어막을 형성하여 보호하도록 함으로써 상부 금속배선과의 접속을 위한 비아형성시 그 공정이 용이해 지면서도 기생커패시턴스 증가를 방지할 수 있을 뿐 아니라 금속배선의 EM특성을 향상시켜 결과적으로 소자의 효율과 신뢰성을 향상시킬 수 있는 효과가 있다.In the metal wiring forming method according to the present invention as described above, the metal barrier film is formed on the upper portion of the metal wiring layer using the lift-off characteristic on the exposed metal wiring to protect the side and the bottom of the metal film through which the current flows. This method facilitates the process of forming vias for connection to the upper metal wiring, while preventing parasitic capacitance increase, and improves the EM characteristics of the metal wiring, resulting in improved device efficiency and reliability. It can be effective.
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|---|---|---|---|---|
| JPH06275612A (en) * | 1993-03-19 | 1994-09-30 | Fujitsu Ltd | Manufacture of integrated circuit device |
| JPH08124848A (en) * | 1994-10-21 | 1996-05-17 | Ngk Insulators Ltd | Lift-off method of forming pattern layer on substrate by use of single resist layer |
| JPH10189592A (en) * | 1996-12-25 | 1998-07-21 | Nippon Steel Corp | Manufacturing method of semiconductor device |
| JPH118242A (en) * | 1997-06-17 | 1999-01-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH1116906A (en) * | 1997-06-27 | 1999-01-22 | Sony Corp | Semiconductor device and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH06275612A (en) * | 1993-03-19 | 1994-09-30 | Fujitsu Ltd | Manufacture of integrated circuit device |
| JPH08124848A (en) * | 1994-10-21 | 1996-05-17 | Ngk Insulators Ltd | Lift-off method of forming pattern layer on substrate by use of single resist layer |
| JPH10189592A (en) * | 1996-12-25 | 1998-07-21 | Nippon Steel Corp | Manufacturing method of semiconductor device |
| JPH118242A (en) * | 1997-06-17 | 1999-01-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH1116906A (en) * | 1997-06-27 | 1999-01-22 | Sony Corp | Semiconductor device and its manufacturing method |
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