KR100305544B1 - 정수 나눗셈 장치 - Google Patents

정수 나눗셈 장치 Download PDF

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Publication number
KR100305544B1
KR100305544B1 KR1019950703430A KR19950703430A KR100305544B1 KR 100305544 B1 KR100305544 B1 KR 100305544B1 KR 1019950703430 A KR1019950703430 A KR 1019950703430A KR 19950703430 A KR19950703430 A KR 19950703430A KR 100305544 B1 KR100305544 B1 KR 100305544B1
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KR
South Korea
Prior art keywords
dividend
bit
divisor
integer
quotient
Prior art date
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Expired - Lifetime
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KR1019950703430A
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English (en)
Korean (ko)
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KR960701397A (ko
Inventor
하프만웰리암에이
Original Assignee
롭 샘, 로베르트 알. 비숍, 스코트 아르넬
실리콘그래픽스 인코포레이티드
니시무로 타이죠
가부시끼가이샤 도시바
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Application filed by 롭 샘, 로베르트 알. 비숍, 스코트 아르넬, 실리콘그래픽스 인코포레이티드, 니시무로 타이죠, 가부시끼가이샤 도시바 filed Critical 롭 샘, 로베르트 알. 비숍, 스코트 아르넬
Publication of KR960701397A publication Critical patent/KR960701397A/ko
Application granted granted Critical
Publication of KR100305544B1 publication Critical patent/KR100305544B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
    • G06F2207/5353—Restoring division

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
KR1019950703430A 1993-12-15 1994-12-15 정수 나눗셈 장치 Expired - Lifetime KR100305544B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/167006 1993-12-15
US08/167,006 US5493523A (en) 1993-12-15 1993-12-15 Mechanism and method for integer divide involving pre-alignment of the divisor relative to the dividend
US08/167,006 1993-12-15
PCT/JP1994/002109 WO1995016951A1 (en) 1993-12-15 1994-12-15 Method and apparatus for integer division

Publications (2)

Publication Number Publication Date
KR960701397A KR960701397A (ko) 1996-02-24
KR100305544B1 true KR100305544B1 (ko) 2001-11-22

Family

ID=22605562

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950703430A Expired - Lifetime KR100305544B1 (ko) 1993-12-15 1994-12-15 정수 나눗셈 장치

Country Status (8)

Country Link
US (1) US5493523A (enExample)
EP (1) EP0684548B1 (enExample)
JP (1) JP3564138B2 (enExample)
KR (1) KR100305544B1 (enExample)
CN (1) CN1103077C (enExample)
DE (1) DE69430053T2 (enExample)
TW (1) TW280891B (enExample)
WO (1) WO1995016951A1 (enExample)

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US5754460A (en) * 1995-05-26 1998-05-19 National Semiconductor Corporation Method for performing signed division
US5946223A (en) * 1995-12-08 1999-08-31 Matsushita Electric Industrial Co. Ltd. Subtraction/shift-type dividing device producing a 2-bit partial quotient in each cycle
US5805489A (en) * 1996-05-07 1998-09-08 Lucent Technologies Inc. Digital microprocessor device having variable-delay division hardware
US5768573A (en) * 1996-11-20 1998-06-16 International Business Machines Corporation Method and apparatus for computing a real time clock divisor
JP3173419B2 (ja) 1997-05-08 2001-06-04 日本電気株式会社 倍数判定回路及びその判定方法
TW374885B (en) * 1997-06-06 1999-11-21 Matsushita Electric Industrial Co Ltd The arithmetic unit
US6317771B1 (en) * 1998-01-15 2001-11-13 Altera Corporation Method and apparatus for performing digital division
US20040249877A1 (en) * 2003-06-05 2004-12-09 International Business Machines Corporation Fast integer division with minimum number of iterations in substraction-based hardware divide processor
US7403966B2 (en) * 2003-12-08 2008-07-22 Freescale Semiconductor, Inc. Hardware for performing an arithmetic function
US7734901B2 (en) * 2005-10-31 2010-06-08 Mips Technologies, Inc. Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US7711934B2 (en) * 2005-10-31 2010-05-04 Mips Technologies, Inc. Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US20070204139A1 (en) 2006-02-28 2007-08-30 Mips Technologies, Inc. Compact linked-list-based multi-threaded instruction graduation buffer
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US7370178B1 (en) * 2006-07-14 2008-05-06 Mips Technologies, Inc. Method for latest producer tracking in an out-of-order processor, and applications thereof
US20080016326A1 (en) 2006-07-14 2008-01-17 Mips Technologies, Inc. Latest producer tracking in an out-of-order processor, and applications thereof
US7657708B2 (en) * 2006-08-18 2010-02-02 Mips Technologies, Inc. Methods for reducing data cache access power in a processor using way selection bits
US7650465B2 (en) 2006-08-18 2010-01-19 Mips Technologies, Inc. Micro tag array having way selection bits for reducing data cache access power
US7647475B2 (en) * 2006-09-06 2010-01-12 Mips Technologies, Inc. System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
US8032734B2 (en) * 2006-09-06 2011-10-04 Mips Technologies, Inc. Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor
US8078846B2 (en) 2006-09-29 2011-12-13 Mips Technologies, Inc. Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US9946547B2 (en) 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US7594079B2 (en) 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
JP2009175958A (ja) * 2008-01-23 2009-08-06 Seiko Epson Corp 除算器および除算方法、並びに除算器を用いた画像符号化装置
JP5397061B2 (ja) * 2009-07-21 2014-01-22 富士通株式会社 演算処理装置、その制御方法および演算処理プログラム
RU2498393C1 (ru) * 2012-07-27 2013-11-10 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования Вятский государственный университет ФГБОУ ВПО "ВятГУ" Способ деления целых двоичных чисел без остатка начиная с младших разрядов
US9747074B2 (en) 2014-02-25 2017-08-29 Kabushiki Kaisha Toshiba Division circuit and microprocessor
CN111104092B (zh) * 2019-12-06 2022-10-11 北京多思安全芯片科技有限公司 一种快速除法器和除法运算方法

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US3293418A (en) * 1964-07-08 1966-12-20 Control Data Corp High speed divider
US4380051A (en) * 1980-11-28 1983-04-12 Motorola, Inc. High speed digital divider having normalizing circuitry
US4460970A (en) * 1981-05-22 1984-07-17 Data General Corporation Digital data processing system using unique techniques for handling the leading digits and the signs of operands in arithmetic operations
US4760550A (en) * 1986-09-11 1988-07-26 Amdahl Corporation Saving cycles in floating point division
JP2585649B2 (ja) * 1987-11-30 1997-02-26 インデータシステムズ株式会社 除算回路
US5027309A (en) * 1988-08-29 1991-06-25 Nec Corporation Digital division circuit using N/M-bit subtractor for N subtractions
US5097435A (en) * 1988-12-24 1992-03-17 Kabushiki Kaisha Toshiba High speed dividing apparatus
JPH02194430A (ja) * 1989-01-24 1990-08-01 Oki Electric Ind Co Ltd 除算器
JPH04283832A (ja) * 1991-03-13 1992-10-08 Fujitsu Ltd 除算回路
JPH0540609A (ja) * 1991-08-02 1993-02-19 Toshiba Corp 浮動小数点除算装置
JPH0553768A (ja) * 1991-08-23 1993-03-05 Mitsubishi Electric Corp 除算器
JPH0573271A (ja) * 1991-09-17 1993-03-26 Nec Ic Microcomput Syst Ltd 除算回路
US5317531A (en) * 1992-04-02 1994-05-31 Intel Corporation Apparatus for reducing the size of an arithmetic and logic unit necessary to practice non-restore division
US5297073A (en) * 1992-08-19 1994-03-22 Nec Electronics, Inc. Integer divide using shift and subtract

Also Published As

Publication number Publication date
JP3564138B2 (ja) 2004-09-08
HK1018168A1 (en) 1999-12-10
CN1117763A (zh) 1996-02-28
US5493523A (en) 1996-02-20
EP0684548A4 (en) 1996-04-03
DE69430053T2 (de) 2002-11-21
EP0684548A1 (en) 1995-11-29
KR960701397A (ko) 1996-02-24
TW280891B (enExample) 1996-07-11
WO1995016951A1 (en) 1995-06-22
CN1103077C (zh) 2003-03-12
DE69430053D1 (de) 2002-04-11
EP0684548B1 (en) 2002-03-06

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