KR100300347B1 - Circuit for detecting/correcting digital frequency error in digital modulator/demodulator - Google Patents

Circuit for detecting/correcting digital frequency error in digital modulator/demodulator Download PDF

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KR100300347B1
KR100300347B1 KR1019930025521A KR930025521A KR100300347B1 KR 100300347 B1 KR100300347 B1 KR 100300347B1 KR 1019930025521 A KR1019930025521 A KR 1019930025521A KR 930025521 A KR930025521 A KR 930025521A KR 100300347 B1 KR100300347 B1 KR 100300347B1
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frequency
output
signal
demodulator
mixer
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KR950016112A (en
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문영훈
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윤종용
삼성전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/12—Indirect frequency synthesis using a mixer in the phase-locked loop

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE: A circuit for detecting/correcting a digital frequency error in a digital modulator/demodulator is provided to improve capacity of a modem by correcting a frequency error due to a Doppler's transition effect. CONSTITUTION: An amplifier(201) is used for amplifying an input signal of an intermediate frequency input terminal(100) of a demodulator. A frequency multiplier(202) multiplies an output of the amplifier(201) in order to remove a phase-modulated component of the output signal of the amplifier(201). The first and the second PLL circuits(203,204) generates the first and the second frequencies(2f1,2f2) from an output signal of the frequency multiplier(202). The fifth mixer(205) outputs a data carrier signal by multiplying an output of the first PLL circuit(203) by an output of the second PLL circuit(204). A high band pass filter(206) recovers a carrier by intercepting a low band of an output of the fifth mixer(205) and passing a high band of the output of the fifth mixer(205). A frequency divider(207) recovers a frequency of an original signal by dividing an output of the high band pass filter(206).

Description

디지탈 변복조기에 있어서 디지탈 주파수 에러검출/보정회로Digital Frequency Error Detection / Compensation Circuit in Digital Modulator

제1도는 종래의 기술을 설명하기 위한 회로도.1 is a circuit diagram for explaining a conventional technology.

제2도는 본 발명의 실시예에 따른 디지탈 변복조기에 있어서 디지탈 주파수 에러검출/보정회로도.2 is a digital frequency error detection / correction circuit diagram of a digital modulation and demodulator according to an embodiment of the present invention.

본 발명은 디지탈 변복조기에 있어서 주파수 에러제어회로에 관한 것으로, 특히 시분할 다중 접속 방식에서 일정 길이의 동기 데이타 열을 수신단에서 코히런트 복조(Coherent Demodulation)를 할 경우 발생하는 주파수 에러를 검출하고 보정하는 디지탈 변복조기에 있어서 디지탈 주파수 에러검출/보정회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency error control circuit in a digital modulation and demodulator, and more particularly, to detect and correct a frequency error generated when coherent demodulation is performed at a receiving end of a synchronous data string having a predetermined length in a time division multiple access scheme. A digital frequency error detection / correction circuit in a modulator.

제1도의 도시와 같이 수신단(100)으로 수신된 IF신호[S(t)]는 다음과 같을 경우IF signal [S (t)] received by the receiver 100 as shown in FIG. 1 is as follows.

제2믹서(101,104)에서 VCO(106)의 출력신호[Vr(t) = 2 cos wit]를 곱한 후, 제1,2저역통과필터(LPF1, LPF2)(102,104)를 통과한 신호[I1(t)]와 [Ql(t)]는 다음 ①, ②식과 같다.The signal [I 1 passed through the first and second low pass filters (LPF1, LPF2) (102, 104) after multiplying the output signal [Vr (t) = 2 cos wit] of the VCO 106 by the second mixer (101, 104). (t)] and [Q l (t)] are as follows.

여기서 △w = w0-wiㅇ1고, nI(t) 및 no(t)는 각각 I채널 및 Q 채널의 잡음신호에 해당된다. 상기 제1,2저역통과필터(102,103)의 출력은 제1,2미분기(d/dt)(107,108)에 입력하면 다음 ③,④식과 같이 발생된다.Where Δw = w 0 -wi ㅇ 1 and n I (t) and no (t) correspond to noise signals of I and Q channels, respectively. The outputs of the first and second low pass filters 102 and 103 are generated as shown in Equations 3 and 4 when inputted to the first and second differentiators d / dt 107 and 108.

상기 ③, ④식의 출력은 제3,4믹서(110,111)를 통과하면 하기 ④, ⑤식과 같이 I2(t), Q2(t) 신호가 된다.When the output of the above equations 3 and 4 passes through the third and fourth mixers 110 and 111, they become I 2 (t) and Q 2 (t) signals as shown in Equations 4 and 5 below.

상기 제3,4믹서(110,111)의 출력은 가산기(112)에서 가산되어 출력된 신호는 I2(t) + Q2(t)이므로 I2(t) + Q2(t) = -A2[△w +φ'(t)] 이다. 이를 루우프 필터(109)에 인가할 시 루우프 필터(109)의 출력신호는 -A2|HLp(w)|2[△w + φ'(t)]이 되므로 △w에 비례하는 전압 제어발진기(106)의 제어신호로 출력되어 이 신호로 VCO(106)를 제어하므로서 주파수 에러량을 줄여 나가게 된다.Since the outputs of the third and fourth mixers 110 and 111 are added by the adder 112 and the output signals are I 2 (t) + Q 2 (t), I 2 (t) + Q 2 (t) = -A 2 [Δw + φ '(t)]. When this is applied to the loop filter 109, the output signal of the loop filter 109 is -A 2 | HLp (w) | It becomes 2 [Δw + φ '(t)], so it is output as a control signal of the voltage controlled oscillator 106 proportional to Δw, thereby reducing the amount of frequency error by controlling the VCO 106 with this signal.

그러나 종래는 상기 VCO(106)의 제어입력신호인 루우프필터(109)의 출력 신호는 주파수 오차 △w에만 비례하는 -A2[△w] 성분만 있어야 하나 위상 변조된 성분의 미분값인 φ'(t) 성분이 남아 있으므로 해서 정확한 주파수 에러의 제어가 어렵다.However, conventionally, the output signal of the loop filter 109 which is the control input signal of the VCO 106 should have only -A 2 [Δw] component which is proportional to the frequency error Δw, but is the derivative value of the phase modulated component φ Since the (t) component remains, it is difficult to control the exact frequency error.

즉, 전체 주파수 에러 제어의 성능이 저하되는 문제점이 있었다.That is, there is a problem that the performance of the overall frequency error control is degraded.

따라서 본 발명의 목적은 국부 반송파 발생에 있어 주파수 오차 및 송신단과 수신단간의 상대적 이동 속도차로 인하여 발생되는 도플러 천이 현상에 의하여 나타나는 주파수 에러를 보정하여 모뎀의 성능저하 현상을 개선시키고 전체시스템의 통신성능을 향상시키는 회로를 제공함에 있다.Accordingly, an object of the present invention is to correct the frequency error caused by the Doppler transition caused by the frequency error and the relative movement speed difference between the transmitter and receiver in local carrier generation, thereby improving the performance degradation of the modem and improving the communication performance of the entire system. It is to provide a circuit for improving.

이하 본 발명은 첨부된 도면을 참조하여 설명되어 질것이며, 도면들중 동일한 부품들은 가능한한 어느 곳에 든지 동일한 부호들을 나타내고 있음을 유의하여야 한다.DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described with reference to the accompanying drawings, in which like parts are denoted by like reference numerals wherever possible.

제2도는 본 발명에 따른 실시예를 설명하기 위한 회로도로서, 중간 주파수(IF) 입력단(100)의 입력신호를 증폭하는 증폭기(201)와, 상기 증폭기(201)의 출력신호는 변조되어 있으므로 위상 변조된 성분을 제거하기 위하여 2배로 체배하는 주파수 체배기(202)와, 상기 주파수 체배기(202)의 출력신호[(t)]로 부터 비트클럭과 캐리어 클럭주파수로 록킹시켜 제1,2주파수(251,252)를 발생하는 제1,2 PLL회로(203,204)와, 상기 제1,2PLL회로(203,204)의 양 출력을 곱셈하여 양 출력에 대한 데이타 비트의 합(+)과 차(-)의 결과에 대해 데이타 캐리어 신호를 출력하는 제5믹서(205)와, 상기 제5믹서(205)의 출력으로 부터 저역을 차단하고 고역을 통과시켜 캐리어를 복구하는 고역통과필터(206)와, 상기 고역통과필터(206)의 출력으로부터 상기 주파수 체배기(202)와 믹서(205)를 거치면서 체배된 주파수를 원래 신호의 주파수로 복구하기 위해 4분주하는 분주기(207)로 구성된다.2 is a circuit diagram illustrating an embodiment according to the present invention, in which an amplifier 201 for amplifying an input signal of an intermediate frequency (IF) input terminal 100 and an output signal of the amplifier 201 are modulated so that a phase A frequency multiplier 202 multiplying to remove the modulated component and the first and second frequencies 251 and 252 by locking to the bit clock and the carrier clock frequency from the output signal [(t)] of the frequency multiplier 202. Multiplying both outputs of the first and second PLL circuits 203 and 204, and the first and second PLL circuits 203 and 204, for the result of the sum (+) and difference (-) of the data bits for both outputs. A fifth mixer 205 for outputting a data carrier signal, a high pass filter 206 for restoring a carrier by cutting low frequencies from the output of the fifth mixer 205, and recovering the carrier, and the high pass filter ( Multiplying through the frequency multiplier 202 and the mixer 205 from the output of 206 It consists of a frequency divider 207 to frequency divider 4 to restore the frequency to the frequency of the original signal.

본 발명에서는 상기 분주기(207)의 출력 즉, 주파수 오차 및 송신단과 수신단간의 상대적 이동 속도차로 발생되는 도플러 천이 현상에 의하여 나타나는 주파수를 보정한 위상변조된 신호가 제거된 순수한 반송파 신호를 제1도와 동일 구성요소로 결합된 회로에서 처리토록 되어 있다.In the present invention, a pure carrier signal from which a phase-modulated signal whose frequency is corrected by a Doppler transition caused by an output of the frequency divider 207, that is, a frequency error and a relative movement speed difference between a transmitter and a receiver, is removed. It is intended to be processed in circuits that are combined into identical components.

따라서 본 발명의 구체적인 실시예를 제2도를 참조하여 상세히 설명하면, 수신단(100)으로 수신된 IF 신호 x(t)는 증폭기(201)에서 증폭된후 수식으로 나타내면 ⑥식과 같이 나타난다.Therefore, when a specific embodiment of the present invention is described in detail with reference to FIG. 2, the IF signal x (t) received by the receiver 100 is amplified by the amplifier 201 and represented by a formula ⑥.

상기 증폭기(201)를 통과한 신호는 변조되어 있으므로 위상 번조 성분을 제거하기 위해 주파수 체배기(202)에서 2로 체배한다.The signal passing through the amplifier 201 is modulated and multiplied by 2 in the frequency multiplier 202 to remove the phase annoying component.

상기 주파수 체배기(202)를 통과한 후의 출력신호[x1(t)]는 하기 ⑦식과 같다.The output signal [x 1 (t)] after passing through the frequency multiplier 202 is expressed by Equation 7 below.

MSK 신호인 경우, 데이터 1과 0에 대한 주파수 w1과 w2는 다음과 같이 정의 된다.For MSK signals, the frequencies w 1 and w 2 for data 1 and 0 are defined as follows.

여기에서 fb데이타 비트 레이트Fb here Data bit rate

상기 주파수 체배기(202)의 출력으로부터 비트클럭과 캐리어클럭을 록킹시키기 위해 제1, 2PLL회로(203,204)에서 록킹이 되면 하기 ⑧, ⑨식과 같다.When locking is performed in the first and second PLL circuits 203 and 204 to lock the bit clock and the carrier clock from the output of the frequency multiplier 202, Equations 8 and 9 are as follows.

상기 제1, 2PLL회로(203,204)의 출력 두신호를 제5믹서(205)에서 곱하여, HPF(206)를 통과한 후의 신호는 하기 ⑨식과 같다. cos(4wOt) + n"(t) ......⑨. 한편 분주기(207)를 상기 주파수체배기(202)와 제5믹서(205)를 거치면서 4체배된 신호를 원래의 주파수로 복구하기 위해 4분주 한다. 이의 결과는 하기 ⑩식과 같다. 즉, 분주기(207)의 출력 신호는 다음과 같이 위상(주파수) 변조된 신호가 제거된 순수한 반송파 신호로 재생된다.The signal after passing through the HPF 206 by multiplying the output two signals of the first and second PLL circuits 203 and 204 by the fifth mixer 205 is expressed by the following equation ⑨. cos (4w O t) + n "(t) ....... 9. Meanwhile, the frequency divider 207 is passed through the frequency multiplier 202 and the fifth mixer 205 to recover the original signal. In order to recover to frequency, the frequency is divided into 4. The result is as follows: The output signal of the frequency divider 207 is reproduced as a pure carrier signal from which a phase (frequency) modulated signal is removed as follows.

또한, VCO(106)의 출력신호가 Vr(t) = 2 cos wit라고 하면, 상기 분주기(207)의 출력신호[S(t)]와 제1,2믹서(101,104)에서 곱해진 후 제1,2저역통과필터(102,103)를 통과한 신호 Il(t)와 Q1(t)는 하기 (11),(12)과 같다.Further, when the output signal of the VCO 106 is Vr (t) = 2 cos wit, the output signal [S (t)] of the divider 207 is multiplied by the first and second mixers 101 and 104, and then The signals I l (t) and Q 1 (t) passing through the first and second low pass filters 102 and 103 are as follows (11) and (12).

여기서 △w = wO- wI이고, nI(t) 및 nQ(t)는 각각 I채널 및 Q채널 잡음신호이다. 이를 제1,2미분기(107,108)에서 미분하면 (13),(14)식과 같이 발생된다.Where Δw = w O −w I , and n I (t) and n Q (t) are I channel and Q channel noise signals, respectively. Differentiating this from the first and second differentiators 107, 108 generates the equations (13) and (14).

이므로 이를 제3,4믹서(110,111)에서 믹싱하면, 출력신호 [I1(t)],[Q2(t)]는 (15),(16)식과 다음과 같이 발생된다.Therefore, when mixing them in the third and fourth mixers 110 and 111, the output signals [I 1 (t)] and [Q 2 (t)] are generated as shown in (15) and (16) as follows.

상기 (15),(16)의 출력을 합성기(112)에서 하면 출력 신호는When the outputs of the above (15) and (16) are performed by the synthesizer 112, the output signal is

상기 합성기(112)의 출력신호는 루우프필터(109)에 입력되어 출력은 -B2(△W)/HLP(w)/2이 되므로, △w에만 비례하는 제어 신호가 출력되어 이신호로 VCO(106)를 제어하므로서 주파수 에러량을 줄여나가게 된다.Since the output signal of the synthesizer 112 is input to the loop filter 109 and the output becomes -B 2 (ΔW) / H LP (w) / 2, a control signal proportional to only Δw is output and thus the VCO By controlling 106, the amount of frequency error is reduced.

상술한 바와같이 종래 기술에서는 위상 변조된 성분의 미분 값인 φ'(t) 성분이 남아 있으므로 해서 정확한 주파수 에러 제어가 어렵지만 본 발명에서는 위상 변조된 성분의 미분값인 φ'(t) 성분을 제거함으로서 정확한 주파수 에러 제어가 가능하므로 모뎀의 성능 저하 현상을 개선시키고, 전체 시스템의 통신 성능을 향상시킨 이점이 있다.As described above, in the prior art, it is difficult to control the frequency error precisely because the φ '(t) component, which is the derivative value of the phase-modulated component, remains, but in the present invention, Accurate frequency error control allows improved modem performance degradation and improved overall system communication performance.

Claims (1)

복조기의 주파수 보정회로에 있어서, 상기 복조기의 중간 주파수(IF) 입력단(100)의 입력신호를 증폭하는 증폭기(201)와, 상기 증폭기(201)의 출력신호의 위상 변조된 성분을 제거하기위해 2배로 체배하는 주파수체배기(202)와, 상기 주파수체배기(202)의 출력신호[x,(t)]로 부터 비트클럭과 캐리어 클럭주파수로 록킹시켜 제1,2주파수(251,252)를 발생하는 제1,2PLL회로(203,204)와, 기 제1,2PLL회로(203,204)의 양 출력을 곱셈하여 양 출력에 대한 데이타 비트 데이트의 합(+)과 차(-)의 결과에 대해 데이타 캐리어신호로 출력하는 제5믹서(205)와, 상기 제5믹서(205)의 출력으로 부터 저역을 차단하고 고역을 통과시켜 캐리어를 복구하는 고역통과 필터(206)와, 상기 고역통과 필터(206)의 출력으로부터 상기 주파수 체배기(202)와 믹서(205)를 거치면서 체배된 주파수를 원래 신호 주파수로 복구하기 4분주하는 분주기(207)로 구성됨을 특징으로 하는 디지탈 변복조기에 있어서 디지탈 주파수 에러 검출 및 보정회로.A frequency correction circuit of a demodulator, comprising: an amplifier (201) for amplifying an input signal of an intermediate frequency (IF) input terminal 100 of the demodulator, and two for removing phase modulated components of an output signal of the amplifier 201. The first and second frequencies 251 and 252 are generated by locking the frequency multiplier 202 multiplied by a double and the bit clock and the carrier clock frequency from the output signal [x, (t)] of the frequency multiplier 202. 2PLL circuits 203 and 204 and the outputs of the first and second PLL circuits 203 and 204 are multiplied to output a data carrier signal for the result of the sum (+) and difference (-) of the data bit data for both outputs. A fifth filter 205, a high pass filter 206 for blocking the low range from the output of the fifth mixer 205, and recovering the carrier by passing the high range, and from the output of the high pass filter 206; The frequency multiplied by passing the frequency multiplier 202 and the mixer 205 is used as the original signal source. Groups in digital modulation and demodulation, characterized by recovering channel composed of a frequency divider 4 frequency divider 207 to a digital frequency error detection and correction module.
KR1019930025521A 1993-11-27 1993-11-27 Circuit for detecting/correcting digital frequency error in digital modulator/demodulator KR100300347B1 (en)

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US7855662B2 (en) 2006-12-01 2010-12-21 Mitsubishi Heavy Industries, Ltd. System for detecting over axle weight vehicle

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DE60112632T2 (en) * 2000-03-10 2006-06-14 Koninkl Philips Electronics Nv Phase-locked loop
WO2022146037A1 (en) * 2020-12-29 2022-07-07 포항공과대학교 산학협력단 Phase shift method using phase shifter and frequency quadrupler, and device performing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7855662B2 (en) 2006-12-01 2010-12-21 Mitsubishi Heavy Industries, Ltd. System for detecting over axle weight vehicle

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