FI97662B - Method for carrier recovery - Google Patents

Abstract

The invention is based on the object of specifying a method for carrier recovery in coherent or quasi-coherent demodulation of digitally transmitted data in which method the effects of a phase drift are reduced. The object is achieved by converting the received signal frequency (fc) by modulation with an oscillator frequency (n . fc) into a frequency (n + 1) fc which is supplied to a PLL circuit. A voltage- controlled oscillator (30) of the PLL circuit has a frequency (n + 1) fc and the output frequency of the voltage-controlled oscillator is divided by (n + 1) so that a signal frequency (fc) is obtained which is largely free of phase drift. A preferred field of application for the present method are radiotelephones. The drawing shows a block diagram of a device for carrying out the method. <IMAGE>

Description

97662

Method for carrier recovery

The invention relates to a method according to the preamble of claim 1.

5 When transmitting digital signals via optical wires or cables or by radio, methods using coherent demodulation are often used. Examples are BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying) and OQPSK (Offset Quadrature 10 Phase Shift Keying). Standard PLL (Phase Locked Loop) circuits or Costas loop circuits or square loop capacitors are commonly used to recover a high frequency carrier. It is disadvantageous in these loop circuits that there may be 15 interfering phase delays in connection with a noisy reception signal. For example, when a square loop circuit is used in conjunction with a multiplier as a phase discriminator, this omission is as high as ½ · 2π = n i.e. 180 °, which in the case of the BPSK method even leads to inversion of the digital signal. The correction can be achieved by a corresponding coding method, for example by differential coding in connection with the BPSK or OQPSK method. However, this has the disadvantage that the probability of errors increases as a result of the occurrence of double errors.

The object of the invention is to develop a method according to the preamble so that the effects of phase omission can be reduced to a minimum.

This object is solved in connection with the method according to the preamble by means of the features of claim 1.

The advantages achieved by the invention are based in particular on the fact that the phase lag that also occurs when the carrier is restored hardly has a negative effect on the error frequency with a worse signal-to-noise ratio.

The preferred field of application 35 of the method according to the invention is digital radiotelephones.

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Embodiments of the invention are illustrated by several figures of the drawing and are explained in more detail below. In the drawing, Fig. 1 shows a schematic circuit diagram 5 of a PLL circuit for a method according to the invention, Fig. 2 shows a block diagram for a carrier recovery device according to the invention and Fig. 3 shows a block diagram for a carrier recovery device according to the invention by MPSK method. In the schematic circuit diagram according to Fig. 1, reference numeral 10 denotes the input of the PLL circuit applied to the method according to the invention, and reference numeral 11 denotes its output. Connected to the input 10 is an amplifier 12, the output of which is connected to the first input 13 of the multiplier 14 of the discriminator 14, respectively. The second input 15 of the multiplier 14 communicates with the output of the voltage controlled oscillator 16. The output of the multiplier 14 is connected via a low-pass filter 17 to the control input 18 of a voltage-controlled oscillator 16, the second output 19 of which corresponds to the output 11 of the PLL circuit-20.

The operation of the PLL circuit described above is as follows. The noisy high frequency signal at input 10 of the PLL circuit follows the equation 25 u '(t) - U0' cos [ω c t + φτ (ΐ)], where ω0 is the carrier frequency and <{> r (t) is the noisy zero phase.

The signal given by the voltage controlled oscillator 16 is 30 u (t) = U0 · sin (ω c t + 4> c), where ω c is the (largely) noise-free phase of the voltage signal of the voltage controlled oscillator 16. Multiplying the signal voltages at the first input 13 and the second input 15 of the multiplier 14 by the multiplier 14 generates a voltage following the equation U (S = U0 · |> ct + 4> r (t)] · Uc sin (o) ct + Φβ).

By means of the low-pass filter 17, an error signal u filtered from the above-mentioned signal voltage is obtained. - u 5 · H (j ω) u0 "10 = - sin [φ - ΦΓ (t)] · H (jw), 2 where H corresponds to the transfer function of the low-pass filter 17. The operating modulation is not taken into account in the above equations 15.

In the block diagram of Fig. 2, extended with respect to the block diagram of Fig. 1 with respect to degrees 22-25 and 31, reference numeral 20 denotes the input of the PLL circuit to reduce phase failure and reference numeral 21 denotes its output.

20 Input 20 is associated with an amplifier 22 and a first input of a mixer 23, the second input of which is connected to a high frequency oscillator 24. The mixer 23 is followed by a bandpass filter 25 and a second amplifier 26, the output of which is connected to the first input of a multiplier (discriminator) 27. The output of the multiplier is connected via a low-pass filter 28 to the control input 29 of a voltage-controlled oscillator 30, the output of which is connected to the second input of the multiplier 27. The second input of the voltage controlled oscillator is connected via a voltage divider 31 to the output 21 of the device.

. The operation mode of the circuit arrangement of Fig. 2 is as follows.

The frequency fc 'of the noisy high frequency signal at input 20 and amplified by amplifier 22 is modulated in mixer 23 at oscillator frequency f0 = n · fc, 35 where n is an integer much greater than 1. The bandpass filter 4 97662 associated with mixer 23 separates frequency (n + 1) fc. The output voltage of the bandpass filter 25 is applied in connection with the amplification by the second amplifier 26 to the first input of the multiplier 27, the second input of which has the output voltage of the voltage-controlled oscillator 30. The voltage from the multiplier passes through the low-pass filter 28 and controls the voltage-controlled oscillator. Further, the conducted oscillator voltage is divided by a voltage divider 31 by a factor (n + 1), so that the signal frequency fc is again available at the output 21 of the circuit arrangement. If there is a phase omission in the PLL circuit, for example 2n, then it affects this frequency fc at output 21 only in the ratio 2π / (η + 1). If n is chosen large enough, then the quality degradation due to the phase delay is insignificant.

15 The stage leave this can be 2n or k · π, depending on the type, in most cases k = 2 or 4.

In the block diagram of Fig. 3 for the MPSK method (M-ARY method), the following limitations have been made with respect to the block diagram of Fig. 2. Between the first amplifier 22 and the mixer 23 there is a series multiplier 36, a bandpass filter 37 and another amplifier 38 in series. There is an additional frequency divider 39 between the voltage controlled oscillator 30 and the output of the circuit arrangement. The frequency multiplier 36 25 multiplies the input frequency fc 'by a factor m; the oscillator 24 included in the mixer 23 has an oscillator frequency f0 to m (n + 1) fc; the additional frequency divider 39 divides the frequency derived for it by a factor m.

The factor, i.e. the divisor m, corresponds to the number of possible phase states in the MPSK method, m is an integer greater than 1. The additional measures given above make it possible to develop a modulation-free carrier. The additional summation m (n + 1) fe by the mixer 23 and the subsequent division by the factor-35 (n + 1) in the frequency divider 31 reduces the phase lag.

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Dividing by the divider m in the frequency divider 39 reconstructs the original carrier frequency fc. The two frequency dividers 31 and 39 can then be combined into a single frequency divider with a division ratio m (n + 1).

Claims (3)

A method of synchronization reset in connection with coherent or rail coherent demodulation of digitally transmitted data, characterized in that in the received signal frequency (fc *), modulation is generated with a signal frequency (n * fc), a frequency (n + 1) fc , where n is an integer greater than 1, that the frequency (n + 1) fc obtained through modulation is fed as a reference frequency to a PLL circuit, whose voltage controlled oscillator (30) has a frequency (n + 1) ) fc and that, by frequency division with the divisor (n + 1), the oscillator frequency obtains a signal frequency (fc) which is substantially free of phase shift. 15 Method according to claim 1, characterized in that the signal frequency (fc ') received from the data transmitted in connection with the MPSK method before the modulation is further multiplied by the factor (m), where m is an integer greater than 1 and that the second frequency division occurs with the divisor of the frequency division (n + 1), with a divisor (m) corresponding to the factor (m). Device for carrying out the method according to claim 2, characterized in that both frequency parts (31, 39) have been combined into a single frequency divider with the partition ratio m (n + 1).