KR100282216B1 - Soi DRAM and its manufacturing method - Google Patents

Abstract

The present invention relates to an SOI DRAM for performing dynamic threshold voltage control and a low Vcc operation, and to a method of manufacturing the same, wherein the storage node electrode of the cell region is electrically connected to a first surface of the first semiconductor substrate having the device isolation layer. And the back gate electrode in the peripheral circuit area at the same time. A plate electrode is formed on the storage node electrode with a capacitor dielectric layer interposed therebetween to form an embedded capacitor. The first semiconductor substrate and the second semiconductor substrate are bonded to each other with the SOI insulating layer interposed therebetween. After the planarization etching of the second surface of the first semiconductor substrate using the device isolation film as an etch stop layer, a front gate electrode is formed on the second surface of the first semiconductor substrate. The bit line is formed to electrically connect the first semiconductor substrate between the front gate electrode and the second surface, and at the same time, the plate contact and the back gate contact are formed to be electrically connected to the plate electrode and the back gate electrode. With such a semiconductor device and its manufacturing method, it is possible to perform dynamic threshold voltage control of the peripheral circuit area using a back gate, and to form a low Vcc operating DRAM using an embedded structure capacitor and an SOI substrate. Can be. In addition, the back gate is formed at the same time as the storage node electrode to simplify the process and reduce the process cost.

Description

A SILICON ON INSULATOR DRAM AND METHOD OF FABRICATING THE SAME

TECHNICAL FIELD The present invention relates to a silicon on insulator (SOI) DRAM and a method for manufacturing the same. More specifically, an embedded capacitor performs dynamic threshold voltage control using a back gate electrode. The present invention relates to an SOI DRAM having an embedded capacitor and a manufacturing method thereof.

Assuming that Vcc is 1.0V, the associated threshold voltage can be defined as 0.15 to 0.2V. At this time, the subthreshold leakage current in the offset state is increased, and in the on state, the mobility of the transistor must be increased. It is a difficult problem to solve.

In the prior art, low Vcc related high integration processes of less than 1.5 V use a back gate poly to dynamically control the threshold voltage of the transistor.

The dynamic threshold voltage control method reduces the subthreshold leakage current in the offset state by increasing the threshold voltage by the back gate when the front gate is off. In the on state, the voltage of the back gate is increased by the front gate voltage so that the threshold voltage is decreased by the influence of the back gate, thereby increasing the mobility of the transistor and thus increasing the current. This is a technology that is only used in SOI.

However, this technique adds a back gate poly between SOIs, which is not suitable for embedded memory in which capacitors exist under active in the DRAM field. The reason for this is that when the process is performed by embedding the capacitor to the bottom, the difficulty of forming the storage node contact of the capacitor and the connection method of the plate poly contact should be solved.

In the case of forming a DRAM by using the prior art, it is inevitable to form a capacitor on the bit line 16 as shown in FIG. 1.

1 is a cross-sectional view showing the structure of a conventional SOI DRAM. Here, portions denoted by "a" and "b" denote cell array regions and peripheral circuit regions, respectively.

Referring to FIG. 1, a conventional SOI DRAM has a sub-silicon 2, a device isolation film 3, and an insulating layer 4 defined by the formation of a device isolation film 3 such as LOCOS. And an intrinsic poly layer (6). The intrinsic poly layer 6 comprises an n + type back gate poly 7a and a p + type back gate poly 7b.

The structure comprises a handle wafer 10 bonded on the intrinsic poly layer 6 with an insulating layer 8 for SOI interposed therebetween. And a bit line 16 formed through the insulating layer 15 between the front gate electrode 14 and electrically connected to the sub silicon 2. And the front gate electrodes 14a and 17b and the back gate contacts 18a and 18b formed to be electrically connected to the front gate electrode 14 and the n + type and p + type back gate polys 7a and 7b, respectively.

A stacked capacitor formed through the insulating layer 15 and the insulating layer 19 and electrically connected to the sub silicon 2, that is, the storage node electrode 20, the capacitor dielectric layer 21, and the plate electrode 22 are formed. Include. And a load poly 23 formed on the insulating layer 19.

The capacitor is formed on the bit line 16.

Metal contacts 26a to 26d formed through the insulating layer 24 or the insulating layers 19 and 24 to be electrically connected to the plate electrode 22, the load poly 23, and the front gate contacts 17a and 17b, respectively. It includes. Metal contacts 29a and 29b formed through the insulating layer 28 and electrically connected to the metal contacts 26c and 26d. And a metal line 27 formed on the insulating layer 24 and a metal line 30 formed on the insulating layer 28.

The present invention has been proposed to solve the above-described problems, and provides a SOI DRAM capable of performing dynamic threshold voltage control using a back gate and simultaneously forming a capacitor having an embedded structure, and a method of manufacturing the same. Has its purpose.

1 is a cross-sectional view showing the structure of a conventional SOI DRAM.

2 is a cross-sectional view showing a structure of an SOI DRAM according to an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing an SOI DRAM according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

2: sub silicon 3, 101: device isolation film

4, 15, 19, 24, 28: insulation layer 6: intrinsic poly layer

7: back gate poly 8, 112: insulation layer for SOI

10: handle wafer 14, 118: front gate electrode

16: bit line 17, 125: front gate contact

18, 126: back gate contact 20, 104a: storage node electrode

21, 105: capacitor dielectric film 22, 106: plate electrode

26, 29, 129, 133: metal contacts 27, 30, 130, 134: metal lines

100: first semiconductor substrate 102: first insulating layer

104: back gate electrode 108, 110: second insulating layer

114: second semiconductor substrate 120: third insulating layer

123: plate contact 124: rod poly contact

[Configuration]

According to the present invention for achieving the above object, a method of manufacturing an SOI DRAM includes a first insulating layer on a first surface of a first semiconductor substrate having a cell region and a peripheral circuit region and having an active region defined by an element isolation film. Forming a; A storage node electrode is formed to penetrate the first insulating layer and is electrically connected to the first semiconductor substrate of the cell region, and at the same time, a back gate electrode insulated from the first semiconductor substrate on the first insulating layer of the peripheral circuit region. Forming a; Forming a plate electrode on the storage node electrode with a capacitor dielectric film interposed therebetween; Forming a second insulating layer on the entire first surface of the first semiconductor substrate including the plate electrode; Bonding the first semiconductor substrate and the second semiconductor substrate on the second insulating layer with an insulating layer for SOI interposed therebetween; Planarization etching the second surface of the first semiconductor substrate until the device isolation layer is exposed; Forming a front gate electrode on a second side of the first semiconductor substrate; Forming a third insulating layer on the entire surface of the second surface of the first semiconductor substrate including the front gate electrode; The third insulating layer, the first insulating layer, and a part of the device isolation layer to be electrically connected to the second surface of the first semiconductor substrate and the plate electrode, the front gate electrode, and the back gate electrode, respectively. Bit lines 122 and plate contacts 123, front gate contacts 125a and 125b, and back gate contacts 126a and 126b are formed, respectively, the front gate contacts 125a and 125b and the back gate contacts 126a, respectively. 126b) is electrically connected.

In a preferred embodiment of the method, the device isolation film comprises forming one of LOCOS and STI methods on the first surface of the first semiconductor substrate.

According to the present invention for achieving the above object, an SOI DRAM has a structure in which a first semiconductor substrate and a second semiconductor substrate are bonded with an insulating layer for SOI interposed therebetween, wherein the first semiconductor substrate is the second semiconductor. A SOI substrate having a relatively thin thickness compared to a substrate and divided into a cell region and a peripheral circuit region, wherein the cell region and the peripheral circuit region have an element isolation film defined by defining an active region and an inactive region; A storage formed to be electrically connected to the cell region of the first semiconductor substrate with an insulating layer interposed between the SOI insulating layer and the first semiconductor substrate, and to be directly connected to the cell region of the first semiconductor substrate. An embedded capacitor comprising a node electrode and a plate electrode formed on the storage node electrode with a capacitor dielectric film interposed therebetween; A back gate electrode formed to be insulated from a peripheral circuit region of the first semiconductor substrate with an insulating layer interposed between the SOI insulating layer and the first semiconductor substrate; A front gate electrode formed on the unbonded surface of the first semiconductor substrate; A bit line formed to be electrically connected to a first semiconductor substrate between the front gate electrode in the cell region; A front gate contact formed to be electrically connected to the front gate electrode in the peripheral circuit region; And a plate contact and a back gate contact formed to penetrate the device isolation layer from the unbonded surface of the first semiconductor substrate and to be electrically connected to the plate electrode and the back gate electrode, respectively.

[Action]

The SOI DRAM and its manufacturing method according to the present invention allow the back gate to be formed at the same time when forming the storage node, and enable the formation of a capacitor of an embedded structure while using the back gate.

EXAMPLE

Referring to FIG. 2, the novel SOI DRAM and its manufacturing method according to the embodiment of the present invention form a storage node electrode in the cell region to be electrically connected to the first surface of the first semiconductor substrate having the device isolation film, At the same time, the back gate electrode of the peripheral circuit area is formed. A plate electrode is formed on the storage node electrode with a capacitor dielectric layer interposed therebetween to form an embedded capacitor. After the top surface of the capacitor is planarized using an insulating layer, the first semiconductor substrate and the second semiconductor substrate are bonded to each other with the insulating layer for SOI interposed therebetween. After the planarization etching of the second surface of the first semiconductor substrate using the device isolation layer as an etch stop layer, a front gate electrode is formed on the second surface of the first semiconductor substrate. A bit line is formed to electrically connect the first semiconductor substrate between the front gate electrode and the second surface, and a plate contact and a back gate contact are respectively formed to be electrically connected to the plate electrode and the back gate electrode. With such a semiconductor device and its manufacturing method, it is possible to perform dynamic threshold voltage control of the peripheral circuit area using a back gate, and to form a low Vcc operating DRAM using an embedded structure capacitor and an SOI substrate. Can be. In addition, the back gate is formed at the same time as the storage node electrode to simplify the process and reduce the process cost.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2 is a cross-sectional view illustrating a structure of an SOI DRAM according to an embodiment of the present invention.

Referring to FIG. 2, the structure of an SOI DRAM according to an exemplary embodiment of the present invention includes an SOI substrate, an embedded capacitor, back gate electrodes 104b and 104c, a front gate electrode 118, a bit line 122, and the like. And front gate contacts 125a and 125b, plate contacts 123, and back gate contacts 126a and 126b.

The SOI substrate has a structure in which the first semiconductor substrate 100 and the second semiconductor substrate 114 are bonded with the SOI insulating layer 112 interposed therebetween. The first semiconductor substrate 100 has a thickness relatively thinner than that of the second semiconductor substrate 114, and has a cell region a and a peripheral circuit region b. The cell region a and the peripheral circuit region b each have an isolation layer 101 formed by defining an active region and an inactive region.

The embedded capacitor may be electrically connected to the cell region a of the first semiconductor substrate 100 with the insulating layers 108 and 110 interposed between the SOI insulating layer 112 and the first semiconductor substrate 100. It is formed so that it may be connected. The embedded capacitor includes a storage node electrode 104a formed to be directly connected to the cell region a of the first semiconductor substrate 100, and a capacitor dielectric layer 105 disposed on the storage node electrode 104a. Formed plate electrode 106.

The back gate electrodes 104b and 104c are formed on the insulating layer 102 of the peripheral circuit region b of the first semiconductor substrate 100, and the front gate electrode 118 is the first semiconductor. It is formed on the unbonded surface of the substrate 100. The front gate electrode 118 is, for example, a multilayer film in which a polysilicon film and a silicide film are stacked, and a gate oxide film is further formed between the front gate electrode 118 and the first semiconductor substrate 100.

The bit line 122 penetrates the insulating layer 120 and is electrically connected to the first semiconductor substrate 100 between the front gate electrode 118.

The front gate contacts 125a and 125b are formed to be electrically connected to the front gate electrode 118 through the insulating layer 120.

The plate contact 123 and the back gate contacts 126a and 126b penetrate through the device isolation film 101 of the first semiconductor substrate 100 from the unbonded surface of the first semiconductor substrate 100 and the plate electrode. It is formed so as to be electrically connected to the 106 and the back gate electrodes 104b and 104c, respectively.

The front gate contacts 125a and 125b and the back gate contacts 126a and 126b are formed to be electrically connected to each other.

In addition to the bit line 122 and the contacts 123, 125a, 125b, 126a, and 126b, the semiconductor device may further include a load poly contact 124 for the rod poly 119, which is a resistance polysilicon film. The insulating layer 128 and the insulating layer 132 formed on the insulating layer 120 including the bit line 122 and the contacts 126 to 126, the metal contacts 129a, 129b, 133a, and 133b, and the metal lines (130, 134) further.

Hereinafter, a method of manufacturing the SOI DRAM as described above will be described in detail with reference to FIGS. 3A to 3E.

Referring to FIG. 3A, the first semiconductor substrate 100 having the cell region a and the peripheral circuit region b, that is, the first insulating layer is formed of an oxide film such as HTO (High Temperature Oxide) on the first surface of the sub silicon. Form layer 102. Each region of the first semiconductor substrate 100 has an isolation layer 101 formed by defining an active region and an inactive region. The device isolation layer 101 is formed by a common LOCOS (LOCal Oxidation of Silicon) or STI (Shallow Trench Isolation). The device isolation layer 101 is used as a stopper in a subsequent planarization etching process of the first semiconductor substrate 100. That is, the device isolation film 101 is a factor for determining the thickness of the active region of the SOI. In addition, the plate contact 123 and the back gate contacts 126a and 126b may be used as etching regions of the first semiconductor substrate 100.

Referring to FIG. 3B, the storage node electrode 104a is formed to penetrate the first insulating layer 102 and to be electrically connected to the first semiconductor substrate 100 of the cell region a. At the same time, back gate electrodes 104b and 104c are formed on the first insulating layer 102 in the peripheral circuit region b.

The storage node electrode 104a forms a storage node contact hole by etching the first insulating layer 102 so that a portion of the first surface of the first semiconductor substrate 100 is exposed. The contact hole is formed by filling a conductive film such as polysilicon and patterning the contact hole. Deposition of the conductive film proceeds in the order of low doping and high doping in the chamber. This is because embedded capacitors are formed early in the DRAM manufacturing process and undergo a number of subsequent thermal processes. The back gate electrodes 104b and 104c are formed of the conductive film used to form the storage node electrode 104a and are formed to control the dynamic threshold voltage of the peripheral circuit region b. By such a process, a separate conductive film forming step for forming the back gate electrodes 104b and 104c can be omitted.

A thin nitride film, an oxide film, and the like are stacked on the cell region a including the storage node electrode 104a to form a capacitor dielectric film 105, and a plate electrode 106 is formed to form an embedded capacitor. The polysilicon film for plate electrodes formed in regions other than the cell region a is removed by overetching. This is necessary in order to prevent the DC bias of OV or more from being applied to the back gate electrodes 104b and 104c in the peripheral circuit region b so as to generate a subthreshold leakage current.

Referring to FIG. 3C, second insulating layers 108 and 110 are formed on the entire surface of the first surface of the first semiconductor substrate 100 including the plate electrode 106. The second insulating layers 108 and 110 include a PSG (PhosphoSilicate Glass) film 110 capable of densifying the film quality in a small subsequent heat treatment process. The top surfaces of the second insulating layers 108 and 110 are planarized by CMP (Chemical Mechanical Polishing) or the like.

Bonding the first semiconductor substrate 100 and the second semiconductor substrate 114, that is, a handle wafer, with the SOI insulating layer 112 therebetween on the second insulating layers 108 and 110. bonding).

Referring to FIG. 3D, the second surface of the first semiconductor substrate 100 is planarized by using the device isolation layer 101 as an etch stop layer. In addition, active patterns are defined by conventional STI methods.

The front gate electrode 118 is formed by stacking and patterning, for example, a polysilicon film and a silicide film on the second surface of the first semiconductor substrate 100 with a gate oxide film interposed therebetween. On the device isolation film 101, a rod poly 119 that is a resistance polysilicon film is formed with an insulating layer such as HTO, PE-TEOS, or PE-SiH ₄ interposed therebetween.

The third insulating layer 120 is formed on the entire surface of the second surface of the first semiconductor substrate 100 including the rod poly 119.

Referring to FIG. 3E, the bit line 122 and the rod poly contact 124, the front gate contact 125a, using tungsten material, for example, using a damascene CMP technique well known in the art. 125b), plate contacts 123, and back gate contacts 126a, 126b are formed, respectively.

When forming the bit line contact hole for forming the bit line 122, contact holes for forming the front gate contacts 125a and 125b and the rod poly contact 124 are formed, respectively. When the contact hole for forming the plate contact 123 is formed, a contact hole for forming the back gate contacts 126a and 126b is formed. The step difference between the plate contact 123 and the back gate contacts 126a and 126b is the same.

Thereafter, the insulating layer 128 and the insulating layer 132, the metal contacts 129a, 129b, 133a, and 133b, the metal lines 130 and 134, and a passivation film (not shown) are formed in a conventional process. SOI DRAM is formed.

The present invention allows the dynamic threshold voltage control of the peripheral circuit region to be performed using a back gate, and can form a low Vcc operating DRAM using an embedded structure capacitor and an SOI substrate. In addition, since the back gate is formed at the same time as the storage node electrode, the process may be simplified and the process cost may be reduced.

Claims (2)

Forming a first insulating layer 102 on the first surface of the first semiconductor substrate 100 having a cell region a and a peripheral circuit region b and having an active region defined by the device isolation film 101. Wow; The storage node electrode 104a is formed to penetrate the first insulating layer 102 and is electrically connected to the first semiconductor substrate 100 of the cell region a while simultaneously forming the storage node electrode 104a in the peripheral circuit region b. Forming back gate electrodes (104b, 104c) insulated from the first semiconductor substrate (100) on the insulating layer (102); Forming a plate electrode (106) on the storage node electrode (104a) with a capacitor dielectric film (105) therebetween; Forming a second insulating layer (108, 110) on the entire first surface of the first semiconductor substrate (100) including the plate electrode (106); Bonding the first semiconductor substrate (100) and the second semiconductor substrate (114) with the insulating layer (112) for SOI interposed on the second insulating layer (108, 110); Planar etching a second surface of the first semiconductor substrate 100 until the device isolation layer 101 is exposed; Forming a front gate electrode (118) on a second surface of the first semiconductor substrate (100); Forming a third insulating layer (120) on the entire surface of the second surface of the first semiconductor substrate (100) including the front gate electrode (118); A second surface of the first semiconductor substrate 100, the plate electrode 106, and the second insulating layer 120, the first insulating layer 102, and a portion of the device isolation layer 101. The bit line 122 and the plate contact 123, the front gate contacts 125a and 125b, and the back gate contact 126a so as to be electrically connected to the front gate electrode 118 and the back gate electrodes 104b and 104c, respectively. 126b), respectively, wherein the front gate contacts (125a, 125b) and the back gate contacts (126a, 126b) are electrically connected. The first semiconductor substrate 100 and the second semiconductor substrate 114 are bonded to each other with the SOI insulating layer 112 interposed therebetween, and the first semiconductor substrate 100 is the second semiconductor substrate 114. The cell isolation layer (a) and the peripheral circuit region (b) have a relatively thin thickness, and are divided into a cell region (a) and a peripheral circuit region (b). An SOI substrate having 101); It is formed to be electrically connected to the cell region a of the first semiconductor substrate 100 with the insulating layers 108 and 110 interposed between the SOI insulating layer 112 and the first semiconductor substrate 100. A plate formed between the storage node electrode 104a formed to be directly connected to the cell region a of the first semiconductor 100 and a capacitor dielectric layer 105 disposed on the storage node electrode 104a. An embedded capacitor comprising an electrode 106; A bag formed to be insulated from the peripheral circuit region b of the first semiconductor substrate 100 with the insulating layers 108 and 110 interposed between the SOI insulating layer 112 and the first semiconductor substrate 100. Gate electrodes 104b and 104c; A front gate electrode 118 formed on an unbonded surface of the first semiconductor substrate 100; A bit line (122) formed to be electrically connected to the first semiconductor substrate (100) between the front gate electrode (118) in the cell region (a); Front gate contacts 125a and 125b formed to be electrically connected to the front gate electrode 118 in the peripheral circuit region b; A plate contact 123 formed to penetrate the device isolation layer 101 from the unbonded surface of the first semiconductor substrate 100 and to be electrically connected to the plate electrode 106 and the back gate electrodes 104b and 104c, respectively. And back gate contacts (126a, 126b).