KR100276146B1 - 집적 회로 제조 방법 - Google Patents

집적 회로 제조 방법 Download PDF

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Publication number
KR100276146B1
KR100276146B1 KR1019930023860A KR930023860A KR100276146B1 KR 100276146 B1 KR100276146 B1 KR 100276146B1 KR 1019930023860 A KR1019930023860 A KR 1019930023860A KR 930023860 A KR930023860 A KR 930023860A KR 100276146 B1 KR100276146 B1 KR 100276146B1
Authority
KR
South Korea
Prior art keywords
dielectric layer
layer
substrate
window
teos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019930023860A
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English (en)
Korean (ko)
Other versions
KR940012505A (ko
Inventor
알러그빈 데이요
디. 칸사 프랭클린
알. 올라수포 콜라올
Original Assignee
죤 제이. 키세인
에이 티 앤드 티 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 죤 제이. 키세인, 에이 티 앤드 티 코포레이션 filed Critical 죤 제이. 키세인
Publication of KR940012505A publication Critical patent/KR940012505A/ko
Application granted granted Critical
Publication of KR100276146B1 publication Critical patent/KR100276146B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H10D64/011—
    • H10W20/081—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
  • ing And Chemical Polishing (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
KR1019930023860A 1992-11-12 1993-11-11 집적 회로 제조 방법 Expired - Lifetime KR100276146B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/975,235 US5268332A (en) 1992-11-12 1992-11-12 Method of integrated circuit fabrication having planarized dielectrics
US975,235 1992-11-12

Publications (2)

Publication Number Publication Date
KR940012505A KR940012505A (ko) 1994-06-23
KR100276146B1 true KR100276146B1 (ko) 2001-01-15

Family

ID=25522812

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930023860A Expired - Lifetime KR100276146B1 (ko) 1992-11-12 1993-11-11 집적 회로 제조 방법

Country Status (5)

Country Link
US (1) US5268332A (cg-RX-API-DMAC10.html)
EP (1) EP0597634A3 (cg-RX-API-DMAC10.html)
JP (1) JPH06224188A (cg-RX-API-DMAC10.html)
KR (1) KR100276146B1 (cg-RX-API-DMAC10.html)
TW (1) TW247370B (cg-RX-API-DMAC10.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2926864B2 (ja) * 1990-04-12 1999-07-28 ソニー株式会社 銅系金属膜のエッチング方法
US6297110B1 (en) 1994-07-29 2001-10-02 Stmicroelectronics, Inc. Method of forming a contact in an integrated circuit
AU718096C (en) 1995-06-07 2001-11-22 Noven Pharmaceuticals, Inc. Transdermal compositions containing low molecular weight drugs which are liquid at room temperatures
CN102157437B (zh) * 2010-02-11 2013-12-25 中国科学院微电子研究所 半导体结构的形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4708770A (en) * 1986-06-19 1987-11-24 Lsi Logic Corporation Planarized process for forming vias in silicon wafers
DE3686721D1 (de) * 1986-10-08 1992-10-15 Ibm Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric

Also Published As

Publication number Publication date
EP0597634A3 (en) 1994-08-24
KR940012505A (ko) 1994-06-23
TW247370B (cg-RX-API-DMAC10.html) 1995-05-11
EP0597634A2 (en) 1994-05-18
US5268332A (en) 1993-12-07
JPH06224188A (ja) 1994-08-12

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