KR100275407B1 - 컴퓨터 버스 상의 공유 자원에 대한 신속한 액세스 - Google Patents

컴퓨터 버스 상의 공유 자원에 대한 신속한 액세스 Download PDF

Info

Publication number
KR100275407B1
KR100275407B1 KR1019980706203A KR19980706203A KR100275407B1 KR 100275407 B1 KR100275407 B1 KR 100275407B1 KR 1019980706203 A KR1019980706203 A KR 1019980706203A KR 19980706203 A KR19980706203 A KR 19980706203A KR 100275407 B1 KR100275407 B1 KR 100275407B1
Authority
KR
South Korea
Prior art keywords
bus
memory
control
controller
row address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980706203A
Other languages
English (en)
Korean (ko)
Other versions
KR19990082470A (ko
Inventor
쿨지트 에스. 베인스
케네쓰 엠. 크록커
데이비드 이. 프레커
Original Assignee
피터 엔. 데트킨
인텔 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24401666&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR100275407(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 피터 엔. 데트킨, 인텔 코오퍼레이션 filed Critical 피터 엔. 데트킨
Publication of KR19990082470A publication Critical patent/KR19990082470A/ko
Application granted granted Critical
Publication of KR100275407B1 publication Critical patent/KR100275407B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Dram (AREA)
KR1019980706203A 1996-02-12 1996-07-18 컴퓨터 버스 상의 공유 자원에 대한 신속한 액세스 Expired - Fee Related KR100275407B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/599,921 US5678009A (en) 1996-02-12 1996-02-12 Method and apparatus providing fast access to a shared resource on a computer bus
US8/599,921 1996-02-12

Publications (2)

Publication Number Publication Date
KR19990082470A KR19990082470A (ko) 1999-11-25
KR100275407B1 true KR100275407B1 (ko) 2000-12-15

Family

ID=24401666

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980706203A Expired - Fee Related KR100275407B1 (ko) 1996-02-12 1996-07-18 컴퓨터 버스 상의 공유 자원에 대한 신속한 액세스

Country Status (8)

Country Link
US (1) US5678009A (enExample)
JP (1) JP3749732B2 (enExample)
KR (1) KR100275407B1 (enExample)
AU (1) AU6502396A (enExample)
DE (1) DE19681745B4 (enExample)
GB (1) GB2325320B (enExample)
TW (1) TW353167B (enExample)
WO (1) WO1997029430A1 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09245179A (ja) * 1996-03-08 1997-09-19 Mitsubishi Electric Corp コンピュータグラフィックス装置
US5802395A (en) * 1996-07-08 1998-09-01 International Business Machines Corporation High density memory modules with improved data bus performance
EP0844567A1 (en) * 1996-11-21 1998-05-27 Hewlett-Packard Company Long haul PCI-to-PCI bridge
US5867180A (en) * 1997-03-13 1999-02-02 International Business Machines Corporation Intelligent media memory statically mapped in unified memory architecture
US5941968A (en) * 1997-04-14 1999-08-24 Advanced Micro Devices, Inc. Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
GB2326065B (en) * 1997-06-05 2002-05-29 Mentor Graphics Corp A scalable processor independent on-chip bus
US6052133A (en) * 1997-06-27 2000-04-18 S3 Incorporated Multi-function controller and method for a computer graphics display system
US6157398A (en) * 1997-12-30 2000-12-05 Micron Technology, Inc. Method of implementing an accelerated graphics port for a multiple memory controller computer system
US7395302B2 (en) 1998-03-31 2008-07-01 Intel Corporation Method and apparatus for performing horizontal addition and subtraction
US6418529B1 (en) * 1998-03-31 2002-07-09 Intel Corporation Apparatus and method for performing intra-add operation
US7392275B2 (en) * 1998-03-31 2008-06-24 Intel Corporation Method and apparatus for performing efficient transformations with horizontal addition and subtraction
US6317801B1 (en) * 1998-07-27 2001-11-13 Intel Corporation System for post-driving and pre-driving bus agents on a terminated data bus
US6483516B1 (en) * 1998-10-09 2002-11-19 National Semiconductor Corporation Hierarchical texture cache
US6801207B1 (en) * 1998-10-09 2004-10-05 Advanced Micro Devices, Inc. Multimedia processor employing a shared CPU-graphics cache
US6452601B1 (en) * 1999-05-20 2002-09-17 International Business Machines Corporation Pixel component packing, unpacking, and modification
US6633296B1 (en) * 2000-05-26 2003-10-14 Ati International Srl Apparatus for providing data to a plurality of graphics processors and method thereof
US6636939B1 (en) * 2000-06-29 2003-10-21 Intel Corporation Method and apparatus for processor bypass path to system memory
US6816938B2 (en) * 2001-03-27 2004-11-09 Synopsys, Inc. Method and apparatus for providing a modular system on-chip interface
US6976121B2 (en) * 2002-01-28 2005-12-13 Intel Corporation Apparatus and method to track command signal occurrence for DRAM data transfer
US6976120B2 (en) * 2002-01-28 2005-12-13 Intel Corporation Apparatus and method to track flag transitions for DRAM data transfer
TW548419B (en) * 2002-02-01 2003-08-21 Via Tech Inc Circuit structure of integrated graphing function chip and its test method
US7038687B2 (en) * 2003-06-30 2006-05-02 Intel Corporation System and method for high-speed communications between an application processor and coprocessor
JP2005128963A (ja) * 2003-10-27 2005-05-19 Toshiba Information Systems (Japan) Corp 記憶制御装置及びｄｍａ転送が可能な制御システム
US7370125B2 (en) * 2003-11-25 2008-05-06 Intel Corporation Stream under-run/over-run recovery
US7346716B2 (en) 2003-11-25 2008-03-18 Intel Corporation Tracking progress of data streamer
US20050143843A1 (en) * 2003-11-25 2005-06-30 Zohar Bogin Command pacing
TWI277877B (en) * 2005-03-08 2007-04-01 Via Tech Inc Method and related apparatus for monitoring system bus
US8397006B2 (en) * 2010-01-28 2013-03-12 Freescale Semiconductor, Inc. Arbitration scheme for accessing a shared resource
GB2626544B (en) * 2023-01-24 2025-02-19 Advanced Risc Mach Ltd Shared resource access control

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
US5517626A (en) * 1990-05-07 1996-05-14 S3, Incorporated Open high speed bus for microcomputer system
US5289584A (en) * 1991-06-21 1994-02-22 Compaq Computer Corp. Memory system with FIFO data input
US5448703A (en) * 1993-05-28 1995-09-05 International Business Machines Corporation Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus
AU1845597A (en) * 1996-02-09 1997-08-28 Intel Corporation Apparatus for programmably defining the access latency

Also Published As

Publication number Publication date
GB9817416D0 (en) 1998-10-07
DE19681745B4 (de) 2010-12-02
AU6502396A (en) 1997-08-28
GB2325320A (en) 1998-11-18
JP3749732B2 (ja) 2006-03-01
GB2325320B (en) 2000-06-14
DE19681745T1 (de) 1998-12-24
JP2000505573A (ja) 2000-05-09
US5678009A (en) 1997-10-14
WO1997029430A1 (en) 1997-08-14
KR19990082470A (ko) 1999-11-25
TW353167B (en) 1999-02-21

Similar Documents

Publication Publication Date Title
KR100275407B1 (ko) 컴퓨터 버스 상의 공유 자원에 대한 신속한 액세스
US4818932A (en) Concurrent memory access system
US5664117A (en) Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer
US5276886A (en) Hardware semaphores in a multi-processor environment
US4181974A (en) System providing multiple outstanding information requests
KR910017296A (ko) 멀티-마스터 버스 파이프라이닝 실행방법 및 장치
US6070204A (en) Method and apparatus for using universal serial bus keyboard to control DOS operations
US6289406B1 (en) Optimizing the performance of asynchronous bus bridges with dynamic transactions
US5664122A (en) Method and apparatus for sequencing buffers for fast transfer of data between buses
US5678064A (en) Local bus-ISA bridge for supporting PIO and third party DMA data transfers to IDE drives
US4236203A (en) System providing multiple fetch bus cycle operation
KR950008231B1 (ko) 퍼스널 컴퓨터 시스템
US6085261A (en) Method and apparatus for burst protocol in a data processing system
JP2002132701A (ja) メモリ制御装置
US5768550A (en) Bus interface logic system
EP0261751A2 (en) Concurrent memory access system
US4245299A (en) System providing adaptive response in information requesting unit
US5680591A (en) Method and apparatus for monitoring a row address strobe signal in a graphics controller
JPH06214945A (ja) コンピュータシステム及び情報の高速転送方法
US5809534A (en) Performing a write cycle to memory in a multi-processor system
EP0488566A2 (en) Method and apparatus for fast page mode selection
JP3720872B2 (ja) システムメモリとｐｃｉマスタ装置との間のデータの転送を最適化するための方法、およびコンピュータにおけるメモリアクセス時間を最適化するためのシステム
KR100441996B1 (ko) 직접 메모리 액세스 제어기 및 제어 방법
US5325515A (en) Single-component memory controller utilizing asynchronous state machines
US6718400B1 (en) Data accessing system with an access request pipeline and access method thereof

Legal Events

Date Code Title Description
A201 Request for examination
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20090918

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20100922

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20100922

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000