AU1845597A - Apparatus for programmably defining the access latency - Google Patents

Apparatus for programmably defining the access latency

Info

Publication number
AU1845597A
AU1845597A AU18455/97A AU1845597A AU1845597A AU 1845597 A AU1845597 A AU 1845597A AU 18455/97 A AU18455/97 A AU 18455/97A AU 1845597 A AU1845597 A AU 1845597A AU 1845597 A AU1845597 A AU 1845597A
Authority
AU
Australia
Prior art keywords
access latency
programmably
defining
programmably defining
latency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU18455/97A
Inventor
Kuljit S Bains
Zohar Bogin
Nilesh V. Shah
David C. Smyth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU1845597A publication Critical patent/AU1845597A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
AU18455/97A 1996-02-09 1997-02-07 Apparatus for programmably defining the access latency Abandoned AU1845597A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US59905896A 1996-02-09 1996-02-09
US599058 1996-02-09
PCT/US1997/001410 WO1997029432A1 (en) 1996-02-09 1997-02-07 Apparatus for programmably defining the access latency

Publications (1)

Publication Number Publication Date
AU1845597A true AU1845597A (en) 1997-08-28

Family

ID=24398029

Family Applications (1)

Application Number Title Priority Date Filing Date
AU18455/97A Abandoned AU1845597A (en) 1996-02-09 1997-02-07 Apparatus for programmably defining the access latency

Country Status (3)

Country Link
AU (1) AU1845597A (en)
TW (1) TW445414B (en)
WO (1) WO1997029432A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5678009A (en) * 1996-02-12 1997-10-14 Intel Corporation Method and apparatus providing fast access to a shared resource on a computer bus
US6266718B1 (en) * 1998-10-14 2001-07-24 Micron Technology, Inc. Apparatus for controlling data transfer operations between a memory and devices having respective latencies
US6304923B1 (en) * 1998-10-14 2001-10-16 Micron Technology, Inc. Method for prioritizing data transfer request by comparing a latency identifier value received from an I/O device with a predetermined range of values
US6438629B1 (en) * 1999-02-02 2002-08-20 Maxtor Corporation Storage device buffer access control in accordance with a monitored latency parameter
US8104039B2 (en) 2006-08-07 2012-01-24 International Business Machines Corporation Method for balancing resource sharing and application latency within a data processing system
WO2008117246A1 (en) 2007-03-28 2008-10-02 Nxp B.V. Multiprocessing system and method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03177893A (en) * 1989-12-06 1991-08-01 Toshiba Corp Multiwindow display device
ATE154714T1 (en) * 1992-01-21 1997-07-15 Compaq Computer Corp CIRCUIT AND METHOD FOR DRAWING LINES IN A VIDEOGRAPHIC SYSTEM
US5450542A (en) * 1993-11-30 1995-09-12 Vlsi Technology, Inc. Bus interface with graphics and system paths for an integrated memory system
US5555383A (en) * 1994-11-07 1996-09-10 International Business Machines Corporation Peripheral component interconnect bus system having latency and shadow timers

Also Published As

Publication number Publication date
TW445414B (en) 2001-07-11
WO1997029432A1 (en) 1997-08-14

Similar Documents

Publication Publication Date Title
AU3341395A (en) Vibration-compensating apparatus
AUPN833096A0 (en) Access device
AU3095595A (en) Dimension-measuring apparatus
AU683779B2 (en) Tablet-manufacturing device
AUPP175198A0 (en) Access device
AUPP175098A0 (en) Access device
AU3497297A (en) Roller-ski apparatus
AU1616195A (en) Device for describing arcs
AU1226095A (en) Language-information providing apparatus
AU4575597A (en) Manure-collection device
AU679312B2 (en) Apparatus for electro-fishing
AU1802297A (en) Device
AU1733997A (en) Blower-vacuum apparatus
AU1656397A (en) Finger-protective device
AU3140997A (en) Photoelectrochemical-electrochromic device
AU1845597A (en) Apparatus for programmably defining the access latency
AUPN755496A0 (en) Size reduction apparatus
AU3391895A (en) Supports
AU1805897A (en) An adjustable bed
AU2985395A (en) Anti-pecking device
AU2378697A (en) Product-transporting device
AU2354295A (en) Suspension-treating device
AU4828297A (en) Access device
AU2987097A (en) De-wiring apparatus
AU3345497A (en) Distance-holding device