DE19681745B4 - Verfahren zum Übergeben der Kontrolle des Zugriffs auf einen Hauptspeicher von einer Speichersteuereinrichtung auf eine weitere Steuereinrichtung und ein solches Verfahren ausführendes Computersystem - Google Patents

Verfahren zum Übergeben der Kontrolle des Zugriffs auf einen Hauptspeicher von einer Speichersteuereinrichtung auf eine weitere Steuereinrichtung und ein solches Verfahren ausführendes Computersystem Download PDF

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Publication number
DE19681745B4
DE19681745B4 DE19681745T DE19681745T DE19681745B4 DE 19681745 B4 DE19681745 B4 DE 19681745B4 DE 19681745 T DE19681745 T DE 19681745T DE 19681745 T DE19681745 T DE 19681745T DE 19681745 B4 DE19681745 B4 DE 19681745B4
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DE
Germany
Prior art keywords
memory
control device
ras
bus
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19681745T
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German (de)
English (en)
Other versions
DE19681745T1 (de
Inventor
Kuljit S. Folsom Bains
Kenneth M. Orangevale Crocker
David E. Folsom Freker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
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Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24401666&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE19681745(B4) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19681745T1 publication Critical patent/DE19681745T1/de
Application granted granted Critical
Publication of DE19681745B4 publication Critical patent/DE19681745B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Dram (AREA)
DE19681745T 1996-02-12 1996-07-18 Verfahren zum Übergeben der Kontrolle des Zugriffs auf einen Hauptspeicher von einer Speichersteuereinrichtung auf eine weitere Steuereinrichtung und ein solches Verfahren ausführendes Computersystem Expired - Fee Related DE19681745B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/599,921 US5678009A (en) 1996-02-12 1996-02-12 Method and apparatus providing fast access to a shared resource on a computer bus
US08/599,921 1996-02-12
PCT/US1996/011941 WO1997029430A1 (en) 1996-02-12 1996-07-18 Fast access to a shared resource on a computer bus

Publications (2)

Publication Number Publication Date
DE19681745T1 DE19681745T1 (de) 1998-12-24
DE19681745B4 true DE19681745B4 (de) 2010-12-02

Family

ID=24401666

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19681745T Expired - Fee Related DE19681745B4 (de) 1996-02-12 1996-07-18 Verfahren zum Übergeben der Kontrolle des Zugriffs auf einen Hauptspeicher von einer Speichersteuereinrichtung auf eine weitere Steuereinrichtung und ein solches Verfahren ausführendes Computersystem

Country Status (8)

Country Link
US (1) US5678009A (enExample)
JP (1) JP3749732B2 (enExample)
KR (1) KR100275407B1 (enExample)
AU (1) AU6502396A (enExample)
DE (1) DE19681745B4 (enExample)
GB (1) GB2325320B (enExample)
TW (1) TW353167B (enExample)
WO (1) WO1997029430A1 (enExample)

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JPH09245179A (ja) * 1996-03-08 1997-09-19 Mitsubishi Electric Corp コンピュータグラフィックス装置
US5802395A (en) * 1996-07-08 1998-09-01 International Business Machines Corporation High density memory modules with improved data bus performance
EP0844567A1 (en) * 1996-11-21 1998-05-27 Hewlett-Packard Company Long haul PCI-to-PCI bridge
US5867180A (en) * 1997-03-13 1999-02-02 International Business Machines Corporation Intelligent media memory statically mapped in unified memory architecture
US5941968A (en) * 1997-04-14 1999-08-24 Advanced Micro Devices, Inc. Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
GB2326065B (en) * 1997-06-05 2002-05-29 Mentor Graphics Corp A scalable processor independent on-chip bus
US6052133A (en) * 1997-06-27 2000-04-18 S3 Incorporated Multi-function controller and method for a computer graphics display system
US6157398A (en) * 1997-12-30 2000-12-05 Micron Technology, Inc. Method of implementing an accelerated graphics port for a multiple memory controller computer system
US7395302B2 (en) 1998-03-31 2008-07-01 Intel Corporation Method and apparatus for performing horizontal addition and subtraction
US6418529B1 (en) * 1998-03-31 2002-07-09 Intel Corporation Apparatus and method for performing intra-add operation
US7392275B2 (en) * 1998-03-31 2008-06-24 Intel Corporation Method and apparatus for performing efficient transformations with horizontal addition and subtraction
US6317801B1 (en) * 1998-07-27 2001-11-13 Intel Corporation System for post-driving and pre-driving bus agents on a terminated data bus
US6483516B1 (en) * 1998-10-09 2002-11-19 National Semiconductor Corporation Hierarchical texture cache
US6801207B1 (en) * 1998-10-09 2004-10-05 Advanced Micro Devices, Inc. Multimedia processor employing a shared CPU-graphics cache
US6452601B1 (en) * 1999-05-20 2002-09-17 International Business Machines Corporation Pixel component packing, unpacking, and modification
US6633296B1 (en) * 2000-05-26 2003-10-14 Ati International Srl Apparatus for providing data to a plurality of graphics processors and method thereof
US6636939B1 (en) * 2000-06-29 2003-10-21 Intel Corporation Method and apparatus for processor bypass path to system memory
US6816938B2 (en) * 2001-03-27 2004-11-09 Synopsys, Inc. Method and apparatus for providing a modular system on-chip interface
US6976121B2 (en) * 2002-01-28 2005-12-13 Intel Corporation Apparatus and method to track command signal occurrence for DRAM data transfer
US6976120B2 (en) * 2002-01-28 2005-12-13 Intel Corporation Apparatus and method to track flag transitions for DRAM data transfer
TW548419B (en) * 2002-02-01 2003-08-21 Via Tech Inc Circuit structure of integrated graphing function chip and its test method
US7038687B2 (en) * 2003-06-30 2006-05-02 Intel Corporation System and method for high-speed communications between an application processor and coprocessor
JP2005128963A (ja) * 2003-10-27 2005-05-19 Toshiba Information Systems (Japan) Corp 記憶制御装置及びｄｍａ転送が可能な制御システム
US7370125B2 (en) * 2003-11-25 2008-05-06 Intel Corporation Stream under-run/over-run recovery
US7346716B2 (en) 2003-11-25 2008-03-18 Intel Corporation Tracking progress of data streamer
US20050143843A1 (en) * 2003-11-25 2005-06-30 Zohar Bogin Command pacing
TWI277877B (en) * 2005-03-08 2007-04-01 Via Tech Inc Method and related apparatus for monitoring system bus
US8397006B2 (en) * 2010-01-28 2013-03-12 Freescale Semiconductor, Inc. Arbitration scheme for accessing a shared resource
GB2626544B (en) * 2023-01-24 2025-02-19 Advanced Risc Mach Ltd Shared resource access control

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289584A (en) * 1991-06-21 1994-02-22 Compaq Computer Corp. Memory system with FIFO data input
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
WO1997029432A1 (en) * 1996-02-09 1997-08-14 Intel Corporation Apparatus for programmably defining the access latency

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517626A (en) * 1990-05-07 1996-05-14 S3, Incorporated Open high speed bus for microcomputer system
US5448703A (en) * 1993-05-28 1995-09-05 International Business Machines Corporation Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
US5289584A (en) * 1991-06-21 1994-02-22 Compaq Computer Corp. Memory system with FIFO data input
WO1997029432A1 (en) * 1996-02-09 1997-08-14 Intel Corporation Apparatus for programmably defining the access latency

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Hermann Eichele, Multiprozessorsysteme, B.G.Teubner Stuttgart, 1990, S.128-132 *

Also Published As

Publication number Publication date
GB9817416D0 (en) 1998-10-07
AU6502396A (en) 1997-08-28
GB2325320A (en) 1998-11-18
JP3749732B2 (ja) 2006-03-01
GB2325320B (en) 2000-06-14
DE19681745T1 (de) 1998-12-24
KR100275407B1 (ko) 2000-12-15
JP2000505573A (ja) 2000-05-09
US5678009A (en) 1997-10-14
WO1997029430A1 (en) 1997-08-14
KR19990082470A (ko) 1999-11-25
TW353167B (en) 1999-02-21

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Legal Events

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8110 Request for examination paragraph 44
8363 Opposition against the patent
R026 Opposition filed against patent

Effective date: 20110227

8339 Ceased/non-payment of the annual fee
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20110215

R008 Case pending at federal patent court
R009 Remittal by federal patent court to dpma for new decision or registration
R031 Decision of examining division/federal patent court maintaining patent unamended now final
R031 Decision of examining division/federal patent court maintaining patent unamended now final

Effective date: 20141202