KR100274340B1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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KR100274340B1
KR100274340B1 KR1019970022003A KR19970022003A KR100274340B1 KR 100274340 B1 KR100274340 B1 KR 100274340B1 KR 1019970022003 A KR1019970022003 A KR 1019970022003A KR 19970022003 A KR19970022003 A KR 19970022003A KR 100274340 B1 KR100274340 B1 KR 100274340B1
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South Korea
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titanium silicide
silicide layer
layer
silicon
heat treatment
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KR1019970022003A
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Korean (ko)
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KR19980085832A (en
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진성곤
류인철
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent leakage current and obtain a stable contact resistance by retraining the formation of TiSi2 due to a reaction of Ti and Si. CONSTITUTION: A titanium silicide layer(21) is formed on a silicon substrate(20) including a contact hole by using a titanium silicide target including a silicon. A TiN layer(22) is deposited on the titanium silicide layer(21) by using a reactive sputtering method. A stable titanium silicide layer(23) is formed by performing a furnace annealing process using a rapid thermal process system or a furnace. The stable titanium silicide layer(23) is formed by reacting the titanium silicide layer(21) with a junction portion(24). The furnace annealing process using the furnace is performed under 500 to 700 degrees centigrade during 5 to 30 minutes whereas the furnace annealing process using the rapid thermal process system is performed under 500 to 700 degrees centigrade during 5 seconds to 2 minutes.

Description

반도체 소자의 제조 방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자 제조 공정에 관한 것으로, 특히 실리콘이 함유된 타티타늄실리사이드 타겟을 이용하여 콘택홀을 포함한 전면에 타이타늄실리사이드층을 형성한 후 열처리 공정을 실시하여 접합부의 실리콘 소모가 없는 안정된 타이타늄실리사이드층을 형성하는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing process. In particular, by using a titanium silicide target containing silicon, a titanium silicide layer is formed on the entire surface including a contact hole, and then a heat treatment process is performed to stabilize the titanium silicide without using silicon at the junction. A metal wiring formation method of a semiconductor element which forms a layer.

종래에는 금속 배선 형성시 실리콘과의 양호한 오믹 콘택(ohmic contact) 형성을 위한 베리어 금속막(barrier metal) 증착시, 도 1(a)에서와 같이 먼저 타이타늄(11)을 증착한 후, 도 1(b)에서와 같이 타이타늄나이트라이드(TiN;12)를 증착하는 방법을 택하고 있다. 이때 증착된 타이타늄(11)은 후속 열처리시 접합(junction) 영역(14)의 실리콘과 반응하여 비저항이 낮은 타이타늄실리사이드(TiSi2; 13)를 형성하고 또 콘택 식각(contack etch)시에 발생하는 손상층(damage layer)이나 결함층(defect layer), 자연 산화막 등을 제거하여 안정된 콘택 저항을 얻고 있다.Conventionally, when depositing a barrier metal film for forming a good ohmic contact with silicon when forming a metal wiring, the titanium 11 is first deposited as shown in FIG. As in b), a method of depositing titanium nitride (TiN) 12 is employed. At this time, the deposited titanium 11 reacts with silicon in the junction region 14 during subsequent heat treatment to form titanium silicide (TiSi 2 ; 13) having a low specific resistance, and damage occurring at the time of contact etching. A stable contact resistance is obtained by removing a damage layer, a defect layer, a natural oxide film, and the like.

그러나 반도체 소자가 고집적화 됨에 따라 접합 깊이(junction depth)가 매우 얕은 접합(ultra shallow junction; 〈 0.1∼0.15㎛)으로 감소함에 따라 기존의 방식으로 베리어 금속막(barrier metal)을 증착할 경우, 도 2(a)에서 보이는 바와 같이, 타이타늄(11)과 접합영역(14)의 실리콘과의 반응에 의한 TiSi2(13) 형성시 도판트(dopant) 및 접합영역의 실리콘이 과도하게 소모된다. 이로 인하여 누설전류 및 콘택저항의 증가를 가져온다. 또한 이러한 TiSi2(13)가 접합 깊이보다 더 깊게 생성될 경우에는 도 2(b)와 같이 접합 파괴를 가져오게 된다.However, as the semiconductor device is highly integrated, the junction depth is reduced to an ultra shallow junction (<0.1 to 0.15 µm), and when the barrier metal film is deposited in the conventional manner, FIG. 2 As shown in (a), the silicon of the dopant and the junction region is excessively consumed when the TiSi 2 (13) is formed by the reaction of the titanium 11 and the silicon of the junction region 14. This results in an increase in leakage current and contact resistance. In addition, when the TiSi 2 (13) is formed deeper than the junction depth, as shown in Fig. 2 (b) it leads to junction failure.

기존의 또다른 방법인 타이타늄실리사이드(TiSix;x〉2) 타겟(target)을 사용하여 확산방지용 금속막(barrier matel)을 증착하는 경우에도 타이타늄보다 낮은 비저항의 TiSi2가 증착되어 비교적 안정된 콘택 저항이 얻어지나, 접합부위의 실리콘과 반응이 거의 일어나지 않기 때문에 콘택 식각시에 발생하는 손상층이나 결함층, 자연 산화막을 거의 제거할 수가 없기 때문에 소자 적용에 한계를 갖고 있다.In the case of depositing a barrier matel using another method, a titanium silicide (TiSi x ; x> 2) target, TiSi 2 having a specific resistivity lower than that of titanium is deposited so that a relatively stable contact resistance is achieved. However, since the reaction with the silicon at the junction is hardly generated, the damage layer, the defect layer, and the natural oxide film generated at the time of contact etching can hardly be removed, thereby limiting the device application.

따라서, 본 발명은 반도체 소자의 고집적화로 인하여 접합 깊이가 매우 얕은 접합으로 감소하여도 베리어 금속막 증착시 Ti과 Si의 반응에 의한 과도한 TiSi2형성을 억제하여 누설전류(leakage current)를 방지하고 안정된 콘택 저항을 얻을 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention prevents excessive leakage of TiSi 2 due to the reaction of Ti and Si during deposition of the barrier metal film and prevents leakage current even when the junction depth is reduced to a very shallow junction due to the high integration of semiconductor devices. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of obtaining a contact resistance.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 콘택 홀이 형성된 실리콘 기판이 제공되는 단계와, 상기 콘택 홀을 포함하는 전체 구조 상부에 실리콘이 함유된 타이타늄실리사이드 타겟을 이용하여 타이타늄실리사이드층을 증착하는 단계와, 열처리 공정을 실시하여 접합 영역에 안정된 타이타늄실리사이드층을 형성하는 단계로 이루어진 것을 특징으로 한다.The semiconductor device manufacturing method according to the present invention for achieving the above object is provided by the step of providing a silicon substrate with a contact hole, and using a titanium silicide target containing silicon on the entire structure including the contact hole And depositing a silicide layer and forming a stable titanium silicide layer in the junction region by performing a heat treatment process.

도 1(a) 및 도 1(b)는 종래의 메탈 콘택 형성 방법의 일 실시 예를 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of devices sequentially shown to illustrate one embodiment of a conventional metal contact formation method.

도 2(a) 및 도(2b)는 종래의 메탈 콘택 형성 방법의 다른 실시 예를 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) and 2 (b) are cross-sectional views of devices sequentially shown to explain another embodiment of the conventional metal contact forming method.

도 3(a) 내지 도 3(c)는 본 발명에 따른 메탈 콘택 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.Figure 3 (a) to Figure 3 (c) is a cross-sectional view of the device sequentially shown to explain the metal contact forming method according to the present invention.

〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>

10 및 20 : 실리콘 기판 11 : Ti층10 and 20: silicon substrate 11: Ti layer

12 : TiN층 13 및 23 : TiSi2층12: TiN layer 13 and 23: TiSi 2 layer

14 및 24 : 접합(junction) 영역 21 : TiSix층14 and 24: junction region 21: TiSi x layer

22 : TiN층 또는 TiSixNy층22: TiN layer or TiSi x N y layer

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

본 발명은 도 3(a)와 같이, 콘택 홀 형성 후 베리어 금속막을 증착하기 전에 콘택 기저부의 자연산화막을 제거하기 위하여 CF4/O2또는 BOE(Buffered Oxide Etchant, NF4+HF+H2O)를 이용한 세정(cleaning)을 실시한다. 그 후 실리콘과의 안정된 콘택을 형성하기 위하여 실리콘의 조성비가 2 이하인 바람직하게는 0.5 내지 1.5인 TiSix타겟(target)을 사용하여 스퍼터링(sputtering) 방식에 의해 TiSix층(21)을 300Å∼600Å 증착한다. 이때 반응 챔버의 온도는 실온에서 300℃ 사이에서 진행하고 반응 챔버의 압력은 2mTorr∼5mTorr로 한다.In the present invention, as shown in FIG. 3 (a), CF 4 / O 2 or BOE (Buffered Oxide Etchant, NF 4 + HF + H 2 O) is used to remove the native oxide layer on the contact base after depositing the barrier metal layer after forming the contact hole. Clean using). Thereafter, the TiSi x layer 21 is 300 Å to 600 Å by sputtering using a TiSi x target having a composition ratio of 2 or less, preferably 0.5 to 1.5, in order to form a stable contact with the silicon. Deposit. At this time, the temperature of the reaction chamber proceeds from room temperature to 300 ° C., and the pressure of the reaction chamber is set to 2 mTorr to 5 mTorr.

다음은 도 3(b)와 같이, 타이타늄 타겟이 장착된 챔버에서 리액티브-스퍼터링(reactive sputtering) 방식으로 TiN층(22)을 500Å∼1000Å 정도 증착시킨다.Next, as shown in FIG. 3 (b), the TiN layer 22 is deposited by 500-1000 mW by reactive sputtering in a chamber equipped with a titanium target.

이렇게 증착된 TiN층(22) 대신 N2분위기에서 TiSix타겟을 사용하여 리액티브-스퍼터링 방식으로 타이타늄실리콘나이트라이드(TiSixNy)층(22)을 500Å∼1000Å 정도 증착시킬 수도 있다. 이때 TiN층(22) 또는 TiSixNy층(22)을 증착함에 있어서 후속 열처리시에 발생될 수 있는 결함(crack) 등을 방지하기 위하여 막(film)의 인장(tensile), 또는 압축(compressive) 응력을 109dyne/㎠ 이하가 되게 한다. 이러한 조건을 만족시키기 위하여 반응 챔버의 압력은 5mTorr∼20mTorr 사이로 유지하고 반응 챔버의 온도는 100℃∼400℃가 되게 한다.Instead of the TiN layer 22 deposited as described above, a titanium silicon nitride (TiSi x N y ) layer 22 may be deposited by using a TiSi x target in an N 2 atmosphere in a reactive-sputtering manner. At this time, in the deposition of the TiN layer 22 or the TiSi x N y layer 22, the tensile or compressive of the film to prevent cracks or the like that may occur during subsequent heat treatment. ) The stress should be 10 9 dyne / cm 2 or less. In order to satisfy this condition, the pressure of the reaction chamber is maintained between 5 mTorr and 20 mTorr, and the temperature of the reaction chamber is 100 ° C to 400 ° C.

다음으로 퍼니스(furnace)나 급속 열처리 장치를 이용하여 500℃∼700℃ 사이에서 열처리하여 안정된 TiSi2층(23)을 도 3(c)와 같이 형성되게 한다. 이때 퍼니스를 사용하여 열처리(furnace annealing)하는 경우 시간은 5분에서 30분, 급속 열처리 장치를 이용하는 경우 시간은 5초에서 2분 사이로 진행한다. 이러한 후속 열처리 과정에서 TiSix층(21)과 접합부(24)의 Si의 반응에 의하여 TiSi2층(23)이 형성된다.Next, a heat treatment is performed between 500 ° C. and 700 ° C. using a furnace or a rapid heat treatment device to form a stable TiSi 2 layer 23 as shown in FIG. 3 (c). In this case, the time of the heat treatment using the furnace (furnace annealing) is 5 minutes to 30 minutes, and when using a rapid heat treatment device, the time proceeds from 5 seconds to 2 minutes. In this subsequent heat treatment, the TiSi 2 layer 23 is formed by the reaction of the Si of the TiSi x layer 21 and the junction 24.

이 경우 기존의 제조 방식에서 나타나는 타이타늄과 실리콘의 반응과는 달리, TiSix층(21)이 증착된 순간에 이미 타이타늄 내에 실리콘이 존재하므로 후속 열처리시 접합 영역(24)의 과도한 실리콘 소모를 억제시킬 수 있다.In this case, unlike the reaction of titanium and silicon in the conventional manufacturing method, since silicon is already present in the titanium at the time when the TiSi x layer 21 is deposited, excessive silicon consumption of the junction region 24 may be suppressed during subsequent heat treatment. Can be.

따라서 기존의 타이타늄과 실리콘의 반응에 의해 생성되는 TiSi2층(13)의 두께보다도 적은, 20Å∼300Å 정도의 두께를 가진 TiSi2층(23)을 형성시켜 매우 얕은 접합에서도 접합의 파괴없이 안정된 콘택 저항을 얻을 수 있을 뿐만 아니라 과도한 누설 전류를 방지할 수 있다.Therefore, a TiSi 2 layer 23 having a thickness of about 20 kPa to 300 kPa, which is smaller than the thickness of the TiSi 2 layer 13 produced by the reaction of titanium and silicon, is formed, thus making stable contact without breaking the junction even in a very shallow junction. Not only can resistance be obtained, but excessive leakage current can be prevented.

상술한 바와 같이 본 발명에 의하면, 반도체 소자 제작공정 중 베리어 금속막 증착시 기존의 Ti 타겟 대신에 Si이 함유된 TiSix타겟을 사용함으로써 후속 열처리시 접합부의 과도한 Si 소모없이 TiSi2를 형성하여 안정된 콘택 저항을 얻을 수 있을 뿐만 아니라 과도한 누설 전류를 방지할 수 있다. 따라서 매우 얕은 접합이 가능하여 모든 고집적 반도체 소자에 적용할 수 있다.As described above, according to the present invention, the TiSi x target containing Si is used instead of the existing Ti target during the deposition of the barrier metal film during the semiconductor device fabrication process, thereby forming TiSi 2 without excessive Si consumption at the joint during subsequent heat treatment, thereby making it stable. Not only can contact resistance be obtained, but excessive leakage current can be prevented. Thus, very shallow junctions can be applied to all highly integrated semiconductor devices.

Claims (7)

콘택 홀이 형성된 실리콘 기판이 제공되는 단계와,Providing a silicon substrate having contact holes formed thereon; 상기 콘택 홀을 포함하는 전체 구조 상부에 실리콘이 함유된 타이타늄실리사이드 타겟을 이용하여 타이타늄실리사이드층을 증착하는 단계와,Depositing a titanium silicide layer using a titanium silicide target containing silicon on the entire structure including the contact hole; 열처리 공정을 실시하여 접합 영역의 실리콘 소모없이 안정된 타이타늄실리사이드층을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device, comprising the step of forming a stable titanium silicide layer by performing a heat treatment process without consuming silicon in the junction region. 제 1 항에 있어서, 상기 증착된 타이타늄실리사이드층은 실리콘 원자의 조성비가 0.5 내지 2.0인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the deposited titanium silicide layer has a composition ratio of silicon atoms of about 0.5 to about 2.0. 제 1 항에 있어서, 상기 타이타늄실리사이드층은 실온 내지 300℃의 온도에서 증착되는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the titanium silicide layer is deposited at a temperature of room temperature to 300 ° C. 7. 제 1 항에 있어서, 상기 타이타늄실리사이드층은 2mTorr 내지 5mTorr의 압력 조건의 반응챔버 내에서 증착되는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the titanium silicide layer is deposited in a reaction chamber under a pressure condition of 2 mTorr to 5 mTorr. 제 1 항에 있어서, 상기 안정된 타이타늄실리사이드층의 두께는 20Å 내지 300Å인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the stabilized titanium silicide layer has a thickness of 20 kPa to 300 kPa. 제 1 항에 있어서, 상기 열처리 공정은 500℃ 내지 700℃ 온도의 퍼니스에서 5분에서 30분 동안 실시되는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the heat treatment is performed at a furnace at a temperature of 500 ° C. to 700 ° C. for 5 minutes to 30 minutes. 제 1 항에 있어서, 상기 열처리 공정은 500℃ 내지 700℃ 온도의 급속 열처리 장치에서 5초 내지 2분동안 실시되는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the heat treatment is performed in a rapid heat treatment apparatus at a temperature of 500 ° C. to 700 ° C. for 5 seconds to 2 minutes.
KR1019970022003A 1997-05-30 1997-05-30 Method of manufacturing a semiconductor device KR100274340B1 (en)

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