JP3044728B2 - Manufacturing method of embedded plug - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an embedded plug that fills an opening with a polycrystalline silicon layer at high speed with high controllability and reproducibility.

[Summary of the Invention]

According to the method of the present invention, in the method of manufacturing a buried plug made of a polycrystalline silicon layer, the etching back of the polycrystalline silicon is divided into two stages, and the radical reaction mainly progresses until the base is exposed or immediately before the exposure. 1
Etching back (overetching) for flattening the surface of the substrate is a second etching step in which a deposition reaction and an etching reaction proceed competitively or an ion assisted reaction proceeds. Accordingly, the opening can be buried flat by a buried plug made of a polycrystalline silicon layer without being affected by a so-called reverse loading effect.

[Conventional technology]

2. Description of the Related Art Conventionally, in the field of semiconductor devices such as VLSI and ULSI, not only miniaturization in two dimensions but also integration in three dimensions has been attempted in order to achieve higher integration and higher performance. In order to achieve such integration, a multi-layer ship arrangement is being performed. In order to realize a multi-layer ship arrangement, a hole filling technique of filling a contact hole or a via hole having a high aspect ratio with a conductive material to flatten the surface of a substrate is used. As a hole filling technique, a method of embedding with a metal, such as a selective tungsten method or a blanket tungsten method, or a method of embedding polycrystalline silicon by etch-back after deposition has been proposed.

The method of embedding with a metal such as tungsten has advantages such as a low resistance of the plug part itself as the embedding part and the fact that it can be formed irrespective of the conductivity type of the underlying diffusion layer, but the selective tungsten method ensures the selectivity. And the blanket tungsten method has a problem that adhesion between tungsten and SiO ₂ is low.

On the other hand, the method of embedding with a plug made of polycrystalline silicon has the problems that the resistance of the plug itself is relatively high, and that an impurity corresponding to the conductivity type of the lower diffusion layer must be introduced, and the process becomes longer. However, since an existing process can be applied, highly reliable processing can be performed.
Moreover, Semiconductor World December 1989 issue, No.
As described on pages 103 to 105, it is possible to form a low-resistance plug of polycrystalline silicon by optimally selecting an ion species and an implantation energy when performing ion implantation when introducing impurities. .

Conventionally, for example, a contact hole formed in an insulating film,
The following method is employed to bury polycrystalline silicon flatly in an opening such as a via hole.

That is, as shown in FIG. 2A, an insulating film 12 made of SiO ₂ or the like and having an opening 13 is previously formed on a semiconductor substrate 11.
Is formed, and a polycrystalline silicon layer 14 is formed so as to cover at least the opening 13 to substantially flatten the substrate surface.

Next, the polycrystalline silicon layer 14 is etched back. At this time, if the etch back is terminated when the surface of the insulating film 12 is exposed, a state where the opening 13 is buried flat by the polycrystalline silicon layer 14 is achieved.

[Problems to be solved by the invention]

However, when actually performing the etch back of the polycrystalline silicon layer, the controllability of the remaining film thickness is low, and it is difficult to achieve a state in which the opening 13 is buried flat by the polycrystalline silicon layer 14. You can see that. For example, when a fluorine-based gas such as chlorofluorocarbon is used as an etching gas, the uniformity of the process, the etching rate, the reproducibility, etc. are extremely good, but the polycrystalline silicon layer 14 on the insulating film 12 is removed at the same time. Excess fluorine radicals are concentrated in the openings 13. Therefore, as shown in FIG. 2 (B), the polycrystalline silicon layer 14 in the opening 13, which should originally become a plug, is largely eroded by a slight overetching,
In some cases, it is often experienced that the semiconductor substrate 11 is also damaged. This is also called an inverse loading effect because the etching rate locally increases, which is the opposite effect of the so-called loading effect.

In order to prevent such a reverse loading effect, it is conceivable that the etching gas is a chlorine-based gas. It is difficult for the chlorine-based gas to spontaneously etch the polycrystalline silicon layer, and can participate in the etching reaction more effectively by ion bombardment. Therefore, the etching rate is low, and the progress of the etching is fluctuated due to the surface state of the polycrystalline silicon layer caused by ion bombardment, or the presence of moisture or deposits in the etching chamber,
Reproducibility tends to decrease.

Accordingly, it is an object of the present invention to solve these problems and to provide a method capable of manufacturing a buried plug made of a polycrystalline silicon layer at high speed with high controllability and reproducibility.

[Means for solving the problem]

The present inventors have conducted intensive studies in order to achieve the above object, and as a result, the etching speed is high and uniformity and reproducibility immediately before the base is exposed or until the part of the base starts to be exposed. If the process proceeds with a process having excellent controllability, and the subsequent over-etching for flattening the substrate surface proceeds with a process having a controllability of the remaining film thickness, the overall process is excellent in uniformity, reproducibility and controllability at high speed. It has been found that the polycrystalline silicon layer can be etched.

In this case, it is necessary to sharply determine the etching switching time based on the two types of processes. However, the present inventor monitored the emission spectrum of SiF using a fluorine-based gas as the etching gas in the first half of the process. I also found that this would be possible. Further, they have also found that if the reaction for removing the deposits in the etching chamber proceeds simultaneously in the first half of the process, a clean process always proceeds even when performing continuous processing on a plurality of wafers.

The present invention has been proposed based on the above findings.

That is, the present invention provides a method of manufacturing an embedded plug made of a polycrystalline silicon layer, wherein a step of forming an opening in a base and exposing a substrate surface, and covering the base having the opening and contacting the base surface are performed. Forming the polycrystalline silicon layer and etching back the polycrystalline silicon layer until a part of the surface of the underlayer is exposed or immediately before the underlying layer is exposed to external energy by using radicals as etching species. A first etching step performed by spontaneously reacting with silicon, and a state in which the opening is buried flat by the polycrystalline silicon layer under the condition that the etching proceeds at a lower speed than the first etching step. It has a second etching step of performing etch-back while preventing the reverse loading effect until it is.

Here, in the second etching step, etching proceeds at a low speed by using an etching gas and a deposition gas to cause an etching reaction and a deposition reaction to coexist.

More specifically, the second etching step is performed at a low speed by being performed in a system in which etching proceeds spontaneously when external energy is applied, that is, a system in which etching does not easily progress unless external energy is applied. Etching proceeds. Here, in the second etching step, a chlorine-based gas is used.

In addition, the end point of the first etching step is determined by monitoring the emission spectrum of SiF using a fluorine-based etching gas in the first etching step.

Further, cleaning of the etching chamber is performed by the first etching step.

[Action]

The method of the present invention mainly employs conditions in which a radical reaction proceeds in the first etching step of performing etch-back until the base is exposed or immediately before the base is exposed. In this step, radicals such as fluorine radicals having a size that can easily penetrate into the crystal lattice of polycrystalline silicon or into the crystal grain boundaries become the main etching species, so that energy cannot be given from the outside. In addition, it spontaneously reacts with silicon to etch it.

The method of the present invention further provides a second etching step of performing etch-back (over-etching) until the opening provided in the base is flatly buried with polycrystalline silicon. Is adopted. This condition is a condition under which the deposition reaction and the etching reaction can compete with each other, and in the second invention, an ion-assisted reaction proceeds. That is, the net etching rate is reduced by allowing the etching reaction to coexist with the deposition reaction, and the etching rate is reduced by a system in which the etching reaction does not proceed spontaneously unless external energy is applied, thereby reducing the remaining film thickness. Controllability is improved.

By the way, when the first etching is started by using a fluorine-based etching gas in the first etching step and selecting a sufficiently large selection ratio between the polycrystalline silicon layer and the base, the etching of the polycrystalline silicon layer proceeds. During this time, volatile SiF is generated at a constant rate. Therefore,
When the emission spectrum of SiF at a wavelength of 440 nm is monitored, a constant intensity peak is continuously observed. When a part of the base begins to be exposed, the intensity of the peak starts to decrease rapidly. When the base is almost completely exposed, the peak intensity remains at a low level because the area to be etched is reduced. In the method of the present invention, the point in time when the peak intensity starts decreasing first is defined as the end point. This point can be determined by a suitable electrical signal processing method such as a second derivative.

Further, according to the method of the present invention, if the etching gas system in each etching step is appropriately selected, it is possible to clean the inside of the etching chamber in the first etching step. This cleaning effect is extremely significant when performing continuous processing on a plurality of wafers. That is, in the second etching step, a carbon-based or silicon-based polymer may remain in the etching chamber depending on the type of etching gas used, but the possibility of a deposition reaction in the first etching step is reduced. Especially when using the reduced etching gas system,
Since the radical species generated in this step efficiently convert the residual sediment into a volatile substance and remove it, a clean process can always proceed.

〔Example〕

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 This embodiment is an example in which polycrystalline silicon is buried flat in an opening formed in an insulating film. This step will be described with reference to FIGS. 1 (A) to 1 (C).

First, as shown in FIG. 1A, an insulating film 2 made of, for example, silicon oxide is formed on a semiconductor substrate 1 made of silicon or the like, and an opening 3 is formed by patterning. Next, a polycrystalline silicon layer 4 is formed over the entire surface by a vacuum thin film forming technique such as a CVD method having excellent covering properties, and the surface of the base is substantially flattened.

Next, the polycrystalline silicon layer 4 was etched as a first etching. The first etching is performed by using a high frequency bias application type ECR (Electron Cyclotron Resonance) etching apparatus, and the condition is, for example, SF ₆ amount 30SCC
M, C ₂ Cl ₃ F ₃ (CFC113) flow rate 30SCCM, gas pressure 10mTorr,
The microwave power was 850 W and the high frequency bias was 30 W. In this step, a reaction using fluorine radicals as a main etching species progressed, and the etching rate was as fast as 6000 ° / min, and the uniformity was as good as ± 2%. During this etching, the emission spectrum intensity of SiF at a wavelength of 440 nm was continuously monitored, and the point at which the intensity began to decrease was defined as the end point of the first etching. At this time, the substrate had a state in which the insulating film 2 was partially exposed on the surface of the substrate as shown in FIG. 1 (B).

Next, second etching for planarizing the surface of the base was performed. This condition is, for example, SF ₆ amount 7 SCCM, C ₂ Cl ₃ F ₃
(CFC 113) The flow rate was 53 SCCM, the gas pressure was 10 mTorr, the microwave power was 850 W, and the high frequency bias was 100 W. The etching gas used here had the same components as those used in the first etching, but the flow rate ratio was changed to increase the amount of C ₂ Cl ₃ F ₃ capable of depositing the carbon-based polymer. Things. As a result, a condition in which the etching reaction and the deposition reaction compete with each other is achieved, and etching can be performed with a uniformity of about ± 5% at a relatively low etching rate of 2000 ° / min. As shown in the figure, the surface of the substrate was flattened very well. In this case, since the etching rate was reduced and the controllability of the remaining film thickness was improved, the plug portion 4a inside the opening 3 was not eroded. Although the second etching seems to have a lower etching rate and a lower uniformity than the first etching, the problem substantially arises because over-etching is performed after most of the etching has already been completed. Instead, sufficient speed and uniformity are achieved for the entire process.

By the way, the etching gas used in each etching step can be selected from a wide range of substances as long as the gas can achieve desired conditions. However, as described above, if a mixed etching gas consisting of the same component is used in both etching steps and the reaction mode in each step can be switched only by changing the flow rate ratio, an extremely practical dry etching method is provided. Is done. In this case, as the gas as the gas as a source of fluorine radicals in addition to NF _3, ClF ₂ etc. of SF ₆ described above, also capable of depositing carbonaceous polymer, C ₂ Cl ₃ F ₃ (CFC 113) Others
C ₂ Cl ₂ , F ₄ (CFC 114), CHF ₃ , CH ₂ F ₂ , CH ₃ F, C ₂ F ₆ , C
_{3 F 8, C 4 F 10} , CCl 4, CCl 3 F, CCl 2 F 2 or the like can be used.

Here, when a deposition gas as in this embodiment is used,
After the completion of the second etching, deposits such as carbon-based polymer remain in the etching chamber, which cause contamination, and the reproducibility is reduced especially when continuous processing is performed in one etching chamber. Seems to happen. Most of the remaining deposits are changed to volatile substances and removed by fluorine radicals in the next first etching step, so that a clean process can always proceed.

Embodiment 2 In this embodiment, the same embedding as in Embodiment 1 described above was performed by applying the second and third aspects of the present invention. That is, after performing the first etching to bring the substrate into the state shown in FIG. 1 (B) in the same manner as in Example 1, the conditions for allowing the ion-assisted reaction to proceed as the second etching are set, and the over-etching is performed. Was. This condition is, for example, BCl ₃ flow rate
30 SCCM, Cl ₂ flow rate was 20 SCCM, gas pressure was 10 mTorr, microwave power was 850 W, and high frequency bias was 100 W. By this etching, as shown in FIG. 1 (C), the opening 3 could be buried flat by the plug portion 4a of the polycrystalline silicon layer.

Example 3 In this example, first, the first etching was performed using SF ₆ gas alone, and the substrate was brought into a state shown in FIG. 1 (B). Conditions at this time are, for example, SF ₆ flow rate 60 SCCM, gas pressure 10 mTorr,
The microwave power was 850 W and the high frequency bias was 100 W.

Next, as the second etching, etching is performed under the same conditions as in the above-described second embodiment, and the opening 3 is buried flat with the plug portion 4a of the polycrystalline silicon layer as shown in FIG. Was completed.

Here, in the first etching step, without combination of C ₂ Cl ₃ F ₃ as in Example 1 or Example 2, S
Was used the F ₆ alone is to increase the cleaning effect of the etching chamber by the first etching step. That is, in the above-described second etching step, BC
When l ₃ / Cl ₂ mixed gas is used, SiCl _X which is an etching reaction product reacts with oxygen released from a quartz member in the etching chamber, and SiO ₂ by-produced also becomes a residual deposit. there is a possibility. Therefore, it is more effective to perform the first etching under the condition that the possibility of deposition is minimized. As a result, even in continuous processing, an extremely clean process proceeded with good reproducibility.

In each of the above embodiments, the composition or flow rate ratio of the etching gas system used is switched between the first etching step and the second etching step. It is also possible to switch between the process of (1) and the process of the ion assisted reaction. In general, if the gas pressure is set high and the high-frequency bias is set low, the process mainly involving the radical reaction can proceed. On the contrary, if the gas pressure is set low and the high-frequency bias can be set high, the process mainly involving the ion-assisted reaction can be advanced. .

Although each of the above-described embodiments is based on the assumption that the contact holes and via holes are filled with polycrystalline silicon, the present invention is not limited to these embodiments. For example, the present invention is applied to a single-crystal silicon substrate. The same can be applied to a case where a trench is filled with polycrystalline silicon through a thin insulating layer to form a capacitor.

〔The invention's effect〕

As is apparent from the above description, by using the method of the present invention, the etch back of the polycrystalline silicon layer constituting the buried plug formed by covering the base having the opening is divided into two stages, so-called, The opening can be quickly and flatly filled with the polycrystalline silicon layer without being affected by the reverse loading effect and without damaging the substrate. In addition, since the radical reaction mainly proceeds in the first etch-back, a clean and highly reproducible process always proceeds even in the continuous processing.

Therefore, by applying the dry etching method of the present invention to the manufacture of a semiconductor device, a semiconductor device having high integration and high reliability can be manufactured with high productivity and yield.

[Brief description of the drawings]

1 (A) to 1 (C) are schematic cross-sectional views illustrating an example of a dry etching method of the present invention in the order of steps, and FIG. 1 (A) is an insulating film, an opening, and a polycrystal. FIG. 1B shows a step of forming a silicon layer, FIG. 1B shows a step of etching back a polycrystalline silicon layer by first etching, and FIG. 1C shows a step of forming a plug portion by second etching. 2 (A) and 2 (B) are schematic cross-sectional views for explaining a problem in a conventional general polycrystalline silicon layer etch-back process, and FIG. 2 (A) is an insulating film. FIG. 2B shows an erosion state in the opening at the end of the etch-back. 1 ... semiconductor substrate, 2 ... insulating film, 3 ... opening, 4 ...
... Polycrystalline silicon layer, 4a ... Plug part.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3065 H01L 21/28 301 H01L 21/3205

Claims (5)

(57) [Claims] 1. A method of manufacturing a buried plug made of a polycrystalline silicon layer, comprising the steps of: forming an opening in a base and exposing a surface of a base; and covering the base having the opening and contacting the base surface. Forming a polycrystalline silicon layer on the substrate, and spontaneously etching back the polycrystalline silicon layer until a part of the surface of the underlayer is exposed or immediately before the polycrystalline silicon layer is exposed to energy from outside using radicals as etching species. A first etching step performed by reacting with the silicon selectively, and under the condition that the etching proceeds at a lower speed than the first etching step, until the opening is in a state of being buried flat by the polycrystalline silicon layer. A second etching step of performing etch back while preventing a reverse loading effect, wherein the second etching step The method for manufacturing a buried plug, characterized in that the etching at a low speed progresses in the coexistence of the a deposition reaction and an etching reaction using an etching gas and deposition gas. 2. The burying method according to claim 1, wherein the second etching step is performed in a system in which the etching proceeds spontaneously when external energy is applied, whereby the etching proceeds at a low speed. Plug manufacturing method. 3. The method according to claim 2, wherein said second etching step uses a chlorine-based gas. 4. The method according to claim 1, wherein an end point of the first etching step is determined by using a fluorine-based etching gas in the first etching step and monitoring an emission spectrum of SiF. Embedded plug manufacturing method. 5. The method according to claim 1, wherein the cleaning of the etching chamber is performed by the first etching step.
A method of manufacturing the embedded plug described in the above.