KR100274153B1 - Method of formation for fine t-shaped gate with holder - Google Patents

Method of formation for fine t-shaped gate with holder Download PDF

Info

Publication number
KR100274153B1
KR100274153B1 KR1019970071617A KR19970071617A KR100274153B1 KR 100274153 B1 KR100274153 B1 KR 100274153B1 KR 1019970071617 A KR1019970071617 A KR 1019970071617A KR 19970071617 A KR19970071617 A KR 19970071617A KR 100274153 B1 KR100274153 B1 KR 100274153B1
Authority
KR
South Korea
Prior art keywords
gate
resist
insulating film
type gate
etched
Prior art date
Application number
KR1019970071617A
Other languages
Korean (ko)
Other versions
KR19990052168A (en
Inventor
박병선
윤형섭
이진희
박철순
편광의
Original Assignee
정선종
한국전자통신연구원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정선종, 한국전자통신연구원 filed Critical 정선종
Priority to KR1019970071617A priority Critical patent/KR100274153B1/en
Publication of KR19990052168A publication Critical patent/KR19990052168A/en
Application granted granted Critical
Publication of KR100274153B1 publication Critical patent/KR100274153B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Abstract

PURPOSE: A manufacturing method of microscopic T-type gate with supporter is provided to make a T-type gate metal easily for improving a transistor characteristic. CONSTITUTION: The first metal layer(3) is vaporized and patterned on a substrate(1) with a channel layer. An ohmic layer(2) is evaporated and patterned as a T-type for building a T-type gate. After being doped and etched a PMMA(Poly-Methyl MethAcrylate) resist and an MMA-MMA(Methyl MethAcrylate-Methyl MethAcrylate) resist respectively, the leg and the head of a T-type gate is formed, and a T-type gate pattern is built. The part of exposed substrate(1) is recessed, and an insulating layer(6) is attached on the sidewall of the resist layers and flattened layer with the same thickness of the resist layers using plasma CVD(Chemical Vapor Deposition) method. Using dry etching method, the insulating layer(6) is etched selectively for building a supporter. After recessing the exposed substrate(1), a gate metal is doped and the resist layers are removed by soaking in acetone or in solvent. Then, the T-type gate metal(7) is produced.

Description

지지대가 있는 미세한 티-형 게이트 제작방법How to make fine tee gates with supports

본 발명은 반도체를 이용한 소자의 제조 방법에 관한 것으로, 특히 트랜지스터의 특성을 개선할 수 있도록 미세한 T-형상의 게이트 금속을 쉽게 형성하기 위한 지지대가 있는 미세한 티(T)-형 게이트 제작 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a device using a semiconductor, and more particularly, to a method of manufacturing a fine T-type gate having a support for easily forming a fine T-shaped gate metal so as to improve the characteristics of a transistor. will be.

고성능 트랜지스터의 제작을 위한 게이트 길이의 감소는 구조적으로 트랜지스터의 차단 주파수를 높게 할 뿐 아니라 관련된 여러 가지 특성들을 개선하는 효과를 가져온다.Reducing the gate length for the fabrication of high performance transistors not only increases the cutoff frequency of the structure, but also improves various related characteristics.

그러나 게이트 길이의 감소는 금속의 단면적을 작게 하기 때문에 잡음특성등을 저하시킴에 따라 게이트를 T-형으로 만들어 저항의 감소를 꾀하고 있는데, 이러한 T-형상의 게이트는 다양한 방법들에 의해서 제작이 가능하여 지금까지 발명, 또는 보고된 예가 매우 많은데, 이들 모두 주로 E-beam 리소그라피를 사용하고 있다.However, as the gate length is reduced, the cross-sectional area of the metal is reduced, which reduces the noise characteristics, thereby reducing the resistance by making the gate T-shaped. Such T-shaped gates are manufactured by various methods. There are many examples of inventions or reports reported so far, all of which mainly use E-beam lithography.

종래의 방법에 의한 상기 T-형 게이트는, E-beam 리소그라피 방법으로 역삼각형의 T-형 레지스트 형상을 만들어 여기에 금속을 증착하고 리프트-오프하여 만들거나 또는 임시 게이트를 만들어 미세한 게이트 형상의 홈을 만들고 여기에 다시 넓은 폭을 갖는 상층의 레지스트 패턴을 형성하여 금속을 증착, 리프트-오프하여 만들 수 있으나, 이들 방법은 모두 T-형상의 게이트를 만드는데 효과적이지만 미세한 게이트를 만드는 데는 문제점이 있다.The T-type gate according to the conventional method may be formed by forming an inverted triangle T-type resist shape by using an E-beam lithography method, depositing and lifting metal thereon, or making a temporary gate to form a fine gate shape groove. Although the upper layer resist pattern is formed on the back layer and the metal layer is deposited and lifted off, these methods are effective for making T-shaped gates, but there are problems in making fine gates.

또한 전자-빔 리소그라피 공정을 사용하여 미세한 게이트를 만드는 경우에는, 미세한 게이트 패턴을 형성하기 위하여 가속전압을 높여 사용하고 있는데, 가속전압을 높여 사용하면 미세한 게이트 패턴은 가능하나 게이트 메탈 증착 시 게이트 길이 대 게이트 다리 부위의 높이의 비가 상대적으로 높아지므로, 금속증착 시 게이트 다리와 머리가 끊어지는 문제점이 있다.In addition, in the case of making a fine gate by using an electron-beam lithography process, an acceleration voltage is increased to form a fine gate pattern. When the acceleration voltage is increased, a fine gate pattern is possible, but the gate length is increased when the gate metal is deposited. Since the ratio of the height of the gate bridge portion is relatively high, there is a problem that the gate bridge and the head is broken when metal deposition.

이에 따라 최근에는 이를 극복하기 위하여 게이트 다리를 형성한 후 높은 온도에서 베이킹을 수행하여 패턴을 삼각형 형태로 둥글게 만든 후, 다시 한번 리소공정을 수행하여 게이트 머리를 만드는 방법을 사용하고 있다.Accordingly, in order to overcome this, recently, a gate bridge is formed and a pattern is rounded to form a triangle by baking at a high temperature, and then a lithography process is performed again to make a gate head.

상기 문제점을 해결하기 위해 본 발명은, 전자빔을 이용하여 레지스트 T-형 우물 패턴을 형성한 후 저온의 PECVD 절연막을 증착하여 미세한 게이트를 형성하고, C2F6(80)+CHF3(20) 혼합가스 건식식각을 이용하여 측벽의 패턴은 식각시키지 않고, 바닥의 질화막을 제거하여 T-형 게이트를 형성하는 방법을 제공하는 것을 목적으로 한다.In order to solve the above problems, the present invention, after forming a resist T-type well pattern using an electron beam, a low-temperature PECVD insulating film is deposited to form a fine gate, C 2 F 6 (80) + CHF 3 (20) It is an object of the present invention to provide a method of forming a T-type gate by removing a bottom nitride film without etching the pattern of the sidewall by using the mixed gas dry etching.

이러한 과정에서 게이트의 다리 부위와 머리부위가 만나는 부분을 둥글게 패턴을 형성하여 게이트 다리와 머리의 끊어짐을 방지하고, 실리콘 질화막이 게이트 다리를 양쪽에서 지지하여 미세한 게이트 다리와 면적이 큰 T-형 게이트 메탈을 들뜸없이 얻을 수 있으며, 또한 게이트 머리 아래의 실리콘 질화막의 절연막을 제거하여 기생성분이 작아지도록 함으로써 고품위 트랜지스터의 제작이 가능하도록 하는 방법이다.In this process, the gate leg and the head part meet to form a round pattern to prevent the gate leg and the head from being broken, and the silicon nitride film supports the gate leg from both sides so that the fine gate bridge and the large T-type gate are large. The metal can be obtained without lifting, and the parasitic component is reduced by removing the insulating film of the silicon nitride film under the gate head, thereby making it possible to manufacture high-quality transistors.

상기 목적을 달성하기 위해 본 발명은, 채널층이 형성된 기판(1)에 1차 금속막(3)과 오믹층(2)을 증착하여 패터닝하고, 게이트 다리를 형성하는 PMMA 레지스트(4)와 게이트 머리를 형성하기 위한 MMA-MMA 레지스트(5)를 도포하 는 제 1단계, 상기 MMA-MMA 레지스트(5)와 PMMA 레지스트(4)를 각각 식각하여 T-형 게이트의 머리 모양 및 T-형 게이트의 다리 모양을 형성하여 T-형 게이트 패턴을 형성한 후 노출된 기판의 일부를 1차 리세스하는 제 2 단계, 상기 레지스트(4, 5)막의 측벽과 평탄면 위에 플라즈마 화학증착 방법을 이용하여 절연막(6)을 같은 두께로 증착하는 제 3 단계, 상기 게이트 다리와 머리부위의 접촉 부분을 지지하는 지지부분 형성을 위해 건식식각을 이용하여 측벽의 패턴은 식각되지 않고, 측벽의 상단 부분은 경사지게 하며, 수평면은 제거되도록 상기 절연막(6)을 식각하고, 노출된 부분의 기판을 2차 리세스 하는 제 4 단계 및 상기 식각한 절연막 위에 게이트 금속을 증착한 후 상기 레지스트(4, 5)막을 아세톤 또는 용매에 담가 제거하여 T-형상을 가진 게이트 금속(7)을 형성하는 제 5 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention, the PMMA resist 4 and the gate to form a gate bridge by depositing and patterning the primary metal film 3 and the ohmic layer 2 on the substrate 1 on which the channel layer is formed In the first step of applying the MMA-MMA resist (5) to form the head, the MMA-MMA resist (5) and PMMA resist (4) is etched, respectively, the head shape of the T-type gate and the T-type gate A second step of first recessing a part of the exposed substrate after forming a T-type gate pattern by forming a bridge shape of the substrate, using plasma chemical vapor deposition on the sidewalls and flat surfaces of the resist films 4 and 5 In the third step of depositing the insulating film 6 to the same thickness, the pattern of the side wall is not etched using dry etching, and the upper part of the side wall is inclined so as to form a support portion for supporting the contact portion between the gate leg and the head. The horizontal plane to be removed Etching the insulating film 6, second recessing the exposed part of the substrate and depositing a gate metal on the etched insulating film, and then immersing and removing the resist (4, 5) film in acetone or a solvent to remove T. A fifth step of forming the gate metal 7 having a shape.

도 1a 내지 도 1j는 본 발명에 의한 지지대가 있는 미세한 T-형 게이트 제작 방법을 설명하기 위한 공정도.1A to 1J are process drawings for explaining a method for fabricating a fine T-type gate having a support according to the present invention.

도 1a는 게이트를 형성하기 위한 기판 위에 오믹 및1차 금속이 증착된 형상을 보인 공정도.Figure 1a is a process diagram showing the ohmic and primary metal deposited on the substrate for forming the gate.

도 1b는 게이트 다리를 형성하기 위한 PMMA레지스트 도포 공정도.1B is a process diagram of a PMMA resist coating to form a gate bridge.

도 1c는 게이트 머리를 형성하기위한 MMA-MAA(co-polymer)레지스트 도포 공정도.1C is an MMA-MAA (co-polymer) resist application process diagram for forming a gate head.

도 1d는 게이트 다리와 머리를 형성하기 위한 전자빔 노광 공정도.1D is an electron beam exposure process diagram for forming a gate bridge and a head.

도 1e는 노광 후 레지스트 현상 공정도.1E is a post-exposure resist development process diagram.

도 1f는 1차 기판을 리세스 식각한 모양을 보인 공정도.Figure 1f is a process diagram showing the shape of the recess etching the primary substrate.

도 1g는 저온 PECVD을 이용하여 실리콘 질화막 증착 공정도.1G is a silicon nitride film deposition process using low temperature PECVD.

도 1h는 실리콘 질화막 건식식각 및2차 기판 리세스 공정도.1H is a silicon nitride film dry etch and secondary substrate recess process diagram.

도 1i는 게이트 금속 증착 공정도.1I is a gate metal deposition process diagram.

도 1j는 레지스트막을 제거하여 금속을 리프트-오프한 모양을 보인 공정도.1J is a process diagram showing the shape of the metal lifted off by removing the resist film.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

1 : 기판 2 : 오믹층1 substrate 2 ohmic layer

3 : 1차 금속막 4 : PMMA 레지스트막3: primary metal film 4: PMMA resist film

5 : MMA-MAA(co-polymer)레지스트막5: MMA-MAA (co-polymer) resist film

6 : 실리콘 질화막 7 : 게이트 금속6: silicon nitride film 7: gate metal

이하, 본 발명의 실시예를 첨부된 도면을 참조해서 상세히 설명하면 다음과 같다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1j는 본 발명에 의한 지지대가 있는 미세한 T-형 게이트 제작 방법을 설명하기 위한 공정도이다.1A to 1J are process diagrams for explaining a method for fabricating a fine T-type gate having a support according to the present invention.

먼저 도 1a와 같이, 채널층이 형성된 기판(1)에 1차 금속막(3)을 증착하여 패터닝하고 그 위에 오믹층(2)을 증착하여 T-형 게이트를 형성하기 위한 형으로 패터닝하며, 이어서 준비된 시료를 잘 세척한 다음 도 1b와 같이, HMDS로 전처리한 후 게이트 다리를 형성하는 PMMA 레지스트(4)를 0.25μm를 도포한 다음 도 1c와 같이 게이트 머리를 형성하기 위한 MMA-MAA 레지스트(5)를 1.05㎛ 도포한 다음 베이킹 공정을 수행하고, 도스 분리형 패턴을 이용하여 도 1d와 같이, 노광을 수행한 후, MIBK:IPA 혼합용액을 사용하여 도 1e와 같이 현상을 수행하며, 레지스트 패턴을 베이킹한 후 O2프라즈마를 이용하여 잔유물 처리를 하고, 또한 블랙다운(breakdown) 전압특성을 개선하기 위하여 도 1f와 같이 상기 기판(1)을 일부 식각하는 1차 리세스 공정을 수행한 다음 상기 레지스트(4)(5)막의 측벽과 평탄면 위에 같은 두께의 절연막(6)이 증착되도록 실리콘 질화막, 또는 실리콘 산화막 등의 절연막(6)을 플라즈마 화학증착 방법 등에 의해 도 1g와 같이 증착하는데, 이때 상기 절연막(6)은 레지스트 페턴이 변형되지 않도록 100∼120℃의 온도에서 증착하며, 이와같이 절연막(6)을 증착하면 게이트 패턴 측벽에 증착된 절연막에 의해 좁아지고, 이 좁아진 패턴은 기판의 채널층이 드러나는 부분으로 증착된 게이트 금속이 드러난 채널층과 접촉되므로 실질적인 게이트 길이에 해당하며, 이 영역은 리소그라피에 의해 형성된 레지스트 패턴의 크기와 함께 증착막의 두께에 따라 임의의 크기를 갖도록 할 수 있기 때문에 게이트 길이를 리소그라피의 한계 보다도 더 작게 형성할 수 있다.First, as shown in FIG. 1A, by depositing and patterning a primary metal film 3 on a substrate 1 on which a channel layer is formed, and patterning an ohmic layer 2 thereon to form a T-type gate, Subsequently, the prepared sample was washed well, and then pretreated with HMDS as shown in FIG. 1B, and then 0.25 μm of PMMA resist 4 forming the gate bridge was formed, followed by MMA-MAA resist for forming the gate head as shown in FIG. 5) 1.05 μm was applied and then a baking process was performed, and exposure was performed as shown in FIG. 1D using a dose separation pattern, and then development was performed as shown in FIG. 1E using a MIBK: IPA mixed solution. After baking, the residue is treated using O 2 plasma, and a first recess process of partially etching the substrate 1 is performed to improve blackdown voltage characteristics, as shown in FIG. 1F. Resist (4) (5) Film An insulating film 6 such as a silicon nitride film or a silicon oxide film is deposited as shown in FIG. 1G by a plasma chemical vapor deposition method so that the insulating film 6 of the same thickness is deposited on the sidewalls and the flat surface, wherein the insulating film 6 is a resist pattern. When the insulating film 6 is deposited, it is narrowed by an insulating film deposited on the sidewalls of the gate pattern so as not to be deformed, and the narrowed pattern is a gate metal deposited as a portion where the channel layer of the substrate is exposed. It is in contact with the exposed channel layer, which corresponds to the actual gate length, and this region can be made to have any size depending on the thickness of the deposited film together with the size of the resist pattern formed by lithography, so that the gate length is smaller than the limit of the lithography. Can be formed.

이후, 도 1h와 같이, 절연막을 C2F6(80)+CHF3(20) 혼합가스 건식식각을 이용하여 측벽의 패턴은 식각이 되지 않도록 하고, 측벽의 상단부분을 둥글게 식각하며, 기판을 2차 리세스를 하며, 도 1i와 같이, 게이트 금속(7)을 증착한 후, 레지스트막(5)(4)을 아세톤 또는 용매에 담가 제거하는 과정에서 레지스트막 위의 금속이 들뜨게 되므로 T-형상을 가진 금속(7)만이 도 1j와 같이 남아 원하는T-형상의 게이트 금속이 형성된다.Then, as shown in Figure 1h, using the C 2 F 6 (80) + CHF 3 (20) mixed gas dry etching to prevent the pattern of the side wall is etched, and the upper portion of the side wall is etched round, the substrate After the second recess, as shown in FIG. 1I, the gate metal 7 is deposited, and the metal on the resist film is lifted in the process of immersing and removing the resist films 5 and 4 in acetone or a solvent. Only the metal 7 having the shape remains as shown in Fig. 1J to form the desired T-shaped gate metal.

이와같이, 본 발명은 전자빔을 이용하여 레지스트 T-형 우물 패턴을 형성한후, 저온의 PECVD 절연막을 증착하여 미세한 게이트 패턴을 형성한 다음, C2F6(80)+CHF3(20) 혼합가스 건식식각을 이용하여 측벽의 패턴은 식각이 되지 않으며, 바닥의 질화막을 제거하여 T-형 게이트를 형성하는 방법으로서, 이 과정에서 게이트의 다리부위와 머리부위가 만나는 부분을 둥글게 패턴을 형성하여 게이트 다리와 머리의 끊어짐을 방지할수 있으며, 실리콘 질화막이 게이트 다리를 양쪽에서 지지하여 미세한 게이트 다리와 면적이 큰 T-형 게이트 메탈을 들뜸없이 얻을 수 있고, 또한 게이트 머리 아래의 실리콘 질화막의 절연막을 자동 제거하여 기생 성분이 작아지도록 함으로써 고품위 트랜지스터의 제작이 가능하도록 한다.As described above, the present invention forms a resist T-well well pattern using an electron beam, and then deposits a low-temperature PECVD insulating film to form a fine gate pattern, and then a C 2 F 6 (80) + CHF 3 (20) mixed gas. The pattern of the side wall is not etched by using dry etching, and the T-type gate is formed by removing the nitride layer of the bottom. In this process, the gate part is formed in a round pattern where the leg part and the head part of the gate meet. The silicon nitride film supports the gate bridge on both sides, so that the fine gate bridge and the large T-type gate metal can be obtained without lifting, and the insulating film of the silicon nitride film under the gate head is automatically removed. By removing the parasitic components, the high quality transistors can be manufactured.

상술한 바와 같이 본 발명은 기존의 T-형 게이트 형성 방법에 비해 다음과 같은 효과를 갖는다.As described above, the present invention has the following effects as compared to the conventional T-type gate forming method.

첫째, T-형 레지스트 게이트 형성공정 후 절연막을 증착하여 미세한 게이트 선폭을 갖는 T-형 금속 패턴을 형성할 수 있으며, 둘째, 증착된 절연막이 T-형 게이트 메탈의 다리부위를 지지하므로 메탈의 들뜸 현상을 배제할 수 있고, 셋째, 게이트 다리와 머리 부위의 만나는 부위가 둥글게 됨으로서, 게이트 선폭 대 높이의 비가 개선되어 미세한 게이트 금속증착이 가능하고, 네째, 절연막의 두께에 의해 T-형 게이트의 선폭을 조절할 수 있는 장점을 지닌다.First, after the T-type resist gate forming process, an insulating film is deposited to form a T-type metal pattern having a fine gate line width. Second, the deposited insulating film supports the bridge portion of the T-type gate metal so that the metal is lifted. Phenomena can be eliminated, and third, the intersection of the gate bridge and the head is rounded, so that the ratio of gate line width to height is improved, and fine gate metal deposition is possible. Fourth, the line width of the T-type gate is determined by the thickness of the insulating film. It has the advantage of controlling.

Claims (5)

채널층이 형성된 기판(1)에 1차 금속막(3)과 오믹층(2)을 증착하여 패터닝하고, 게이트 다리를 형성하는 PMMA 레지스트(4)와 게이트 머리를 형성하기 위한 MMA-MMA 레지스트(5)를 도포하는 제 1 단계; 상기 MMA-MMA 레지스트(5)와 PMMA 레지스트(4)를 각각 식각하여 T-형 게이트의 머리 모양 및 T-형 게이트의 다리 모양을 형성하여 T-형 게이트 패턴을 형성한 후 노출된 기판의 일부를 1차 리세스하는 제 2 단계; 상기 레지스트(4, 5)막의 측벽과 평탄면 위에 플라즈마 화학증착 방법을 이용하여 절연막(6)을 같은 두께로 증착하는 제 3 단계; 상기 게이트 다리와 머리부위의 접촉 부분을 지지하는 지지부분 형성을 위해 건식식각을 이용하여 측벽의 패턴은 식각되지 않고, 측벽의 상단 부분은 경사지게 하며, 수평면은 제거되도록 상기 절연막(6)을 식각하고, 노출된 부분의 기판을 2차 리세스 하는 제 4 단계; 및 상기 식각한 절연막 위에 게이트 금속을 증착한 후 상기 레지스트(4, 5)막을 아세톤 또는 용매에 담가 제거하여 T-형상을 가진 게이트 금속(7)을 형성하는 제 5 단계를 포함하는 것을 특징으로 하는 지지대가 있는 미세한 티-형 게이트 제작방법.The primary metal film 3 and the ohmic layer 2 are deposited and patterned on the substrate 1 on which the channel layer is formed, and the PMMA resist 4 for forming the gate bridge and the MMA-MMA resist for forming the gate head ( 5) the first step of applying; The MMA-MMA resist 5 and the PMMA resist 4 are etched to form a head shape of the T-type gate and a bridge shape of the T-type gate to form a T-type gate pattern, and then a part of the exposed substrate. A second step of primary recessing; A third step of depositing an insulating film (6) on the sidewalls and planar surfaces of the resist (4, 5) film using a plasma chemical vapor deposition method with the same thickness; In order to form a supporting portion for supporting the contact portion of the gate leg and the head, the pattern of the sidewall is not etched using dry etching, the upper portion of the sidewall is inclined, and the insulating layer 6 is etched to remove the horizontal surface. A fourth step of secondary recessing the substrate in the exposed portion; And depositing a gate metal on the etched insulating film, and then immersing and removing the resist (4, 5) film in acetone or a solvent to form a gate metal (7) having a T-shape. How to make a fine tee-type gate with support. 제 1 항에 있어서, 상기 제 4 과정은 절연막 증착 후 건식식각을 이용하여 게이트 다리와 머리부분이 연결되는 부분을 둥글게 지지하기 위한 부분이 형성되도록 측벽의 상단부분이 둥글게 식각되도록 하는 것을 특징으로 하는 지지대가 있는 미세한 티-형 게이트 제작방법.The method of claim 1, wherein the fourth process comprises using a dry etching after the deposition of the insulating film so that the upper portion of the sidewall is etched roundly so that a portion for roundly supporting the portion where the gate bridge and the head are connected is formed. How to make a fine tee-type gate with support. 제 1 항에 있어서, 상기 제 5 과정은 저온의 PECVD 절연막을 증착한 후 그 증착 두께를 조절하여 게이트와 선촉폭을 미세 조절하는 것을 특징으로 하는 지지대가 있는 미세한 티-형 게이트 제작방법.The method of claim 1, wherein the fifth process comprises depositing a low-temperature PECVD insulating film and then adjusting the deposition thickness to finely adjust the gate and the line width. 제 1 항에 있어서, 상기 절연막은 C2F6(80)+CHF3(20) 혼합가스를 이용하여 건식식각을 수행하는 것을 특징으로 하는 지지대가 있는 미세한 티-형 게이트 제작방법.The method of claim 1, wherein the insulating film is dry etched using a C 2 F 6 (80) + CHF 3 (20) mixed gas. 제 1 항에 있어서, 상기 절연막은 레지스트(4)(5)의 측벽과 평탄면 위에 같은 두께의 절연막(6)이 증착되도록 실리콘 질화막 또는 실리콘 산화막 등의 절연막(6)을 플라즈마 화학 방법을 통하여 절연막(6)의 레지스트 패턴이 변형되지 않도록 100∼120℃의 온도에서 증착하는 것을 특징으로 하는 지지대가 있는 미세한 티-형 게이트 제작방법.2. The insulating film according to claim 1, wherein the insulating film is made of an insulating film 6, such as a silicon nitride film or a silicon oxide film, by plasma chemistry so that the insulating film 6 of the same thickness is deposited on the sidewalls of the resists 4 and 5 and the flat surface. A fine tee-type gate manufacturing method with a support, which is deposited at a temperature of 100 to 120 ° C. so as not to deform the resist pattern of (6).
KR1019970071617A 1997-12-22 1997-12-22 Method of formation for fine t-shaped gate with holder KR100274153B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970071617A KR100274153B1 (en) 1997-12-22 1997-12-22 Method of formation for fine t-shaped gate with holder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970071617A KR100274153B1 (en) 1997-12-22 1997-12-22 Method of formation for fine t-shaped gate with holder

Publications (2)

Publication Number Publication Date
KR19990052168A KR19990052168A (en) 1999-07-05
KR100274153B1 true KR100274153B1 (en) 2000-12-15

Family

ID=19528076

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970071617A KR100274153B1 (en) 1997-12-22 1997-12-22 Method of formation for fine t-shaped gate with holder

Country Status (1)

Country Link
KR (1) KR100274153B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7141464B2 (en) 2004-10-12 2006-11-28 Electronics And Telecommunications Research Institute Method of fabricating T-type gate
US9166011B2 (en) 2014-02-14 2015-10-20 Electronics And Telecommunications Research Institute Semiconductor device having stable gate structure and method of manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100703998B1 (en) * 2004-09-24 2007-04-04 동국대학교 산학협력단 Method for producing gate with wide head
CN117637456A (en) * 2024-01-26 2024-03-01 合肥欧益睿芯科技有限公司 Semiconductor device, gate manufacturing method thereof and electronic equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7141464B2 (en) 2004-10-12 2006-11-28 Electronics And Telecommunications Research Institute Method of fabricating T-type gate
US9166011B2 (en) 2014-02-14 2015-10-20 Electronics And Telecommunications Research Institute Semiconductor device having stable gate structure and method of manufacturing the same

Also Published As

Publication number Publication date
KR19990052168A (en) 1999-07-05

Similar Documents

Publication Publication Date Title
US7915106B2 (en) Method of fabricating T-gate
KR100274153B1 (en) Method of formation for fine t-shaped gate with holder
KR0170498B1 (en) Method of forming t-gate electrode
JP5040170B2 (en) Manufacturing method of semiconductor device
US20030082906A1 (en) Via formation in polymers
US20130270680A1 (en) Method for forming semiconductor devices with active silicon height variation
JP3062186B1 (en) Method for manufacturing thin film transistor
KR100521700B1 (en) Method for fabricating T-gate in semiconductor device
KR19980014634A (en) T (T) -type gate fabrication method
KR100262941B1 (en) Method for forming t-type gate of semiconductor device
JP2807122B2 (en) Method for manufacturing thin film transistor
KR0165759B1 (en) Method of forming metal pattern of mos transistor
JPS6390171A (en) Manufacture of field effect transistor
KR100499622B1 (en) Method for manufacturing cell projection mask of semiconductor device
KR100256809B1 (en) Method for forming contact hole in semiconductor device
KR100338091B1 (en) Method for manufacturing semiconductor device
KR100582586B1 (en) Fabrication method for T-type gate of a semiconductor element
JP3271185B2 (en) Manufacturing method of antireflection film
KR20040005381A (en) Method for fabricating cmos image sensor device
KR100259068B1 (en) Method for manufacturing mosfet of soi structure
JPH06310542A (en) Method of forming electrode of semiconductor device
KR20040057594A (en) Method for forming trench of semiconductor device
KR960003851B1 (en) Manufacturing process of compound semiconductor device
KR19980043594A (en) Method of forming a tee gate
JPH0384937A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070831

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee