KR20040057594A - Method for forming trench of semiconductor device - Google Patents
Method for forming trench of semiconductor device Download PDFInfo
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- KR20040057594A KR20040057594A KR1020020084358A KR20020084358A KR20040057594A KR 20040057594 A KR20040057594 A KR 20040057594A KR 1020020084358 A KR1020020084358 A KR 1020020084358A KR 20020084358 A KR20020084358 A KR 20020084358A KR 20040057594 A KR20040057594 A KR 20040057594A
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims description 44
- 230000004888 barrier function Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- Condensed Matter Physics & Semiconductors (AREA)
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- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 트렌치 형성방법에 관한 것으로, 보다 상세하게는 도핑에 따른 실리콘기판의 식각속도의 차이를 이용하여 트렌치 패턴의 조밀한 부분과 넓은 부분의 트렌치 깊이를 균일하게 하는 반도체소자의 트렌치 형성방법에 관한 것이다.The present invention relates to a method of forming a trench in a semiconductor device, and more particularly, to a trench of a semiconductor device which makes the trench depth of the denser and wider portions of the trench pattern uniform by using the difference in the etching rate of the silicon substrate according to the doping. It relates to a formation method.
현재의 반도체 제조기술은 고집적화와 고성능화를 요구한다. 따라서, MOSFET의 게이트 선폭축소 기술과 더불어 소자의 격리기술이 반도체소자의 고집적화에 가장 밀접하게 연관되어 있고 이를 향상시키기 위해 각 분야에서 많은 노력을 기울이고 있다.Current semiconductor manufacturing technology requires high integration and high performance. Therefore, the isolation technology of the device, together with the gate line reduction technology of the MOSFET, is most closely related to the high integration of the semiconductor device, and many efforts have been made in each field to improve it.
이에 부응하기 위해 소자격리 기술에서는 주로 R-LOCOS(Recessed LOCal Oxidation of Silicon) 기술로 어느 정도 효과를 나타내었으나, 0.25㎛ 이하 부터는 거의 모든 소자에 트렌치 형성기술을 이용하고 있다.In order to cope with this, device isolation technology mainly exhibited some effect with Recessed LOCal Oxidation of Silicon (R-LOCOS) technology, but trench forming technology is used for almost all devices from 0.25 μm or less.
그러나, 현재의 트렌치 형성기술을 이용한 소자격리는 실리콘기판을 건식식각할 때 미세 트렌치가 예기치 않게 자주 발생되고, 이러한 미세트렌치 주변의 격자결함에 의한 응력장으로 인해, 소자의 전압 인가시 누설전류등을 발생시킴으로 인해 소자의 신뢰성에 치명적인 손상을 준다는 문제점이 있다.However, device isolation using current trench forming technology unexpectedly frequently generates micro trenches when dry etching the silicon substrate, and due to the stress field caused by lattice defects around the micro trenches, a leakage current or the like is applied when the voltage is applied to the device. There is a problem in that it causes a fatal damage to the reliability of the device.
또한, 도 1에 도시된 바와 같이 실리콘기판상에 30∼200Å두께의 패드산화막과 500∼2000Å두께의 질화막을 증착한 후 5000∼12000Å두께의 감광막을 코팅하여 트렌치 건식식각을 진행할 때, 마이크로-로딩 효과에 의해 패턴의 밀도에 따른 트렌치 식각속도의 차이를 유발시켜 패턴의 조밀한 부분(20a)과 넓은 부분(20b)의 트렌치 깊이가 달라지게 된다.In addition, as shown in FIG. 1, after depositing a pad oxide film having a thickness of 30 to 200 microseconds and a nitride film having a thickness of 500 to 2000 microseconds on a silicon substrate, the micro-loading process is performed by coating a photosensitive film having a thickness of 5000 to 12000 microseconds by coating a trench. The effect causes a difference in the trench etching rate according to the density of the pattern, thereby changing the trench depth of the dense portion 20a and the wide portion 20b of the pattern.
이러한 트렌치 깊이의 차이는 식각부산물이 빠져나가야 할 높이가 너무 높고, 이온과 래디칼이 식각표면까지 이르는데 방해를 받기 때문에 발생하는 것이며,이는 패턴의 조밀한 부분(20a)과 넓은 부분(20b)에서 식각속도의 차이를 유발하는 주된 원인이 되고 있다.This difference in trench depth occurs because the height of the etch by-products is too high and the ions and radicals are disturbed to reach the etch surface, which is caused by the dense and wide portions 20a and 20b of the pattern. It is the main cause of the difference in etching speed.
이러한 식각속도의 차이로 인한 식각깊이의 차이는 향후의 0.13㎛ 이하급의 고성능 반도체소자인 경우에는 그 영향이 매우 심각하게 되고, 결국 조밀한 패턴과 넓은 패턴에서의 산화막의 전기적 특성에 차이를 가져오게 된다는 문제점이 있다.The difference in the etching depth due to the difference in etching speed is very serious in the case of high performance semiconductor devices of 0.13㎛ or less in the future, and eventually has a difference in the electrical characteristics of the oxide film in the dense pattern and the wide pattern. There is a problem that comes.
따라서, 본 발명은 상기 종래기술의 제반문제점을 해결하기 위하여 안출한 것으로서, 마이크로-로딩 효과를 현저하게 감소시키고, 미세 트렌치가 거의 없는 트렌치 형성기술을 구현하여 소자의 신뢰성을 높일 수 있는 반도체소자의 트렌치 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, a semiconductor device capable of significantly reducing the micro-loading effect, and implement a trench forming technology with little micro trench, thereby increasing the reliability of the device. The purpose is to provide a method of forming a trench.
도 1은 종래기술에 따른 반도체소자의 트렌치 형성방법에 있어서 패턴 조밀도에 따른 트렌치 깊이 차이를 도시한 도면.1 is a view showing a trench depth difference according to the pattern density in the trench forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 트렌치 형성방법을 도시한 공정별 단면도.2A to 2D are cross-sectional views illustrating processes for forming trenches in the semiconductor device according to the present invention.
(도면의 주요부분에 대한 부호설명)(Code description of main parts of drawing)
100 : 실리콘기판 120 : 이온주입용 감광막100 silicon substrate 120 ion implantation photosensitive film
130 : 제 1 이온주입층 135 : 제 2 이온주입층130: first ion implantation layer 135: second ion implantation layer
140 : 패드산화막 160 : 패드질화막140: pad oxide film 160: pad nitride film
180 : 트렌치용 감광막 200 : 트렌치180: trench photosensitive film 200: trench
상기 목적을 달성하기 위한 본 발명은, 제 1 이온주입공정에 의해 반도체기판내 소정 영역에 제 1 이온주입층을 형성하는 단계; 상기 제 1 이온주입층의 상부영역에 제 2 이온주입공정에 의해 상기 제 1 이온주입층 보다 넓은 면적을 갖는 제 2 이온주입층을 형성하는 단계; 및 상기 반도체기판 상부에 패드산화막과 패드질화막을 차례로 형성한 후 상기 제 1 및 제 2 이온주입층 상부의 상기 패드산화막과 패드질화막 부분과 함께 상기 제 1 및 제 2 이온주입층의 상기 반도체기판부분을 식각하여 트렌치를 형성하는 단계를 포함하여 구성됨을 특징으로 한다.The present invention for achieving the above object, the step of forming a first ion implantation layer in a predetermined region in the semiconductor substrate by a first ion implantation process; Forming a second ion implantation layer having a larger area than the first ion implantation layer by a second ion implantation process in an upper region of the first ion implantation layer; And sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate, and then the semiconductor substrate portion of the first and second ion implantation layers together with the pad oxide film and the pad nitride film portions on the first and second ion implantation layers. Etching to form a trench.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 트렌치 형성방법을 도시한 공정별 단면도이다.2A through 2D are cross-sectional views illustrating processes for forming trenches in the semiconductor device according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 실리콘기판(100)상에 이온주입용 감광막(120)을 패터닝한 후 1차적으로 인(P)으로 이온주입하여 상기 실리콘기판(100)내에 제 1 이온주입층(130)을 형성한다.First, as shown in FIG. 2A, after ion patterning the photoresist film 120 for ion implantation onto the silicon substrate 100, first ion implantation into the silicon substrate 100 by ion implantation into phosphorus (P) is performed. Form layer 130.
이때, 상기 1차 이온주입은 후속공정에서 형성될 트렌치의 한쪽 측벽으로 부터 50∼1000Å정도 떨어진 트렌치의 안쪽으로 수행한다.In this case, the primary ion implantation is performed to the inside of the trench about 50 to 1000 ∼ away from one sidewall of the trench to be formed in a subsequent process.
그 다음, 도 2b에 도시된 바와 같이, 주입되는 이온의 도우즈 및 에너지를 바꾸고 틸트를 5∼30°더 크게 하여 트렌치의 측벽으로부터 200∼1200Å정도 떨어진 트렌치의 안쪽으로 2차 이온주입을 수행하여 상기 제 1 이온주입층(130)의 상부영역에 그 보다 넓은 면적의 제 2 이온주입층(135)을 형성한다.Then, as shown in FIG. 2B, secondary ion implantation is performed into the trench, which is 200 to 1200 Å away from the sidewall of the trench, by changing the dose and energy of the implanted ions and increasing the tilt by 5 to 30 degrees. A second ion implantation layer 135 having a larger area is formed in the upper region of the first ion implantation layer 130.
이처럼 주입하는 이온의 분포를 다층구조(130)(135)로 하여 트렌치 중심부분의 식각속도를 높일 수 있다.In this way, the etch rate of the center portion of the trench may be increased by using the distribution of the implanted ions as the multilayer structures 130 and 135.
여기서, 상기 제 1 이온주입층(130)과 상기 제 2 이온주입층(135)은 그 순서를 바꾸어 형성할 수도 있다.Here, the first ion implantation layer 130 and the second ion implantation layer 135 may be formed in reverse order.
이때, 주입되는 이온은 실리콘을 전기적으로 활성화시킬 수 있는 주기율표상의 III족, V족 원소등을 이용하며, 상기 이온주입층의 깊이는 500∼5000Å 범위로 한다.In this case, the implanted ions use Group III, Group V elements, etc. on the periodic table capable of electrically activating silicon, and the depth of the ion implantation layer is in the range of 500 to 5000 Pa.
또한, 상기 이온주입은 그 에너지를 10∼200KeV범위로 하고 그 도즈량을1E10∼1E19정도의 범위로 하여 다단계로 수행한다.The ion implantation is carried out in multiple stages with the energy in the range of 10 to 200 KeV and the dose amount in the range of about 1E10 to 1E19.
이어서, 도 2c에 도시된 바와 같이, 10∼300Å두께의 패드산화막(140)과 500∼2000Å두께의 질화막(160)을 차례로 증착한 후 트렌치용 감광막(180)을 증착한다.Subsequently, as shown in FIG. 2C, a 10-300 kPa pad oxide film 140 and a 500-2000 kPa nitride film 160 are sequentially deposited, and then a trench photosensitive film 180 is deposited.
이때, 상기 질화막(160)은 500∼4000Å두께의 질산화막으로 이용할 수 있다.In this case, the nitride film 160 may be used as a nitride oxide film having a thickness of 500 to 4000 GPa.
여기서, 상기 패드산화막(140)과 질화막(160)은 상기 이온주입층(130)(135) 형성전에 먼저 증착하고 이를 트렌치용 마스크(180)를 이용하여 상기 질화막(160)과 패드산화막(140)을 건식식각한 후 이온주입층을 형성할 수도 있다.Here, the pad oxide layer 140 and the nitride layer 160 are first deposited before the ion implantation layers 130 and 135 are formed. The pad oxide layer 140 and the pad oxide layer 140 are formed using a trench mask 180. After dry etching the ion implantation layer may be formed.
이때, 상기 질화막(160)까지만 건식식각한 후 상기 패드산화막(140)을 남겨서 상기 패드산화막(140)을 후속의 이온주입공정에서 이온주입차단막으로 이용할 수도 있다.In this case, the pad oxide layer 140 may be used as an ion implantation barrier in a subsequent ion implantation process by leaving only the pad oxide layer 140 after dry etching up to the nitride layer 160.
그 다음, 도 2d에 도시된 바와 같이, 트렌치 건식식각을 수행한다.Then, as shown in FIG. 2D, trench dry etching is performed.
이때, 상기 트렌치 건식식각시 불소, 염소등의 라디칼족의 원소를 이용하고, 질소, 아르곤, 산소등의 불활성분자 또는 원자를 첨가하여 건식식각한다.In this case, the trench is dry-etched by using an element of radical group such as fluorine or chlorine, and adding an inert molecule or atom such as nitrogen, argon or oxygen.
이로써, 마이크로-로딩 효과를 현저히 감소시키고, 미세 트렌치를 없앤 트렌치를 구현하게 된다.This significantly reduces the micro-loading effect and results in a trench that eliminates fine trenches.
상술한 바와 같이, 본 발명은 좁은 패턴이나 넓은 패턴이나 무관하게 마이크로-로딩 효과를 현저하게 감소시켜 패턴이 조밀한 부분과 넓은 부분의 트렌치 깊이를 균일하게 함으로써 트렌치의 식각속도의 차이를 감소시킬 수 있다는 효과가 있다.As described above, the present invention can significantly reduce the micro-loading effect irrespective of the narrow pattern or the wide pattern, thereby reducing the difference in the etching speed of the trench by making the trench depth of the denser and wider portions uniform. There is an effect.
또한, 미세 트렌치가 거의 없는 트렌치를 형성하여 누설전류와 인접소자간 전기적 간섭효과를 줄일 수 있다는 효과가 있다.In addition, it is possible to reduce the leakage current and the electrical interference effect between adjacent devices by forming a trench with almost no fine trench.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
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