KR20010008561A - Method For Forming The Contact Hole Of Semiconductor Device - Google Patents

Method For Forming The Contact Hole Of Semiconductor Device Download PDF

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KR20010008561A
KR20010008561A KR1019990026468A KR19990026468A KR20010008561A KR 20010008561 A KR20010008561 A KR 20010008561A KR 1019990026468 A KR1019990026468 A KR 1019990026468A KR 19990026468 A KR19990026468 A KR 19990026468A KR 20010008561 A KR20010008561 A KR 20010008561A
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dry etching
contact hole
forming
polysilicon layer
semiconductor device
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KR1019990026468A
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Korean (ko)
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이승철
조직호
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김영환
현대전자산업 주식회사
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Publication of KR20010008561A publication Critical patent/KR20010008561A/en

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    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63B—APPARATUS FOR PHYSICAL TRAINING, GYMNASTICS, SWIMMING, CLIMBING, OR FENCING; BALL GAMES; TRAINING EQUIPMENT
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    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63B—APPARATUS FOR PHYSICAL TRAINING, GYMNASTICS, SWIMMING, CLIMBING, OR FENCING; BALL GAMES; TRAINING EQUIPMENT
    • A63B60/00—Details or accessories of golf clubs, bats, rackets or the like
    • A63B60/06—Handles
    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63B—APPARATUS FOR PHYSICAL TRAINING, GYMNASTICS, SWIMMING, CLIMBING, OR FENCING; BALL GAMES; TRAINING EQUIPMENT
    • A63B60/00—Details or accessories of golf clubs, bats, rackets or the like
    • A63B60/06—Handles
    • A63B60/22—Adjustable handles

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  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Physical Education & Sports Medicine (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to reduce a resistance value among a plug polysilicon layer, a substrate and a gate polysilicon layer accumulated within a contact hole. CONSTITUTION: A method for forming a contact hole of a semiconductor device comprises the following steps. A field oxide layer(20) is formed on a semiconductor substrate(10). A gate polysilicon layer(30) is formed thereon. An insulating layer(40) is stacked on the resultant. A photoresist layer having a contact portion is accumulated on a portion for forming a wiring line. A dry etching process for the insulating layer is performed through the contact portion of the photoresist layer. A contact hole is formed therefrom. An edge portion of the gate polysilicon layer is processed to a round shape. A plug polysilicon layer(60) is buried within the contact hole and ions are implanted therein.

Description

반도체소자의 콘택홀 형성방법 { Method For Forming The Contact Hole Of Semiconductor Device }Method for forming the contact hole of semiconductor device

본 발명은 콘택홀에 배선라인을 형성하는 방법에 관한 것으로서, 특히, 배선라인이 형성될 부위에 선택비가 낮은 건식 식각을 하여 콘택홀을 형성하면서 게이트폴리실리콘층의 모서리부분을 라운드지게 형성하므로 콘택홀(Contact Hole)내에 적층된 플러그폴리실리콘층과 기판 및 게이트폴리실리콘층 사이의 저항값을 저감하도록 하는 반도체소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a wiring line in the contact hole, and in particular, the contact portion is formed by round etching the gate polysilicon layer while forming a contact hole with a low selectivity dry etching on the site where the wiring line is to be formed The present invention relates to a method of forming a contact hole in a semiconductor device to reduce a resistance value between a plug polysilicon layer stacked in a hole and a substrate and a gate polysilicon layer.

일반적으로, 구동속도가 빠른 패스트 에스램(Fast SRAM)에 있어서 하이 로드 레지스터장치(High Load Register Device)는 반도체기판에 트랜지스터를 형성한 후에 절연층을 적층한 후 마스킹식각으로 콘택홀을 형성하고, 그 콘택홀내에 배선라인 역할을 하는 폴리 실리콘을 몰입하여서 임플랜트(Implant)공정으로 이온을 주입한 후 하부에 형성되어 있는 구동 트랜지스터(Driver Transitor)에 스탠바이 전류(Stanby Current)를 공급하여 주는 장치이다.In general, in a fast SRAM having a high driving speed, a high load register device forms a contact hole by masking etching after stacking an insulating layer after forming a transistor on a semiconductor substrate. It is a device that supplies a standby current to a driver transistor formed at a lower part by injecting polysilicon that acts as a wiring line in the contact hole and implanting ions through an implant process.

이 때, 하이 로드 레지스터장치에서는 콘택홀내에 몰입된 플러그폴리실리콘층에 이온을 주입하는 임플랜트공정의 조절(Control)이 매우 중요한 역할을 한다.In this case, the control of the implant process for implanting ions into the plug polysilicon layer immersed in the contact hole plays a very important role in the high load resistor device.

그런데, 상기한 패스트 에스램(Fast SRAM)에서 하이 로드 레지스터장치는 플러그폴리실리콘층을 형성하기 위한 마스크작업시 마스크의 미스얼라인(MisAlign)으로 인한 콘택홀의 CD 콘트롤이 힘들 뿐만아니라 마스크의 미스얼라인으로 인하여 플러그폴리실리콘층에 이온을 주입하는 임플랜트공정에서 이온 주입의 균일도 (Uniformity)가 악화되는 문제점을 지닌다.However, in the fast SRAM, the high load resistor device is difficult to control the CD of the contact hole due to the misalignment of the mask during masking to form the plug polysilicon layer, as well as the misalignment of the mask. Due to phosphorus, uniformity of ion implantation is deteriorated in an implant process of implanting ions into the plug polysilicon layer.

따라서, 이온의 임플랜트 조절이 균일하고 일정하지 않음으로 게이트폴리실리콘층(Polyl) 및 플러그폴리실리콘층(Poly3)과 반도체기판 사이에 노드 콘택 저항(Node Contact Registor)이 높아지는 현상이 발생되고, 이로 인하여 반도체장치의 전압강하(Yield Drop)현상을 유발하여 소자의 전기적인 특성을 저하하는 문제점으로 작용하였다.Therefore, the implant control of ions is not uniform and uniform, so that a node contact resistance is increased between the gate polysilicon layer (Polyl) and the plug polysilicon layer (Poly3) and the semiconductor substrate. It caused the voltage drop of the semiconductor device and caused a problem of lowering the electrical characteristics of the device.

본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판의 필드산화막상에 게이트폴리실리콘층(Poly1층)을 형성한 후 절연막을 적층하고, 배선라인이 형성될 부위에 감광막을 적층하여 콘택홀을 형성하되 선택비가 낮은 건식식각을 하여게이트폴리실리콘층의 모서리부분을 라운드지게 형성한 후, 콘택홀 (Contact Hole)내에 플러그폴리실리콘층(Poly3)을 적층하여 후속공정을 진행하므로 플러그폴리실리콘층과 기판 및 게이트폴리실리콘층 사이의 저항값을 저감하도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and after forming a gate polysilicon layer (Poly1 layer) on a field oxide film of a semiconductor substrate, an insulating film is laminated, and a photoresist film is laminated to a portion where a wiring line is to be formed to form a contact hole. Dry etching with low selectivity to form round edges of the gate polysilicon layer, and then the plug polysilicon layer (Poly3) is laminated in the contact hole to perform the subsequent process. It is an object to reduce the resistance value between the substrate and the gate polysilicon layer.

도 1 내지 도 3은 본 발명에 따른 반도체소자의 콘택홀 형성방법을 순차적으로 보인 도면이다.1 to 3 are views sequentially showing a method for forming a contact hole in a semiconductor device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 : 반도체기판 20 : 필드산화막10: semiconductor substrate 20: field oxide film

30 ; 게이트폴리실리콘층 40 : 절연막30; Gate polysilicon layer 40: insulating film

50 : 감광막 55 : 콘택부위50: photosensitive film 55: contact portion

60 : 플러그폴리실리콘층60: plug polysilicon layer

이러한 목적은 반도체기판에 필드산화막을 형성하고, 그 상부면에 게이트폴리실리콘을 형성하는 단계와; 상기 결과물 상에 절연막을 적층한 후 배선라인이 형성될 부분에 콘택부위를 갖는 감광막을 적층하는 단계와; 상기 감광막의 콘택부위를 통하여 식각비가 낮은 건식식각으로 절연막을 식각하여 콘택홀을 형성함과 동시에 게이트폴리실리콘층의 모서리 부분을 라운드지게 형성하는 단계와; 상기 콘택홀 내에 플러그폴리실리콘층을 몰입한 후 이온을 주입하는 단계를 포함한 반도체소자의 콘택홀 형성방법을 제공함으로써 달성된다.This object is achieved by forming a field oxide film on a semiconductor substrate and forming a gate polysilicon on an upper surface thereof; Stacking an insulating film on the resultant and then laminating a photosensitive film having a contact portion on a portion where a wiring line is to be formed; Forming a contact hole by etching the insulating layer by dry etching having a low etching ratio through the contact portion of the photoresist layer, and simultaneously forming round corners of the gate polysilicon layer; It is achieved by providing a method for forming a contact hole in a semiconductor device including the step of implanting a plug polysilicon layer into the contact hole and implanting ions.

그리고, 상기 건식식각(Dry Etch)은 플라즈마(Plasma)건식식각으로 진행하도록 하고, 이 때, 이 건식식각은 선택비가 낮은 제1건식식각에 선택비가 높은 제2건식식각을 더 포함하여 이루어질 수 있다.The dry etching may be performed by plasma dry etching, wherein the dry etching may further include a second dry etching having a high selectivity to the first dry etching having a low selectivity. .

상기 제1건식식각은 100 ∼ 400mTorr의 압력과, 1000 ∼ 1400Watt의 파워와, CF4가스를 10 ∼ 100sccm의 량 및 Ar가스를 100 ∼ 700sccm의 량으로 10초 ∼ 100초간 실시한다.The first dry etching is performed at a pressure of 100 to 400 mTorr, power of 1000 to 1400 Watts, CF 4 gas at an amount of 10 to 100 sccm, and Ar gas at an amount of 100 to 700 sccm for 10 seconds to 100 seconds.

상기 제2건식식각은 100 ∼ 500mTorr의 압력과, 1000 ∼ 1700Watt의 파워와, CF4가스를 10 ∼ 100sccm의 량, CHF3가스를 10 ∼ 100sccm의 량과, Ar가스를 100 ∼ 700sccm의 량으로 10초 ∼ 100초간 실시하며, 오버에치 타겟(Over Etch Target)은 10 ∼ 50% 범위에서 실시한다.The second dry etching has a pressure of 100 to 500 mTorr, a power of 1000 to 1700 Watts, a CF 4 gas of 10 to 100 sccm, a CHF 3 gas of 10 to 100 sccm, and an Ar gas of 100 to 700 sccm 10 seconds to 100 seconds, and the over-etch target (Over Etch Target) is carried out in 10 to 50% range.

그리고, 상기 플러그폴리실리콘층의 증착온도는 500 ∼ 800℃이고, 증착압력은 500 ∼ 1500Å이며, SiH4및 N2가스를 사용하여 증착하고, 증착을 위한 타겟은 500 ∼ 1500Å의 범위내에서 실시하도록 한다.The deposition temperature of the plug polysilicon layer is 500 to 800 ° C., the deposition pressure is 500 to 1500 kPa, the deposition is carried out using SiH 4 and N 2 gases, and the target for deposition is performed within the range of 500 to 1500 kPa. Do it.

상기 플러그폴리실리콘층에 이온을 주입하는 임플랜트공정은 As 혹은 P이온을 주입하고, 도즈량은 2.0E13 ∼ 4.0E15의 범위이고, 30 ∼100 Kev의 전압을 공급하여 주입하도록 한다.In the implant process of implanting ions into the plug polysilicon layer, As or P ions are implanted, and the dose is in the range of 2.0E13 to 4.0E15, and is supplied by supplying a voltage of 30 to 100 Kev.

이하, 첨부한 도면에 의거하여 본 발명에 바람직한 일실시예에 대하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 5는 본 발명에 따른 반도체소자의 콘택홀 형성방법을 순차적으로 보인 도면이다.1 to 5 are views sequentially showing a method for forming a contact hole in a semiconductor device according to the present invention.

도 1 은 반도체기판(10)에 필드산화막(20)을 형성하고, 그 상부면에 게이트폴리실리콘층(30)을 형성한 후 상기 결과물 상에 절연막(40)을 적층한 후에 배선라인(저항라인 및 전원공급라인)이 형성될 부분에 콘택부위(55)를 갖는 감광막(50)을 적층하는 상태를 도시하고 있다.FIG. 1 shows a field oxide film 20 formed on a semiconductor substrate 10, a gate polysilicon layer 30 formed on an upper surface thereof, and a wiring line (resistance line) after stacking an insulating film 40 on the resultant. And a state in which a photosensitive film 50 having a contact portion 55 is stacked on a portion where a power supply line) is to be formed.

도 2는 상기 감광막(50)의 콘택부위(55)를 통하여 식각비가 낮은 건식식각, 특히, 플라즈마 건식식각으로 절연막(40)을 식각하여 콘택홀(45)을 형성함과 동시에 게이트폴리실리콘층(30)의 모서리 부분을 라운드지도록 라운드부위(35)를 형성하는 상태를 도시하고 있다.FIG. 2 illustrates a method of forming a contact hole 45 by etching the insulating layer 40 by dry etching having a low etch rate, in particular, plasma dry etching, through the contact portion 55 of the photoresist film 50. 30 shows a state in which the round portion 35 is formed to round the corner portion.

상기 건식식각은 선택비가 낮은 제1건식식각과, 선택비가 높은 제2건식식각으로 분리되어져 진행 된다.The dry etching is performed by separating the first dry etching having a low selection ratio and the second dry etching having a high selection ratio.

상기 제1건식식각은 100 ∼ 400mTorr의 압력과, 1000 ∼ 1400Watt의 파워와, CF4가스를 10 ∼ 100sccm의 량 및 Ar가스를 100 ∼ 700sccm의 량으로 10초 ∼ 100초간 실시하도록 한다.The first dry etching is performed at a pressure of 100 to 400 mTorr, power of 1000 to 1400 Watts, CF 4 gas at an amount of 10 to 100 sccm, and Ar gas at an amount of 100 to 700 sccm for 10 seconds to 100 seconds.

그리고, 상기 제2건식식각은 100 ∼ 500mTorr의 압력과, 1000 ∼ 1700Watt의 파워와, CF4가스를 10 ∼ 100sccm의 량, CHF3가스를 10 ∼ 100sccm의 량과, Ar가스를 100 ∼ 700sccm의 량으로 10초 ∼ 100초간 실시하고, 상기 제2건식식각시, 오버에치 타겟은 10 ∼ 50% 범위에서 실시하도록 한다.The second dry etching process includes a pressure of 100 to 500 mTorr, a power of 1000 to 1700 Watts, an amount of CF 4 gas of 10 to 100 sccm, an amount of CHF 3 gas of 10 to 100 sccm, and an Ar gas of 100 to 700 sccm. The amount is carried out for 10 seconds to 100 seconds, and during the second dry etching, the over-etch target is performed in the range of 10 to 50%.

상기 플러그폴리실리콘층(60)의 증착온도는 500 ∼ 800℃이고, 증착압력은 500 ∼ 1500Å이며, SiH4및 N2가스를 사용하여 증착하고, 상기 플러그폴리실리콘층(60)을 증착하기 위한 타겟은 500 ∼ 1500Å의 범위내에서 실시한다.The deposition temperature of the plug polysilicon layer 60 is 500 to 800 ° C., the deposition pressure is 500 to 1500 kPa, and is deposited using SiH 4 and N 2 gases, for depositing the plug polysilicon layer 60. The target is performed within the range of 500 to 1500 kPa.

한편, 상기 플러그폴리실리콘층(60)에 이온을 주입하는 임플랜트공정은 AS(아르세닉) 이온 혹은 P(포스포러스)이온으로서, 도즈(Dose)량은 2.0E13 ∼ 4.0E15의 범위로 공급하고, 30 ∼100 Kev의 전압을 공급하여 형성하도록 한다.On the other hand, the implant process for implanting ions into the plug polysilicon layer 60 is AS (arcenic) ions or P (phosphorus) ions, the dose is supplied in the range of 2.0E13 ~ 4.0E15, It is formed by supplying a voltage of 30-100 Kev.

도 3은 상기 콘택홀(45)내에 플러그폴리실리콘층을 몰입한 후 이온을 주입하는 상태를 도시하고 있다.3 illustrates a state in which ions are implanted after the plug polysilicon layer is immersed in the contact hole 45.

따라서, 본 발명에 따른 반도체소자의 콘택홀 형성방법을 이용하게 되면, 반도체기판의 필드산화막상에에 게이트폴리실리콘층(Poly1층)을 형성한 후 절연막을 적층하고, 배선라인이 형성될 부위에 감광막을 적층하여 선택비가 낮은 건식 식각을 하여 콘택홀을 형성하면서 게이트폴리실리콘층의 모서리부분을 라운드지게 형성하여 콘택홀(Contact Hole)내에 플러그폴리실리콘층(Poly3)을 적층하여 후속 공정을 진행하므로 플러그폴리실리콘층과 기판 및 게이트폴리실리콘층 사이의 저항값을 저감하여 소자의 구동능력을 향상시키는 매우 유용하고 효과적인 발명이다.Therefore, when the contact hole forming method of the semiconductor device according to the present invention is used, a gate polysilicon layer (Poly1 layer) is formed on the field oxide film of the semiconductor substrate, and then an insulating film is laminated to the site where the wiring line is to be formed. Since the photoresist layer is laminated to form a contact hole by dry etching having a low selectivity, the corner portion of the gate polysilicon layer is rounded, and a plug polysilicon layer (Poly3) is laminated in the contact hole to perform the subsequent process. It is a very useful and effective invention to improve the driving capability of the device by reducing the resistance value between the plug polysilicon layer and the substrate and the gate polysilicon layer.

Claims (9)

반도체기판에 필드산화막을 형성하고, 그 상부면에 게이트폴리실리콘을 형성하는 단계와;Forming a field oxide film on the semiconductor substrate and forming gate polysilicon on an upper surface thereof; 상기 결과물 상에 절연막을 적층한 후, 배선라인이 형성될 부분에 콘택부위를 갖는 감광막을 적층하는 단계와 ;Laminating an insulating film on the resultant, and then laminating a photosensitive film having a contact portion on a portion where a wiring line is to be formed; 상기 감광막의 콘택부위를 통하여 식각비가 낮은 건식식각으로 절연막을 식각하여 콘택홀을 형성함과 동시에 게이트폴리실리콘층의 모서리 부분을 라운드지게 형성하는 단계와;Forming a contact hole by etching the insulating layer by dry etching having a low etching ratio through the contact portion of the photoresist layer, and simultaneously forming round corners of the gate polysilicon layer; 상기 콘택홀내에 플러그폴리실리콘층을 매립한 후, 이온을 주입하는 단계를 포함한 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.And embedding a plug polysilicon layer in the contact hole and implanting ions therein. 제 1 항에 있어서, 상기 선택비가 낮은 건식식각은 플라즈마 건식식각을 이용하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the dry etching having a low selectivity uses plasma dry etching. 제 1 항 또는 제 2 항에 있어서, 상기 선택비가 낮은 건식식각을 제1건식식각이라 할 때, 이 제1건식식각에 선택비가 높은 제2건식식각을 더 포함하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The semiconductor device according to claim 1 or 2, wherein when the dry etching having a low selection ratio is referred to as a first dry etching, the first dry etching further comprises a second dry etching having a high selection ratio. Hole formation method. 제 3 항에 있어서, 상기 제1건식식각은 100 ∼ 400mTorr의 압력과, 1000 ∼ 1400Watt의 파워와, CF4가스를 10 ∼ 100sccm 및 Ar가스를 100 ∼ 700sccm으로 10초 ∼ 100초간 실시하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 3, wherein the first dry etching is performed at a pressure of 100 to 400 mTorr, power of 1000 to 1400 Watts, CF 4 gas at 10 to 100 sccm, and Ar gas at 100 to 700 sccm for 10 seconds to 100 seconds. A contact hole forming method of a semiconductor device. 제 3 항에 있어서, 상기 제2건식식각은 100 ∼ 500mTorr의 압력과, 1000 ∼ 1700Watt의 파워와, CF4가스를 10 ∼ 100sccm, CHF3가스를 10 ∼ 100sccm 및 Ar가스를 100 ∼ 700sccm으로 공급하여, 10초 ∼ 100초간 실시하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법The method of claim 3, wherein the second dry etching is performed at a pressure of 100 to 500 mTorr, a power of 1000 to 1700 Watts, 10 to 100 sccm of CF 4 gas, 10 to 100 sccm of CHF 3 gas, and 100 to 700 sccm of Ar gas. And a contact hole forming method of a semiconductor device, characterized in that performed for 10 seconds to 100 seconds. 제 5 항에 있어서, 상기 제2건식식각시, 오버에치 타겟은 10 ∼ 50% 범위에서 실시하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 5, wherein the second etching process comprises performing an over-etch target in a range of 10 to 50%. 제 1 항에 있어서, 상기 플러그폴리실리콘층의 증착온도는 500 ∼ 800℃이고, 증착압력은 500 ∼ 1500Å이며, SiH4및 N2가스를 사용하여 증착하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the deposition temperature of the plug polysilicon layer is 500 to 800 ° C., the deposition pressure is 500 to 1500 kPa, and deposition is performed using SiH 4 and N 2 gases. Way. 제 7 항 있어서, 상기 플러그폴리실리콘층의 증착을 위한 타겟은 500 ∼ 1500Å의 범위내에서 실시하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.8. The method of claim 7, wherein the target for depositing the plug polysilicon layer is performed within the range of 500-1500 kV. 제 1 항에 있어서, 상기 플러그폴리실리콘층에 이온을 주입하는 임플랜트공정은 As 혹은 P이온을 주입하고, 도즈량은 2.0E13 ∼ 4.0E15의 범위로 공급하고, 30 ∼100Kev의 전압을 가하여 주입하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The implant process of claim 1, wherein the implantation step of implanting ions into the plug polysilicon layer implants As or P ions, the dose is supplied in the range of 2.0E13 to 4.0E15, and is injected by applying a voltage of 30 to 100 Kev. A method of forming a contact hole in a semiconductor device, characterized in that.
KR1019990026468A 1999-07-02 1999-07-02 Method For Forming The Contact Hole Of Semiconductor Device KR20010008561A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100438789B1 (en) * 2002-09-19 2004-07-05 삼성전자주식회사 Electrode line structure having fine line width in semiconductor device and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100438789B1 (en) * 2002-09-19 2004-07-05 삼성전자주식회사 Electrode line structure having fine line width in semiconductor device and method for forming the same

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