KR100249182B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100249182B1 KR100249182B1 KR1019960051820A KR19960051820A KR100249182B1 KR 100249182 B1 KR100249182 B1 KR 100249182B1 KR 1019960051820 A KR1019960051820 A KR 1019960051820A KR 19960051820 A KR19960051820 A KR 19960051820A KR 100249182 B1 KR100249182 B1 KR 100249182B1
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- South Korea
- Prior art keywords
- semiconductor device
- semiconductor
- etching
- line
- wafer chuck
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 27
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 239000003507 refrigerant Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000010791 quenching Methods 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000002826 coolant Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 230000000171 quenching effect Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 13
- 238000001816 cooling Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법에 관한 것으로, 특히 고집적 반도체 소자에 적합한 커패시터를 제조하는데 적당하도록 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법에 관한 것이다.The present invention relates to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device using the same, and more particularly, to a semiconductor manufacturing apparatus and a semiconductor device manufacturing method using the same to be suitable for manufacturing a capacitor suitable for a highly integrated semiconductor device.
이를 위한 본 발명의 반도체 제조장치는 웨이퍼 척을 구비한 반도체 제조장치에 있어서, 상기 웨이퍼 척에 급냉 및 급가열이 가능하도록 냉매라인과 히팅라인을 분리하여 형성되는 것을 특징으로 한다. 그리고 웨이퍼 척에 급냉 및 급가열이 가능 하도록 냉매라인과 히팅라인을 구비한 반도체 제조장비를 이용하여 반도체 소자를 제조하는 방법에 있어서, 반도체 기판 전면에 절연층을 형성하는 공정과; 상기 절연층에 도전층을 형성하여 상온에서 메인에칭하는 공정과; 상기 남아있는 잔류물을 제거하기 위해 극저온에서 오버에칭하는 공정을 포함하여 이루어짐을 특징으로 한다.The semiconductor manufacturing apparatus of the present invention for this purpose is a semiconductor manufacturing apparatus having a wafer chuck, characterized in that formed by separating the refrigerant line and the heating line to enable rapid cooling and rapid heating on the wafer chuck. And a method of manufacturing a semiconductor device using a semiconductor manufacturing equipment having a refrigerant line and a heating line to quench and rapidly heat the wafer chuck, the method comprising: forming an insulating layer on the entire surface of the semiconductor substrate; Forming a conductive layer on the insulating layer and main etching at room temperature; It is characterized in that it comprises a step of over-etching at cryogenic temperatures to remove the remaining residue.
Description
본 발명은 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법에 관한 것으로, 특히 고집적 반도체 소자에 적합한 커패시터를 제조하는데 적당하도록 한 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device using the same, and more particularly, to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device using the same, which are suitable for manufacturing a capacitor suitable for a highly integrated semiconductor device.
일반적으로 에칭공정은 메인에칭(Main Etching)과 오버에칭(Over Etching)으로 구성되며, 메인에칭에서는 측면(Profile)을 콘트롤(Control)하고, 오버에칭에서는 메인에칭시 사용되고 남은 잔류물을 제거하게 된다.In general, the etching process is composed of main etching and over etching. In main etching, the profile is controlled, and in over etching, residual residues used during main etching are removed. .
이하, 첨부된 도면을 참조하여 종래의 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a conventional semiconductor manufacturing apparatus and a semiconductor device manufacturing method using the same will be described with reference to the accompanying drawings.
도 1은 종래의 웨이퍼 척을 나타낸 평면도이고, 도 2a 내지 도 2c는 종래의 스택(Stack) 구조의 커패시터 제조방법을 나타낸 공정 단면도이다.1 is a plan view illustrating a conventional wafer chuck, and FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor having a conventional stack structure.
먼저, 도 1에 도시한 바와 같이 웨이퍼 척(1) 상부에 웨이퍼(도면에 도시하지 않았음)가 로딩되면 웨이퍼를 고정시켜 웨이퍼의 얼라인 및 노광을 실시한다.First, as shown in FIG. 1, when a wafer (not shown) is loaded on the wafer chuck 1, the wafer is fixed to perform alignment and exposure of the wafer.
또한, 웨이퍼 척(1)에 냉매라인(2)을 형성하여 메인에칭과 오버에칭을 같은 온도에서 실시한다.In addition, a coolant line 2 is formed on the wafer chuck 1 to perform main etching and overetching at the same temperature.
제2a도에 도시한 바와 같이 반도체 기판(20) 상에 제 1절연층(21)을 형성하고, 상기 제 1절연층(21) 상에 제 1폴리 실리콘층(22)을 형성한다. 이때, 제 1 절연층(21)은 산화막 또는 질화막을 사용한다.As shown in FIG. 2A, a first insulating layer 21 is formed on the semiconductor substrate 20, and a first polysilicon layer 22 is formed on the first insulating layer 21. At this time, an oxide film or a nitride film is used for the first insulating layer 21.
그리고 상기 제 1폴리 실리콘층(22) 상에 포토레지스트(Photoresist)을 형성하고, 현상 및 노광공정을 이용하여 패터닝한 후 포토레지스트 패턴(23)을 형성한다.Then, a photoresist is formed on the first polysilicon layer 22, and patterned using a development and exposure process to form a photoresist pattern 23.
이어, 도 2b에 도시한 바와같이 포토레지스트 패턴(23)을 마스크로 하여 상기 제 1폴리 실리콘층(22)을 메인에칭 한다. 이때, 제 1 폴리 실리콘층(22)은 건식식각 또는 습식식각을 이용한다.Next, as shown in FIG. 2B, the first polysilicon layer 22 is main-etched using the photoresist pattern 23 as a mask. In this case, the first polysilicon layer 22 uses dry etching or wet etching.
여기서, 제 1절연층(21) 상에 건식식각 또는 습식식각에 사용되고 남은 잔류물(24)이 발생한다.Here, a residue 24 used for dry etching or wet etching occurs on the first insulating layer 21.
이어서 도 2c에 도시한 바와 같이, 상기 포토레지스트 패턴(23)을 제거한 후, 상기 남아있는 잔류물(24)을 제거하기 위해 오버에칭을 실시하여 커패시터의 하부 전극을 형성한다. 여기서 메인에칭과 오버에칭은 같은 온도로 실시하며, 온도는 -20~40℃이다.Subsequently, as shown in FIG. 2C, after the photoresist pattern 23 is removed, the bottom electrode of the capacitor is formed by overetching to remove the remaining residue 24. Here, main etching and over etching are performed at the same temperature, and the temperature is -20 ~ 40 ℃.
이때, 상기 제 1절연층(21)과 인접한 제 1폴리 실리콘층(22)의 모서리 부분이 언더컷트(undercut) 또는 나칭(notching) 현상 그리고 네가티브 슬로프(Negative Slop) 현상이 발생한다. 그리고 오버에칭 실시 조건은 기판(20)에 대해 고선택비를 유지한다.At this time, an edge portion of the first polysilicon layer 22 adjacent to the first insulating layer 21 is undercut or notched, and a negative slope phenomenon occurs. In addition, the overetching condition maintains a high selectivity with respect to the substrate 20.
한편, 실린더(Cylinder) 구조의 커패시터 제조방법에 있어서도 같은 현상이 발생한다.On the other hand, the same phenomenon occurs in the method of manufacturing a capacitor having a cylinder structure.
그러나 상기와 같은 종래의 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, the above-described conventional semiconductor manufacturing apparatus and semiconductor device manufacturing method using the same have the following problems.
메인에칭시 이용하는 습식식각 또는 건식식각 후, 남아있는 잔류물을 제거하기 위한 오버에칭시 메인에칭과 같은 온도를 사용하므로 폴리 실리콘층 하부영역에 언더컷트 및 나칭현상이 일어나고 또는 폴리 실리콘층 측면에 네가티브 슬로프가 형성되었다.After wet etching or dry etching used for main etching, undercutting and naching occurs in the lower area of the polysilicon layer because the same temperature as the main etching is used for overetching to remove residual residues. The slope was formed.
따라서 에칭공정에 있어서 측면을 효과적으로 컨트롤 할 수가 없다.Therefore, the side surface cannot be effectively controlled in the etching process.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로 커패시터 하부 전극 형성시 메인에칭과 오버에칭을 실시할 때, 서로 다른 온도를 사용하여 커패시터 하부전극을 수직형태로 형성하므로 측면 콘트롤을 높이는데 그 목적이 있다.The present invention has been made to solve the above problems, and when the main etching and over-etching when forming the lower electrode of the capacitor, the lower electrode is formed in a vertical form using different temperatures to increase the side control. There is this.
제1도은 종래의 웨이퍼 척을 나타낸 평면도1 is a plan view showing a conventional wafer chuck
제2a도 내지 제2c도는 종래의 스택 구조의 커패시터 제조방법을 나타낸 공정 단면도2A through 2C are cross-sectional views illustrating a method of manufacturing a capacitor having a conventional stack structure.
제3도는 본 발명의 웨이퍼 척을 나타낸 평면도3 is a plan view showing a wafer chuck of the present invention.
제4a도 내지 제4c도는 본 발명의 스택 구조의 커패시터 제조방법을 나타낸 공정 단면도4A to 4C are cross-sectional views illustrating a method of manufacturing a capacitor having a stack structure according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
30:웨이퍼 척31:고속냉매30: wafer chuck 31: high speed refrigerant
32:히팅라인40:기판32: heating line 40: substrate
41:제 1절연막42:폴리 실리콘층41: first insulating film 42: polysilicon layer
43:포토레지스트 페턴44:잔류물43: photoresist pattern 44: residue
이와 같은 본 발명의 반도체 제조장치는 웨이퍼 척을 구비한 반도체 제조장치에 있어서, 상기 웨이퍼 척에 급냉 및 급가열이 가능하도록 냉매라인과 히팅라인을 분리하여 형성되는 것을 특징으로 한다. 그리고 웨이퍼 척에 급냉 및 급가열이 가능 하도록 냉매라인과 히팅라인을 구비한 반도체 제조장비를 이용하여 반도체 소자를 제조하는 방법에 있어서, 반도체 기판 전면에 절연층을 형성하는 공정과; 상기 절연층에 도전층을 형성하여 상온에서 메인에칭하는 공정과; 상기 남아있는 잔류물을 제거하기 위해 극저온에서 오버에칭하는 공정을 포함하여 이루어짐을 특징으로 한다.Such a semiconductor manufacturing apparatus of the present invention is a semiconductor manufacturing apparatus having a wafer chuck, characterized in that formed by separating the refrigerant line and the heating line to enable rapid cooling and rapid heating on the wafer chuck. And a method of manufacturing a semiconductor device using a semiconductor manufacturing equipment having a refrigerant line and a heating line to quench and rapidly heat the wafer chuck, the method comprising: forming an insulating layer on the entire surface of the semiconductor substrate; Forming a conductive layer on the insulating layer and main etching at room temperature; It is characterized in that it comprises a step of over-etching at cryogenic temperatures to remove the remaining residue.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법에 대하여 보다 상세히 설명하면 다음과 같다.Hereinafter, a semiconductor manufacturing apparatus of the present invention and a semiconductor device manufacturing method using the same will be described in detail with reference to the accompanying drawings.
제3도는 본 발명의 웨이퍼 척을 나타낸 평면도이고, 도 4a 내지 4c는 본 발명의 스택 구조의 커패시터 제조방법을 나타낸 공정 단면도이다.3 is a plan view showing a wafer chuck of the present invention, Figures 4a to 4c is a process cross-sectional view showing a capacitor manufacturing method of the stack structure of the present invention.
제3도에 도시한 바와 같이 웨이퍼 척(30)에 급냉 및 급가열이 가능하도록 냉매라인(31)와 히팅라인(32)를 분리하여 나선모양으로 형성한다. 이때, 상기 히팅라인(32)으로는 열선 코일을 이용한다.As shown in FIG. 3, the coolant line 31 and the heating line 32 are separated and formed in a spiral shape so as to rapidly cool and rapidly heat the wafer chuck 30. At this time, a heating coil 32 is used as a heating coil.
그리고 상기 웨이퍼 척의 동작을 설명하면 다음과 같다.The operation of the wafer chuck will now be described.
먼저, 웨이퍼의 메인에칭을 상온에서 실시한 후, 냉매라인(30)를 이용하여 저온에서 오버에칭을 실시한다. 그리고 다음 웨이퍼를 메인에칭 실시하기 위해 히팅라인(32)을 이용하여 상온으로의 온도변화를 시킨다. 이때, 온도변화시 소요되는 시간은 1분 이내로 한다.First, the main etching of the wafer is performed at room temperature, and then overetched at a low temperature by using the refrigerant line 30. And the temperature change to room temperature is performed using the heating line 32 in order to perform main etching of the next wafer. At this time, the time required to change the temperature is within 1 minute.
제4a도에 도시한 바와 같이 반도체 기판(40) 상에 제 1절연층(41)을 형성하고, 상기 제 1절연체(41) 상에 제 1폴리 실리콘층(42)을 형성한다.As shown in FIG. 4A, a first insulating layer 41 is formed on the semiconductor substrate 40, and a first polysilicon layer 42 is formed on the first insulator 41.
그리고 상기 제 1폴리 실리콘층(42)상에 포토레지스트(Photoresist)을 형성하고, 노광 및 현상 공정을 이용하여 패터닝한 후, 포토레지스트 패턴(43)을 형성한다.After the photoresist is formed on the first polysilicon layer 42 and patterned using an exposure and development process, a photoresist pattern 43 is formed.
이어, 도 4b에 도시한 바와 같이 상기 포토레지스트 패턴(43)을 마스크로 하여 제 1폴리 실리콘층(42)을 메인에칭한다. 이때, 제 1폴리 실리콘층(42)은 건식식각 또는 습식식각을 이용한다.Next, as shown in FIG. 4B, the first polysilicon layer 42 is main-etched using the photoresist pattern 43 as a mask. At this time, the first polysilicon layer 42 uses dry etching or wet etching.
여기서 상기 제 1절연층(41)상에 건식식각 또는 습식식각에 사용되고 남은 잔류물(44)이 발생하며, 메인에칭은 상온에서 실시한다.Here, the residue 44 used for dry etching or wet etching is generated on the first insulating layer 41, and main etching is performed at room temperature.
이어서 도 4c에 도시한 바와 같이, 상기 포토레지스트 패턴(43) 및 남아있는 잔류물(44)을 제거하기 위해 극저온에서 오버에칭을 실시하여 커패시터의 하부전극을 형성한다.Subsequently, as shown in FIG. 4C, the lower electrode of the capacitor is formed by overetching at a cryogenic temperature in order to remove the photoresist pattern 43 and the remaining residue 44.
이때, 오버에칭시 온도는 -50~-100℃이고, 온도변화시 소요되는 시간은 1분 이내로 한다.At this time, the temperature at the time of over etching is -50 ~-100 ℃, the time required to change the temperature is within 1 minute.
한편, 실린더(Cylinder) 구조의 커패시터 제조에 있어서도 같은 방법을 이용하여 형성하며, 도전체로 폴리 실리콘을 사용하여 반도체 소자의 전극 또는 신호라인을 형성하는 반도체 소자에도 적용한다.Meanwhile, the same method is used to manufacture a capacitor having a cylinder structure, and the present invention is also applied to a semiconductor device that forms electrodes or signal lines of a semiconductor device using polysilicon as a conductor.
이와 같은 본 발명의 반도체 제조장치 및 이를 이용한 반도체 소자 제조방법에 있어서는 다음과 같은 효과가 있다.Such a semiconductor manufacturing apparatus of the present invention and a semiconductor device manufacturing method using the same have the following effects.
첫째, 커패시터 하부전극 형성시 폴리 라인에 나칭현상, 언더컷트 또는 네가티브 스로프 형성을 방지하여 효과적으로 폴리 라인의 측면을 수직으로 유지하면서 잔류물을 제거할 수 있다.First, when forming a capacitor lower electrode, it is possible to prevent the formation of a naming phenomenon, an undercut, or a negative slope in the polyline, thereby effectively removing residues while keeping the sides of the polyline vertical.
둘째, 폴리 라인을 사용하는 경우에는 커패시터의 구조에 상관없이 오버에칭에서 사용할 수 있다.Secondly, when using a poly line, it can be used for over etching regardless of the structure of the capacitor.
셋째, 게이트 라인 에칭시에도 적용할 수 있다.Third, the present invention can also be applied at the time of gate line etching.
넷째, 기가(GIGA) 이상의 고집적 회로 제작시에 특히 측면관리에 유리하고 노드 사이의 잔류물에 의한 숏트방지에도 매우 유리하다.Fourth, it is particularly advantageous for side management when fabricating a highly integrated circuit of GIGA or higher, and also for short prevention by residues between nodes.
Claims (6)
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| WO2016080615A1 (en) * | 2014-11-21 | 2016-05-26 | (주)씨앤아이테크놀로지 | Adhesive pad manufacturing apparatus for forming electromagnetic wave shielding film of semiconductor package, and adhesive pad manufacturing method using same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6430226A (en) * | 1987-07-27 | 1989-02-01 | Oki Electric Ind Co Ltd | Dry etching device |
| JPH04199811A (en) * | 1990-11-29 | 1992-07-21 | Mitsubishi Electric Corp | Periphery exposing device for semiconductor wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6430226A (en) * | 1987-07-27 | 1989-02-01 | Oki Electric Ind Co Ltd | Dry etching device |
| JPH04199811A (en) * | 1990-11-29 | 1992-07-21 | Mitsubishi Electric Corp | Periphery exposing device for semiconductor wafer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016080615A1 (en) * | 2014-11-21 | 2016-05-26 | (주)씨앤아이테크놀로지 | Adhesive pad manufacturing apparatus for forming electromagnetic wave shielding film of semiconductor package, and adhesive pad manufacturing method using same |
| KR20160061063A (en) * | 2014-11-21 | 2016-05-31 | (주) 씨앤아이테크놀로지 | Apparatus for Manufacturing Adhesive-Pad for EMI shielding of Semiconductor Packages and Method for Manufacturing Adhesive-Pad Using the Same |
| KR101666786B1 (en) * | 2014-11-21 | 2016-10-17 | (주) 씨앤아이테크놀로지 | Apparatus for Manufacturing Adhesive-Pad for EMI shielding of Semiconductor Packages and Method for Manufacturing Adhesive-Pad Using the Same |
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