KR100248202B1 - Chip scale package and method foe forming the same - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a chip scale package using a strip-shaped laminated printed circuit board. A chip-sized package is a substrate having a plurality of slot holes formed at a central portion thereof, the substrate having a second surface opposite to the first surface and the first surface, and an adhesive tape attached to the first surface on both sides of the slot hole. A substrate having a signal pattern formed on the second surface, having a plurality of electrical contacts, and coated with an insulating resist to insulate portions other than the signal pattern; An integrated circuit chip comprising a wire bonding pad attached to the first surface on the substrate by an adhesive tape; A plurality of conductive bond wires electrically connecting a wire bonding pad of the integrated circuit chip and a signal pattern on the substrate through the slot holes; And an insulating layer formed by curing an underfill solution that fills a slot hole of the multilayer board on which the plurality of conductive bond wires are arranged.

Description

Chip-sized package and its formation method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package, and more particularly, to a chip scale package using a stripped laminated printed circuit board.

Conventionally, the structure of a chip scale package or chip size package for accommodating a LOC type chip has an adhesive tape for LOC on one surface of the integrated circuit chip 1, as shown in FIG. (2) is attached, the lead frame (3) is attached to the adhesive tape (2) for LOC and arranged so as to extend outwardly, and the bonding circuit (4) and the lead frame (3) by the bonding wire (4) This is electrically connected. In addition, the parts are molded of molding resin 5.

The chip size package for accommodating the LOC chip of the related art has the following structure, and has the following problems.

First, all LOC package processes such as dicing saw, die attach, wire bonding, molding, trim, plating, synergy, visual inspection, and shipment should be performed sequentially.

Second, workability is degraded because lead frames having a predetermined shape (aka; down-set) in advance are used.

Third, there is a high probability that voids will occur between the chip and the lead frame.

Fourth, when the mold is concerned, deformation of the lead frame is concerned.

Fifth, package chipping or cracks are likely to occur near the lead frame during the trimming process.

Sixth, it is difficult to control the thickness of the package.

In order to solve the above problems, the present invention does not use flip chip technology, but uses a conventional wire bonding technology, and uses LOC type chips for LOC assembly technology and BGA (ball gird array package technology). In order to provide a method for forming a CSP and a CSP for accommodating a LOC type chip, the application of a combination of the above techniques is a technical principle.

1 is a schematic cross-sectional view for explaining the structure of a chip sized package containing a conventional LOC type chip.

Figure 2 is a plan view showing a styrop substrate used in one embodiment of the present invention.

3A to 3C are enlarged cross sectional views, a plan view, and a bottom view showing one unit for explaining the structure of the strip-shaped substrate of FIG. 2 in detail;

4A and 4B are cross-sectional views and plan views illustrating a state in which adhesive tape is attached to both sides of a slot hole of a substrate according to one embodiment of the present invention.

5A and 5B are cross-sectional views and plan views showing a state in which an integrated circuit chip is mounted at a position corresponding to a slot hole of a substrate on an adhesive tape according to an embodiment of the present invention.

6A and 6B are a cross-sectional view and a plan view for explaining a wire bonding state according to an embodiment of the present invention.

7A and 7B are cross-sectional views and plan views illustrating an insulating layer formed by curing an under fill solution in a slot hole portion of a substrate on which wires are arranged according to one embodiment of the present invention;

8A and 8B are a cross-sectional view and a plan view for showing a ball attached state according to an embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

21: substrate 22: adhesive tape

23: integrated circuit chip 24: bond wire

25: bond wire 26: ball

21A: Slot Hole

An object of the present invention is a substrate having a plurality of slot holes formed in a central portion, the substrate having a second surface opposite to the first surface and the first surface, and adhesive tape is attached to the first surface on both sides of the slot hole. A substrate having a signal pattern formed on the second surface and having a plurality of electrical contacts; An integrated circuit chip comprising a wire bonding pad attached to the first surface on the substrate by an adhesive tape; A plurality of conductive bond wires electrically connecting a wire bonding pad of an integrated circuit chip and a signal pattern on the substrate through the slot holes; And an insulating layer formed by curing an underfill solution filling a slot hole of a laminated substrate having a plurality of conductive bond wires arranged thereon.

Another object of the present invention is to form a slot hole to expose the wire bonding pad of the integrated circuit chip in the central portion of the substrate; A resist is printed on the first surface of the substrate, and a signal pattern is formed on a second surface corresponding to the opposite surface of the first surface of the substrate, and the portion to which the wire bonds and the sole ball are mounted on the second surface of the substrate. Insulating by applying a solder resist except for; Attaching an adhesive tape on the first surface of the substrate to attach the integrated circuit chip to both of the slot holes formed in the central portion of the substrate; Mounting an integrated circuit chip on a substrate having an adhesive tape attached to the first surface; Connecting the wires between the wire bonding pads arranged between the slot holes formed in the center portion of the substrate and the wire bonding portions exposed on the second surface of the substrate with wires; Filling a narrow gap between the integrated circuit chip and the substrate by injecting an underfill solution into a slot hole formed in a central portion of the substrate; Drying and curing the underfill solution; Dotting the flux to the soul ball mount portion formed on the second surface of the substrate and mounting the plurality of soul balls; And attaching the sole ball on the substrate.

According to the exemplary embodiment of the present invention, the wire bonding pad of the integrated circuit chip and the signal pattern of the substrate are electrically connected to each other through a slot hole formed on the substrate, thereby reducing the size of the package and further improving the integrated circuit chip. By injecting the underfill solution using a capillary phenomenon between the substrate and the substrate, the voids in the package or the deformation problem in the ceramic substrate can be eliminated.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the substrate used in the present embodiment will be described with reference to Fig. 2, where a plurality of slot holes A are formed at a predetermined position, and the break line of the break line can be formed in the trim process. Another slot hole B serving as a role is formed around each slot hole A. FIG. Index holes C are formed at the corners of the rectangle formed by the slot holes B, respectively.

3A to 3C show enlarged cross-sectional views, top views, and bottom views, respectively, illustrating one unit of the substrate of FIG. 2 in order to explain the structure of the substrate in detail.

As shown in Fig. 3A, the substrate 21 is composed of two layers. However, in some cases, the substrate may be made of one layer or a multilayer of two or more layers. In addition, the substrate may be strip-like or matrix-shaped.

The wire slot hole 21A is formed in the center of the substrate 21 so that the wire bonding pad of the LOC type integrated circuit chip is visible. The first surface of the substrate 21 is printed with a resist 21B, preferably a soul resist. A wiring pattern, that is, a signal pattern 21C, is formed on the second surface opposite to the first surface of the substrate 21. Here, the signal pattern includes a wire bonding part 211, a soul ball attach part 212, and a circuit line part 213. In order to insulate the second surface from the outside, portions other than the wire bonding portion 211 and the soul ball attach portion 212 are coated with a resist 214, preferably a soul resist.

As shown in Figs. 4A and 4B, an adhesive tape 22, preferably an LOC adhesive tape, capable of attaching the integrated circuit chip to both sides of the slot hole 21A formed in the central portion of the substrate 21, is preferable. Is attached.

5A and 5B, on the adhesive tape 22, an integrated circuit chip 23 is mounted at a position corresponding to the slot hole 21A of the substrate 21. As shown in FIG.

The wire bonding pads 23A are arranged on the integrated circuit chip 23 in a row, and the wire bonding pads 23A are wire bonding portions 211 of the signal pattern 21C formed on the second surface of the substrate. And are electrically connected by wires 24. In the present embodiment, the size of the package can be reduced by forming a structure in which the integrated circuit chip 23 and the signal pattern 21C on the substrate 21 are connected through the slot hole 21A formed on the substrate 21. (See Figures 6A and 6B).

In addition, as shown in FIGS. 7A and 7B, an insulating layer 25 formed by curing an under fill solution is arranged in the slot hole 21A portion of the substrate 21 on which the wires 24 are arranged. It is.

To the sole ball attach portion 212 formed on the second surface of the substrate 21, as shown in Figs. 8A and 8B, a ball 26, preferably a soul ball, is attached.

9 shows a perspective view of a packaged integrated circuit chip device fabricated in accordance with the present invention. According to this embodiment, the package size can be reduced to the degree of CSP.

Next, the steps for manufacturing the chip size package having the laminated substrate will be described sequentially.

First, as shown in FIG. 3A, a wire slot hole 21A is formed in the center portion of the substrate 21 so that the wire bonding pad of the LOC type integrated circuit chip is visible. In this case, the substrate may be formed of one layer or a multilayer of two or more layers. The substrate may also be strip-like or matrix-shaped.

On the other hand, a resist 21B, preferably a soul resist, is printed on the first surface of the substrate 21. In addition, the signal pattern 21C is formed on the second surface opposite to the first surface of the strip-shaped substrate 21. Here, the signal pattern includes a wire bonding part 211, a soul ball attach part 212, and a circuit line part 213. Then, in order to insulate the second surface from the outside, the resist 214 and the soul resist are applied to portions except the wire bonding portion 211 and the soul ball attach portion 212. Prior to forming the signal pattern on the strip substrate and the slot hole on the substrate, the signal pattern may first be formed by a conventional PCB pattern forming method.

Next, as shown in Figs. 4A and 4B, an adhesive tape 22, preferably LOC, capable of attaching the integrated circuit chip around both sides of the slot hole 21A formed in the central portion of the substrate 21, preferably Attach adhesive tape for.

5A and 5B, the integrated circuit chip 23 is mounted on the adhesive tape 22 at a position corresponding to the slot hole 21A of the substrate 21. As shown in FIG.

As shown in FIGS. 6A and 6B, the wire bonding pattern 23A on the integrated circuit chip 23 and the wire bonding portion 211 of the signal pattern 21C formed on the second surface of the substrate are electrically viewed. It is connected by the wire 24.

After the wire bonding is completed, as shown in Figs. 7A and 7B, an under-fill solution, preferably in the slot hole 21A portion of the strip-shaped substrate 21 on which the wire 24 is arranged, is preferred. An epoxy resin is injected using a dispenser and dried to cure the underfill solution. At this time, the underfill solution is filled with a narrow gap between the collecting circuit chip and the laminated substrate by capillary action. In the ball embodiment, the underfill solution is injected to the extent that it can be filled to the end line of the integrated circuit chip.

8A and 8B, the finished product is doped with a flux to the sole ball etch portion 212 formed on the second surface of the substrate 21, and a plurality of balls 26, Preferably, after mounting the sole ball, the sole ball 26 is attached onto the substrate by passing through an infrared radition-reflow furnace. At this time, the laminated board used can work in the form of a strip or matlips type, and after the work is completed, the unit is formed by performing a trimming process using slot holes (break lines) on the previously formed board. (singulation)

According to an embodiment of the present invention, the structure of electrically connecting the wire bonding pad of the integrated circuit chip and the signal pattern of the substrate through a slot hole formed on the substrate, it is possible to reduce the size of the package, and Capillary action is used to inject the underfill solution between the substrates to eliminate voids in the package or deformation problems in the ceramic substrate.

Claims (13)

A substrate having a second surface opposite to the first surface and the first surface, the substrate having a plurality of slot holes formed in a central portion thereof, the substrate having a second surface opposite to the first surface and the first surface, wherein the slot hole Adhesive tape is attached to both first surfaces, a signal pattern is formed on the second surface, has a plurality of electrical contacts, and an insulating resist is applied to ablate portions other than the signal pattern. Board; An integrated circuit chip comprising a wire bonding pad attached to the first surface on the substrate by an adhesive tape; A plurality of conductive bond wires electrically connecting a wire bonding pad of the integrated circuit chip and a signal pattern on the substrate through the slot holes; And an insulating layer formed by curing an underfill solution that fills the slot hole of the multilayer substrate on which the plurality of conductive bond wires are arranged. The chip size package of claim 1, wherein the substrate is one substrate or two or more laminated substrates. 3. A chip sized package as claimed in claim 1 or 2, wherein the substrate is strip or matrix type. 2. The chip sized package of claim 1, wherein the insulating resist is a Soul Resist. The chip sized package of claim 1, wherein the adhesive tape is an adhesive tape for LOC. The chip sized package of claim 1, wherein the plurality of electrical contacts formed on the substrate are balls. 7. The chip sized package of claim 6, wherein the ball is a soul ball. The chip size package of claim 1, wherein the insulation layer is an epoxy resin. The chip sized package of claim 1, wherein the insulating layer has a height equal to an end line of the integrated circuit chip. Forming a slot hole in the center portion of the substrate to expose the wire bonding pad of the integrated circuit chip; A resist is printed on a first surface of the substrate, a signal pattern is formed on a second surface corresponding to an opposite surface of the first surface of the substrate, and a portion and a sole ball that are wire-bonded to a second surface of the substrate are formed. Applying insulation by applying a solder resist except for the mounted portion; Attaching an adhesive tape on the first surface of the substrate to attach the integrated circuit chip to both sides of the slot hole formed in the central portion of the substrate; Mounting an integrated circuit chip on a substrate having an adhesive tape attached to the first surface; Connecting a wire between the wire bonding pads arranged between the slot holes formed in the center portion of the substrate and the wire bonding portions exposed on the second surface of the substrate; Filling a narrow gap between the integrated circuit chip and the substrate by injecting an underfill solution into a slot hole formed in a central portion of the substrate; Drying and curing the underfill solution; Dotting flux to a soul ball mount portion formed on a second surface of the substrate and mounting a plurality of soul balls; And attaching the sole ball on a substrate. The method of claim 10, wherein the underfill solution is an epoxy resin. The method of claim 10, wherein the injection amount of the underfill solution is an amount that can be filled to an end line of the chip. 11. The method of claim 10, wherein attaching the sole ball onto a substrate is accomplished by passing an infrared radition-reflow furnace.

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